CN103946971B - Method for forming self-aligned contacts and local interconnects - Google Patents

Abstract

The present invention provides a kind of process for fabrication of semiconductor device, it includes forming insulation mandrel above replacement metal gates on a semiconductor substrate, and wherein first grid (104) has source electrode and drain electrode and at least one second grid (104 ') and the isolation of described first grid.Mandrel spacer (124) is formed around each insulation mandrel.Described mandrel and mandrel sept include the first insulating materials.Second insulating barrier (126) with the second insulating materials is formed above transistor.One or more first grooves are formed by removing described second insulating materials between described insulation mandrel, thus are connected to described source electrode and the drain electrode of described first grid.Second groove by remove above described second grid there is described first insulating materials and the part of described second insulating materials is formed, thus be connected to described second grid.Described first groove and described second trench fill have conductive material, are connected to the described source electrode of described first grid and first contact (132) of drain electrode and the second contact (142) being connected to described second grid to be formed.

Description

Method for forming self-aligned contacts and local interconnects

Background of the invention

field of invention

The present invention relates generally to semiconductor processes for forming transistors, and more particularly to processes for forming trench contacts and local interconnects of replacement gate structures on semiconductor substrates.

Related technical description

Transistors such as planar transistors have been at the heart of integrated circuits for decades. Due to advances in process development and the need to increase feature density, the size of individual transistors has steadily decreased. The current scaling uses 32nm technology, and development is still moving towards 20nm and beyond technologies such as 15nm technology.

The use of replacement gate processes (flows) is becoming more common as they avoid some of the problems found in gate first processes. For example, a replacement gate process can avoid problems associated with the stability of the work function material used in the gate. However, the replacement gate process may require the insertion of new process modules such as CMP (Chemical Mechanical Polishing).

Additionally, most replacement gate processes suffer from alignment issues when making trench contacts and/or local interconnect connections to the gate. For example, most replacement gate processes are not self-aligned and can easily fail due to misalignment during processing. Replacement gate processes can also be difficult to pattern bidirectional local interconnects and/or reduce the number of interfacial layers from the local interconnects to the gate or the source/drain of the gate.

To address some of these issues, many process flows have been tailored in an attempt to create self-aligned trench contacts extending over the gate for less complex local interconnect flows. However, such process flows are usually very complex, have many resistive interfaces, and have high manufacturing costs due to the complex process flow. Additionally, misalignment or other errors due to process complexity result in low manufacturing yields because these processes may have tightly constrained design and/or alignment rules.

FIG. 1 depicts an embodiment of a prior art transistor 50 in which a replacement gate structure 52 is located on a semiconductor substrate 54 . Replacement gate structure 52 includes a gate 56 surrounded by gate spacers 58 . Source/drain 60 may be located in well region 62 of substrate 54 . Additionally, one or more gates may be located over isolation region 64 of substrate 54 .

Trench contacts 66 are used to contact source/drain 60 with local interconnect 68A. Local interconnect 68A may be merged with local interconnect 68B to provide routing to local interconnect 68C connected to gate 56'.

As can be seen in FIG. 1 , any misalignment in the trench contacts 66 can easily result in a short to the gate 56 . Therefore, restrictive design/alignment rules must be in place to suppress shorting between trench contacts 66 and gates 56 . Additionally, alignment issues between local interconnect 68C and gate 56' may be prone to alignment issues without the use of restrictive alignment rules.

Furthermore, as seen in FIG. 1 , the routing between local interconnect 68A, local interconnect 68B, local interconnect 68C can be very complex and involve many process steps. The multitude of process steps can increase the likelihood of forming resistive interfaces between local interconnects and/or alignment problems between local interconnects.

Therefore, there is a need for a method to self-align and extend the trench contacts to the source/drain over the gate.

Implementation overview

In certain embodiments, a semiconductor device fabrication process includes providing a transistor comprising a plurality of replacement metal gates on a semiconductor substrate, wherein a first gate has a source and a drain and at least one second The gate is isolated from the first gate. The transistor includes a gate spacer of a first insulating material surrounding each gate, and a first insulating layer of a second insulating material between the gate and the gate spacer. At least some of the second insulating material covers the source and drain of the first gate.

One or more insulating mandrels are formed and aligned over the gate. The insulating mandrel includes the first insulating material. Mandrel spacers are formed around each insulating mandrel. The mandrel spacer includes the first insulating material. A second insulating layer having the second insulating material is formed over the transistor.

one or more first trenches connected to the source and drain of the first gate by removing the second insulating material from portions of the transistor between the insulating mandrels to form. A second trench connected to the second gate is formed by removing a portion of the first insulating material and the second insulating material over the second gate. The first trench and the second trench are filled with a conductive material to form first contacts to the source and drain of the first gate and to the second gate the second contact point.

In certain embodiments, a third insulating layer is formed over the transistor. A third trench is formed by removing a portion of the third insulating layer, the third trench passing through the third insulating layer to the first contact and the second contact. A local interconnect to the first contact and the second contact is formed by depositing a conductive material in the third trench formed through the third insulating layer.

In certain embodiments, a semiconductor device includes a plurality of replacement metal gates on a semiconductor substrate. A first gate has a source and a drain and at least one second gate is isolated from the first gate. A gate spacer having a first insulating material surrounds each first gate. A first insulating layer having a second insulating material is between the gate spacers. At least some of the second insulating material covers the source and drain of the first gate.

One or more insulating mandrels are aligned over the gate. The insulating mandrel includes the first insulating material. A mandrel spacer surrounds each insulating mandrel and includes the first insulating material. One or more first contacts to the source and drain of the first gate pass through the first insulating layer between the mandrel spacers. A second contact to the at least one second gate passes through the first insulating material over the second gate. A third insulating layer is over the transistor, and one or more local interconnects contact the first and second contacts through the third insulating layer.

In some embodiments, one or more of the above process steps are completed, and/or one or more components of the semiconductor device are formed using a CAD (computer-aided design) designed resist pattern, the resist The pattern defines regions to be removed and/or deposited during processing. For example, the CAD pattern may be used to define areas for forming the insulating mandrels and/or the mandrel spacers. In some embodiments, a computer readable storage medium stores a plurality of instructions that, when executed, generate one or more of the resist patterns.

Providing self-aligned trench contacts extending over the gate allows for a simpler local interconnect flow for connecting the trench contacts and the open gate. Using the process embodiments described herein allows for lower gate-to-trench contact and local interconnect coupling capacitance and a reduction in the number of resistive interfaces between layers compared to previous replacement gate flow connection schemes. Additionally, the process embodiments described herein may provide better manufacturing yields by reducing the likelihood of misalignment between contacts and providing a simpler process than previous replacement gate flow connection schemes.

Brief description of the drawings

Figure 1 depicts a cross-sectional side view of a prior art transistor.

2 depicts a cross-sectional side view of an embodiment of a replacement metal gate structure on a silicon substrate.

3 depicts a cross-sectional side view of an embodiment of an insulating layer formed over a gate structure.

4 depicts a cross-sectional side view of an alternative embodiment of an insulating layer with an underlying thin insulating layer formed over a gate structure.

5 depicts a cross-sectional side view of an embodiment of an insulating mandrel formed over a gate structure.

6 depicts a cross-sectional side view of an embodiment of insulating material deposited over an insulating mandrel.

7 depicts a cross-sectional side view of an embodiment of an insulating mandrel and mandrel spacer formed over a gate structure.

8 depicts a cross-sectional side view of an embodiment of an insulating layer deposited over an insulating mandrel and mandrel spacers.

9 depicts a cross-sectional side view of an embodiment of a trench formed in an insulating layer deposited over an insulating mandrel and a mandrel spacer.

10 depicts a cross-sectional side view of an embodiment of a trench formed in an insulating layer filled with a conductive material.

11 depicts a cross-sectional side view of an embodiment of a transistor after planarization.

12 depicts a cross-sectional side view of an embodiment of an insulating layer deposited over the planarizing transistor depicted in FIG. 11 .

13 depicts a cross-sectional side view of an embodiment of a second insulating layer deposited over the insulating layer depicted in FIG. 12 .

14 depicts a cross-sectional side view of an embodiment of a trench formed through the insulating layer depicted in FIG. 13 .

15 depicts a cross-sectional side view of an embodiment of more trenches formed through the insulating layer depicted in FIG. 13 .

16 depicts a cross-sectional side view of an embodiment of a trench formed through a mandrel and a mandrel spacer.

17 depicts a cross-sectional side view of an embodiment of a transistor 100 with local interconnects to the source/drain and gate.

FIG. 18 depicts an alternative embodiment of transistor 100 from the embodiment depicted in FIG. 17 .

19 depicts a cross-sectional side view of an embodiment of a trench formed through an insulating layer to a source/drain using a resist pattern.

20 depicts a cross-sectional side view of an embodiment of a gate open trench through an insulating layer to a gate.

21 depicts a cross-sectional side view of the embodiment depicted in FIG. 20 with the resist pattern removed.

22 depicts a cross-sectional side view of an embodiment of trenches including gate open trenches formed in an insulating layer filled with a conductive material.

23 depicts a cross-sectional side view of the embodiment of the transistor depicted in FIG. 22 after planarization.

24 depicts a cross-sectional side view of an embodiment of an insulating layer deposited over the planarizing transistor depicted in FIG. 23 .

25 depicts a cross-sectional side view of an embodiment of a trench formed through the insulating layer depicted in FIG. 24 using a resist pattern.

26 depicts a cross-sectional side view of an embodiment of another trench formed through the insulating layer depicted in FIG. 25 using a resist pattern.

27 depicts a cross-sectional side view of the embodiment depicted in FIG. 26 with the resist pattern removed.

28 depicts a cross-sectional side view of an embodiment of the trench depicted in FIG. 27 filled with a conductive material.

29 depicts a cross-sectional side view of the embodiment of the transistor depicted in FIG. 28 after planarization.

While the invention is described herein by way of illustration of certain embodiments and illustrative drawings, those skilled in the art will recognize that the invention is not limited to the described embodiments or drawings. It should be understood that the drawings and detailed description thereof are not intended to limit the invention to the particular forms disclosed, but on the contrary, the invention is to cover the spirit and the invention as defined by the appended claims. All modifications, equivalents, and alternatives within the scope. Any headings used herein are for organizational purposes only and are not intended to limit the scope of the description or claims. As used herein, the word "may" is used in a permissive sense (ie, meaning having some possibility), rather than a mandatory sense (ie, meaning must). Similarly, the words "include/including/includes" mean including but not limited to.

Implementation details

2 depicts a cross-sectional side view of an embodiment of a replacement metal gate structure on a silicon substrate forming transistor 100 . Transistor 100 may be any type of transistor known in the art. For example, transistor 100 may be a planar transistor, such as a planar field effect transistor (FET), or a non-planar transistor, such as a FinFET transistor.

In certain embodiments, transistor 100 includes a replacement metal gate structure 102 formed on substrate 101 . The gate structure 102 can be formed on the substrate 101 by a process known in the art, such as but not limited to a replacement gate process. As shown in FIG. 2 , the gate structure 102 includes a gate 104 surrounded by gate spacers 106 . Gate 104 may be formed over well region 108 (active region of transistor 100 ) of substrate 101 and/or over trench isolation 110 (isolation region of transistor). In some embodiments, trench isolation 110 may be a shallow trench isolation.

In certain embodiments, source/drain 112 is formed in well region 108 of substrate 101 . In certain embodiments, the source/drain includes an embedded silicon germanium (eSiGe) layer 112A and a nickel suicide contact 112C separated by a platinum barrier layer 112B. Other types of source/drains may also be used as known in the art.

In some embodiments, the gate 104 is a metal gate 104A (eg, a replacement metal gate) formed on a high-κ (high dielectric constant) material 104B, only labeled in FIG. 2 for clarity. The leftmost gate. As described above, metal gate 104A and high-κ material 104B may be formed using a replacement gate process. The metal gate 104A may include a metal such as, but not limited to, titanium, tungsten, titanium nitride, or combinations thereof. The high-κ material 104B may include a dielectric such as, but not limited to, hafnium silicate, zirconium silicate, hafnium dioxide, zirconium dioxide, or combinations thereof.

As shown in FIG. 2 , gate 104 and gate spacer 106 are surrounded by insulating layer 114 . In certain embodiments, the gate spacers 106 and the insulating layer 114 are formed of different insulating materials such that there is etch selectivity between the gate spacers and the insulating layer. For example, gate spacers 106 may be formed of silicon nitride, while insulating layer 114 is silicon oxide formed by TEOS (tetraethyl orthosilicate) deposition.

In certain embodiments, the replacement metal gate structure 102 shown in FIG. 2 is planarized, for example, by chemical mechanical polishing (CMP). As shown in FIG. 3 , after the gate structure 102 is planarized, an insulating layer 116 is formed (deposited) over the gate structure. In some embodiments, the insulating layer 116 includes silicon nitride or the same insulating material as the gate spacers 106 . The insulating layer 116 may be formed using methods known in the art such as, but not limited to, plasma deposition. In certain embodiments, insulating layer 116 is formed using a planar (non-conforming) deposition process. An insulating layer 116 is formed over the gate structure 102 such that the gate structure is encapsulated in the insulating layer.

As shown in FIG. 4 , in some embodiments, a thin insulating layer 118 is formed (deposited) over the gate structure 102 between the gate structure and the insulating layer 116 . The thin insulating layer 118 may include silicon oxide or the same insulating material as the insulating layer 114 .

As shown in FIG. 5 , following deposition of insulating layer 116 , selected portions of insulating layer 116 may be removed to form insulating mandrel 120 over gate 104 . For simplicity, not every reference to all components is shown in the remaining figures (eg, not every gate 104 or gate spacer 106 is shown). Each mandrel 120 may be formed to have approximately the same width as its underlying gate 104 . In certain embodiments, each mandrel 120 is at least as wide as its underlying gate 104 (e.g., the mandrel has a minimum width at least as large as the width of the underlying gate, but the mandrel may be slightly wider than the underlying gate). Thus, the edge of each mandrel 120 extends at least past the edge of its underlying gate 104 . In some cases, one or more mandrels 120 have a width that is less than the width of the underlying gate due to alignment issues and/or other manufacturing issues. The width of the mandrel can be assessed using in-line measurement techniques known in the art. In cases where the mandrel is not as wide as the underlying gate, the smaller width can be compensated for by the width of the mandrel spacer during subsequent processing steps described herein.

The mandrel 120 may be formed by patterning the insulating layer 116 with a resist pattern or mask designed to select portions of the insulating layer to be removed, leaving the remaining portions in the gate 104. A mandrel is formed above. The resist pattern or mask used to form the mandrel 120 may be a CAD (Computer Aided Design) designed pattern or mask (eg, a CAD designed resist pattern). In certain embodiments, a computer-readable storage medium stores a plurality of instructions that, when executed, generate a resist pattern or mask, such as, but not limited to, a resist pattern for forming a CAD design of the mandrel 120. etch patterns or masks. In certain embodiments, the resist pattern and/or mask used to form mandrel 120 is the same resist pattern and/or mask used to form gate 104 . Using the same resist pattern and/or mask allows mandrel 120 to have substantially the same critical dimension (eg, width) as gate 104 .

Portions of the insulating layer 116 selected for removal by the resist pattern or mask may be removed by, for example, etching the selected portions of the insulating layer. In some embodiments, the etch of the insulating layer 116 is a timed etch. The etch process may be timed such that the etch stops at the insulating layer 114 . In some embodiments, the etching process used to etch insulating layer 116 is selective between insulating layer 116 and insulating layer 114, such that the insulating material in insulating layer 116 is etched while the insulating material in insulating layer 114 is etched. Not etched. For example, the etching process may etch the silicon nitride used in the insulating layer 116 without etching the silicon oxide used in the insulating layer 114 . The etch process can be timed to stop at the insulating layer 114 so that there is no overetch that can etch into the gate spacers 106 . In certain embodiments, an etch stop layer (such as the thin insulating layer 118 as depicted in FIG. 4 ) is used as a base layer to inhibit overetching during the etching of the insulating layer 116 .

Following formation of the mandrel 120 , an insulating layer 122 is formed (deposited) over the mandrel and insulating layer 114 , as shown in FIG. 6 . In some embodiments, insulating layer 122 includes silicon nitride or the same insulating material as mandrel 120 . The insulating layer 122 may be formed using methods known in the art, such as, but not limited to, plasma deposition. In certain embodiments, insulating layer 122 is formed using a non-planar or conformal deposition process. Using non-planar deposition allows the insulating material to conform to the surface (eg, mandrel 120 ) on which the material is deposited, as shown in FIG. 6 .

Following deposition of insulating layer 122 , portions of the insulating layer are removed (etched back) to form mandrel spacers 124 , as shown in FIG. 7 . Mandrel spacers 124 may be formed around the mandrel 120 and adjoin the sides (edges) of the mandrel. Mandrel spacers 124 may be formed by removing portions of insulating layer 122 with an etch process that etches downward faster than it etches sideways. Thus, the etch process preferably removes insulating layer material from horizontal surfaces faster than vertical surfaces such as sidewalls. The final width of the mandrel spacer 124 can be controlled by controlling etch parameters such as etch bias and etch time during the etch process.

In certain embodiments, the mandrel spacer 124 has a similar height as the mandrel 120 . Due to the non-planar (conformal) deposition of the insulating layer 122 as shown in FIG. 6 , the mandrel spacer 124 has a tapered (sloped) profile from the top to the bottom of the spacer, as shown in FIG. 7 . Thus, the mandrel spacer 124 is wider at the bottom and narrower at the top.

In certain embodiments, the mandrel spacers 124 are formed with a width such that the edges of the mandrel spacers 124 extend beyond the edges of the gate spacers 106 . The width of the mandrel spacers 124 can be adjusted by adjusting the etching process used to remove the portion of the insulating layer 122 (eg, controlling the etch rate and/or selectivity during the etching process) and/or by adjusting the etching process used to form the mandrel spacers. The thickness of the insulating layer 122 is adjusted during the deposition of the insulating layer. The width of the mandrel spacers 124 can be adjusted by adjusting the etching process and/or deposition thickness, allowing the width of the mandrel spacers to be controlled on a lot by lot or die basis.

Following the formation of the mandrel spacers 124 , an insulating layer 126 is formed (deposited) over the mandrel 120 , the mandrel spacers, and the insulating layer 114 , as shown in FIG. 8 . In some embodiments, insulating layer 126 includes silicon oxide or the same insulating material as insulating layer 114 . The insulating layer 126 may be formed using methods known in the art, such as, but not limited to, TEOS deposition. In certain embodiments, insulating layer 126 is formed using a planar deposition process. Insulating layer 126 may be formed such that mandrel 120 and mandrel spacer 124 are encapsulated in the insulating layer.

After the formation of the insulating layer 126 , a trench 128 may be formed through the insulating layer 126 and the insulating layer 114 to the source/drain 112 , as shown in FIG. 9 . Because insulating layer 126 and insulating layer 114 are formed of the same insulating material, trench 128 may be formed using a single etching process. Trenches 128 may use an etch that selectively etches the insulating material (eg, silicon oxide) in insulating layer 126 and insulating layer 114 without etching the insulating material (eg, silicon nitride) in mandrel 120 and mandrel spacer 124 . process to form.

At least a portion of the mandrel spacer 124 is exposed in the trench 128 . Due to the presence of the mandrel spacer 124 and the sloped profile of the mandrel spacer, the trench 128 has a sloped profile from a wider top to a narrower bottom. Thus, the slope of the trench 128 is determined by the slope of the mandrel spacer 124 . Using selective etching to form trenches 128 inhibits removal of portions of mandrel spacers 124 formed over the edges of gates 104 and gate spacers 106 . Maintaining the width and profile of the mandrel spacer 124 in the trench 128 inhibits the exposed portion of the gate 104 from contacting the material used to fill the trench, even though the trench, the mandrel 120, the mandrel spacer There is some degree of misalignment in the object or the gate.

After formation of the trench 128, the trench may be filled with a conductive material 130, as shown in FIG. 10 . The conductive material 130 may include, but is not limited to, tungsten, copper, titanium, titanium nitride, or combinations thereof. Conductive material 130 may be formed as a layer of conductive material using methods known in the art, such as, but not limited to, sputter deposition or electroless deposition. In certain embodiments, conductive material 130 is formed using a planar deposition process that encapsulates underlying layers in the conductive material. Encapsulating the underlying layers in conductive material 130 ensures that trenches 128 are completely filled with the conductive material.

After filling trenches 128 with conductive material 130 , transistor 100 may be planarized, as shown in FIG. 11 . Transistor 100 may be planarized by, for example, CMP of the transistor. Planarization of transistor 100 may include removal of material such that top portions of mandrel 120 and mandrel spacer 124 are exposed at the planar surface. After planarization of transistor 100 , conductive material 130 in trench 128 forms trench contact 132 to source/drain 112 .

Trench contacts 132 are formed to have the profile of trenches 128 , wherein the trench contacts are wider at the top than at the bottom. Accordingly, the trench contacts 132 have a slope determined by the slope of the mandrel spacer 124 . The sloped profile of the mandrel spacer 124 and the trench contact 132 inhibits the conductive material 130 in the trench contact 132 from contacting (shorting) the gate 104 . For example, shorting between the trench contact and the gate can occur in prior art devices if there is any misalignment during the formation of the gate, the trench contact, or during other process steps. As shown in FIG. 11 , because the mandrel spacer 124 extends beyond the edge of the gate 104 (and gate spacer 106 ) with a wider bottom profile, there is little or no contact between the trench contact 132 and the gate 104. There is a possibility of shorting, and the trench contacts are self-aligning.

In certain embodiments, capacitive coupling from the gate 104 to the trench contact 132 is reduced due to the reduced CD trench contact bottom created by the slope and width of the mandrel spacer 124 . In some embodiments, the width of the gate 104 is widened. The gate 104 can be widened without increasing the likelihood of shorting the trench contact 132 because the slope and width of the mandrel spacer 124 create a trench contact above the source/drain 112. Self-alignment. Widening the gate 104 can provide less leakage, better power reduction and improved performance characteristics. Self-alignment of the trench contacts 132 also provides improved manufacturing yield (eg, reduced likelihood of manufacturing issues such as shorts or misalignment).

After the planarization process, an insulating layer 134 is formed (deposited) over the planar surface of the transistor 100 as shown in FIG. 12 . In certain embodiments, insulating layer 134 includes silicon nitride or the same insulating material as mandrel 120 and mandrel spacer 124 . The insulating layer 134 may be formed using methods known in the art such as, but not limited to, plasma deposition. In some embodiments, insulating layer 134 is formed using a planar deposition process. The insulating layer 134 may be a thin insulating layer that encapsulates the underlying layers.

In certain embodiments, insulating layer 136 is formed (deposited) over insulating layer 134 , as shown in FIG. 13 . In certain embodiments, insulating layer 136 includes silicon oxide or the same insulating material as insulating layer 114 and insulating layer 116 . The insulating layer 136 may be formed using methods known in the art, such as, but not limited to, TEOS deposition. In some embodiments, insulating layer 136 is formed using a planar deposition process. The insulating layer 136 may be a thick insulating layer that encapsulates the underlying insulating layer 134 .

Following the deposition of insulating layer 136 , trenches 138 are formed through insulating layer 136 and insulating layer 134 to trench contacts 132 , as shown in FIG. 14 . In certain embodiments, trenches 138 are used for local interconnects to trench contacts 132 and source/drains 112 . As shown in FIG. 14, the wide top profile of trench contacts 132 provides more tolerance for alignment between trenches 138 (and local interconnects made using the trenches) and the trench contacts.

In certain embodiments, trenches 138 are formed using a two-step etch process. The first step may etch through insulating layer 136 using insulating layer 134 as an etch stop (silicon oxide etch). A second step may etch through insulating layer 134 (silicon nitride) to trench contact 132 .

In certain embodiments, trenches 140 are formed through insulating layer 136 , as shown in FIG. 15 . Trenches 140 may be formed through insulating layer 136 to insulating layer 134 using insulating layer 134 as an etch stop layer. Trench 140 may be used to form a local interconnect route to gate 104' (the gate on the right in Figure 15). Gate 104' may be isolated from other gates in transistor 100 (e.g., gate 104' is in an isolated region of the transistor and the other gates are in an active region). Combining trenches 140 and trenches 138 over gates other than gate 104' allows the local interconnects to be merged without connecting to gate 104'.

After the formation of the trench 140, a gate open trench 142 may be formed over the gate to connect to the gate 104', as shown in FIG. 16 . Trenches 142 may be gate open trenches. Trench 142 may be formed by etching through mandrel 120 and mandrel spacer 124 over gate 104' using, for example, a silicon nitride etch process. Using trench 142 to connect to gate 104' allows that gate to be selectively connected to other gates in transistor 100. The etch process may be a timed etch process so as to limit significant overetch into the gate spacers 106 surrounding the gate 104'. In certain embodiments, the etch process forming trenches 142 is a self-aligned process, and thus the etch process is selective to the insulating material (eg, silicon nitride) of mandrels 120 and mandrel spacers 124, And the etching process does not etch into the insulating layer 114 (silicon oxide). The combination of trench 138, trench 140 and trench 142 can provide a simple, bi-directional local interconnect scheme for routing between trench contact 132 (contacting source/drain 112) and gate 104'.

In certain implementations, portions of trenches 140 and trenches 138 in insulating layer 136 may be formed using a first etch process for the insulating material in insulating layer 136 . The portion of insulating layer 134 that is in trench 138 may then be removed using a second etch process that utilizes a mask to prevent insulating layer 134 below trench 140 from being etched. In certain embodiments, the second etch process for the insulating layer 134 may also be used to form the trench 142 to the gate 104'.

Filling trenches 138 , trenches 140 , and trenches 142 with conductive material forms local interconnects 144A, 144B, and 144C, as shown in FIG. 17 . In certain embodiments, trench 138, trench 140, and trench 142 are simultaneously filled with a conductive material. The conductive material used to form local interconnect 144A, local interconnect 144B, and local interconnect 144C may be the same material used to form trench contact 132 (eg, tungsten or copper). In some embodiments, local interconnect 144A, local interconnect 144B, and local interconnect 144C are thicker than local interconnects used in other routing schemes due to bidirectional routing and the use of gate open trenches 142 . Using thicker local interconnects can improve transistor performance by providing lower resistance in the local interconnect layers.

In certain embodiments, after filling trenches 138 , 140 , and 142 with conductive material, transistor 100 is planarized (eg, using CMP) to form a planar surface as shown in FIG. 17 . FIG. 18 depicts an alternative embodiment of transistor 100 that differs from the embodiment shown in FIG. 17 by using a thin insulating layer below insulating layer 116 as depicted in the embodiment shown in FIG. 118.

As shown in FIGS. 15-18 , the process of forming the local interconnect 144C includes etching (forming a trench) and/or filling the trench with a relatively large step height. For example, when the gate open trench 142 is formed through the trench 140 in the insulating layer 136 to the gate 104', there is a large step height, as shown in FIG. Such large step heights can be difficult to controllably etch and fill due to large height variations during the process. For example, it may be difficult to control the aspect ratio of gate open trench 142 due to the large height step between the top surface of the device (top of insulating layer 136) and the upper surface of gate 104'.

To overcome the problem of large step heights and to provide a simpler process flow that provides better yields, it may be desirable to provide a process that allows filling of the gate open trenches and trench contacts in a single process. Simultaneous filling of the gate open trenches and trench contacts may provide a simpler process in which step heights are reduced during the etch and fill steps associated with forming local interconnects to the open gates.

19-29 depict cross-sectional side views of the structure of transistor 200 formed using an alternative process for continuing from the structure of transistor 100 depicted in FIG. 8 (eg, transistor 200 is an alternative embodiment of transistor 100). Form trench contacts and local interconnects. After the formation of the insulating layer 126, as shown in FIG. 8, a resist pattern formed by the resist 202 is used to form a trench 128 passing through the insulating layer 126 and the insulating layer 114 to the source/drain 112, as shown in FIG. 19 shown. Trenches 128 may use an etch that selectively etches the insulating material (eg, silicon oxide) in insulating layer 126 and insulating layer 114 without etching the insulating material (eg, silicon nitride) in mandrel 120 and mandrel spacer 124 . process to form.

After the formation of trench 128 , another resist pattern formed from resist 202 may be used to pattern transistor 200 to form gate open trench 142 , as shown in FIG. 20 . The insulating layer 126 may be etched to the mandrel 120 by using a first etch process (eg, a silicon oxide etch process), and then etched through the gate 104' (isolation gate) using a second etch process (eg, a silicon nitride etch process). The upper mandrel 120 and the mandrel spacer 124 form the trench 142 . In certain embodiments, mandrel 120 and mandrel spacer 124 are used as an etch stop layer for the first etch process. In certain implementations, a third etch process is required to etch through the insulating layer 118 (as shown in FIG. 4 ), which may serve as an etch stop layer for the second etch process.

In certain embodiments, one or more of the etch processes are timed etch processes so as to limit significant overetch (eg, into gate spacers 106 surrounding gate 104'). In some embodiments, the second etch process to form the trench 142 is a self-aligned process, so the second etch process is critical to the insulating material (eg, silicon nitride) of the mandrel 120 and the mandrel spacer 124. It is selective, and the second etching process does not etch into the insulating layer 114 (silicon oxide).

Because the gate open trench 142 is formed immediately after the formation of the trench 128, as shown in FIG. The process shown in the embodiment of the gate open trench is a shallower etch that involves some intermediate steps between the formation of the trench 128 and the gate open trench 142 . The shallower etch process provides improved control over the aspect ratio in the gate open trench 142 . As shown in FIG. 20 , resist 202 used to form a resist pattern for gate open trench 142 may fill trench 128 so as to inhibit etching of trench 128 during formation of the gate open trench.

After the formation of the gate open trench 142, the resist 202 may be removed to expose the trench 128 and the gate open trench, as shown in FIG. 21 . Trench 128 and gate open trench 142 may have relatively similar step heights. After the resist is removed, trenches 128 and gate open trenches 142 are filled with conductive material 130 as shown in FIG. 22 . In some aspects, trenches 128 and gate open trenches 142 are filled with conductive material 130 in a single process (eg, the same process).

The conductive material 130 may include, but is not limited to, tungsten, copper, titanium, titanium nitride, or combinations thereof. Conductive material 130 may be formed as a layer of conductive material using methods known in the art, such as, but not limited to, sputter deposition or electroless deposition. In certain embodiments, conductive material 130 is formed using a planar deposition process that encapsulates underlying layers within the conductive material. Encapsulation of underlying layers in conductive material 130 ensures that trenches 128 and gate open trenches 142 are completely filled with the conductive material.

After filling trenches 128 and open gate trenches 142 with conductive material 130 , transistor 200 may be planarized, as shown in FIG. 23 . Transistor 200 may be planarized by, for example, CMP of the transistor. Planarization of transistor 200 may include removal of material such that top portions of mandrel 120 and mandrel spacer 124 are exposed at the planar surface. After planarization of transistor 200, conductive material 130 in trench 128 forms trench contact 132 to source/drain 112, and conductive material 130 in gate open trench 142 forms a connection to gate 104. ' The gate opens to the trench contact 204 .

After the planarization process, insulating layer 134 and insulating layer 136 are formed (deposited) over the planar surface of transistor 200 as shown in FIG. 24 . In certain embodiments, insulating layer 134 includes silicon nitride or the same insulating material as mandrel 120 and mandrel spacer 124 . The insulating layer 134 may be formed using methods known in the art such as, but not limited to, plasma deposition. In some embodiments, insulating layer 134 is formed using a planar deposition process. The insulating layer 134 may be a thin insulating layer that encapsulates the underlying layers.

In certain embodiments, insulating layer 136 includes silicon oxide or the same insulating material as insulating layer 114 and insulating layer 116 . The insulating layer 136 may be formed using methods known in the art such as, but not limited to, TEOS deposition. In some embodiments, insulating layer 136 is formed using a planar deposition process. The insulating layer 136 may be a thick insulating layer that encapsulates the underlying insulating layer 134 .

After the deposition of the insulating layer 136 , a trench 206 is formed through the insulating layer 136 using a resist pattern formed from the resist 202 , as shown in FIG. 25 . In certain embodiments, the insulating layer 134 serves as an etch stop layer for forming the trench 206 through the insulating layer 136 . In some embodiments, insulating layer 134 is not used (no etch stop layer). In embodiments without an etch stop layer, a timed etch is used to control the depth of trenches 206 formed through insulating layer 136 . However, timed etching can have the potential problem of overetching if not properly controlled.

After the formation of the trench 206 , another resist pattern formed from the resist 202 may be used to form a trench 208 through the insulating layer 136 , as shown in FIG. 26 . Trench 208 may be formed through insulating layer 136 to insulating layer 134 using insulating layer 134 as the etch stop, or trench 208 may be formed using a timed etch without insulating layer 134 .

To complete the formation of trenches 206 and 208 , insulating layer 134 may be removed from the trenches using an etching process, and resist 202 may be removed from the surface of transistor 200 , as shown in FIG. 27 . In certain embodiments, the etch process used to remove insulating layer 134 is a timed etch process so as to inhibit overetching into mandrel 120 and mandrel spacer 124 exposed in trench 208 .

In certain embodiments, trenches 206 are used for local interconnects to trench contacts 132 and source/drains 112 . Trench 208 may be used to form a local interconnect route to gate 104' (the gate on the right in FIG. 27). In some embodiments, trench 208 is combined with one of trenches 206 to combine local interconnects for gate 104' (isolation gate) with trench contacts 132 and source/drain 112 local interconnection. The combination of trench 206 and trench 208 can provide a simple, bi-directional local interconnect scheme for routing between trench contacts 132 (contacting source/drain 112) and gate 104'.

After insulating layer 134 is removed, trenches 206 and 208 may be filled with conductive material 210 , as shown in FIG. 28 . The conductive material 210 may include, but is not limited to, tungsten, copper, titanium, titanium nitride, or combinations thereof. Conductive material 210 may be formed as a layer of conductive material using methods known in the art, such as, but not limited to, sputter deposition or electroless deposition. Conductive material 210 may be the same material used to form trench contacts 132 (eg, conductive material 130 ). In certain embodiments, conductive material 210 is formed using a planar deposition process that encapsulates underlying layers within the conductive material. Encapsulating the underlying layers in conductive material 210 ensures that trenches 206 and 208 are completely filled with the conductive material.

After filling trenches 206 and 208 with conductive material 210 , transistor 200 may be planarized (eg, using CMP), as shown in FIG. 29 . Planarization of transistor 200 may include removal of material such that one or more portions of insulating layer 136 are exposed at the planar surface. After planarization of transistor 200, conductive material 210 in trench 206 forms local interconnect 212A to trench contact 132, and conductive material 210 in trench 208 forms a connection to gate open trench contact 204. local interconnect 212B. As shown in FIG. 29 , gate open trench contact 204 has an interface with local interconnect 212B, rather than the local interconnect and gate open trench being a continuous material (such as the local interconnect depicted in FIG. 17 ). 144C and gate open trench 142).

In some embodiments, as shown in FIG. 29 , local interconnects 212A and 212B are thicker than local interconnects used in other routing schemes due to bidirectional routing and the use of gate open trench contacts 204 . Using thicker local interconnects can improve transistor performance by providing lower resistance in the local interconnect layers. In certain embodiments, routing between trench contact 132 and gate open trench contact 204 with local interconnect 212A and local interconnect 212B provides better cell density and allows better technology scaling (eg downscaling to 15nm technology) and/or reduced library cell sizes. In some embodiments, by allowing multiple options for routing between the trench contacts and/or gate open trenches in insulating layer 136, the gap between trench contacts 132 and the gate open trench Routing between contacts 204 using local interconnect 212A and local interconnect 212B provides routing flexibility.

The process implementation depicted in Figures 2 through 29 can utilize self-aligned trench contacts connected to the source/drain of the gate to create a simple local interconnect scheme that extends to the replacement The gate flows above and is connected to the trench contacts and the gate. Some process embodiments described herein may provide lower gate-to-trench contact and local interconnect coupling capacitance. Using the process implementation described herein further reduces the number of resistive interfaces between layers compared to previous replacement gate flow connection schemes. In addition, the self-aligned process embodiments described herein can provide better manufacturing yields due to the reduced possibility of misalignment between contacts, and the process described herein provides a better manufacturing yield than previous replacement gate Process connection schemes and/or simpler process flows utilizing selective etch layers and stricter alignment rules.

The process embodiments as described above for FIGS. 2-29 can be used to form any semiconductor device utilizing the replacement gate flow shown in FIG. 2 . For example, the above-described embodiments may be used to form semiconductor devices for microprocessors, memory devices (eg, SRAM devices), mobile technology devices, or any other device technology that utilizes a replacement gate process during fabrication.

Other modifications and alternative embodiments of the various aspects of the invention will be apparent to those skilled in the art from the present description. Therefore, it is intended that the description be interpreted as illustrative only, and its purpose is to teach those skilled in the art the general way of carrying out the invention. It should be understood that the forms of the invention shown and described herein are to be considered as presently preferred embodiments. Elements and materials shown and described herein may be substituted, parts and processes may be reversed, and certain features of the invention may be utilized independently, all after those skilled in the art having the benefit of the description of the invention. obviously. Changes may be made in the elements described herein without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims (13)

1. a process for fabrication of semiconductor device, comprising:

There is provided transistor, described transistor includes multiple replacement metal gates on a semiconductor substrate Pole, wherein first grid has source electrode and drain electrode and at least one second grid and described first Gate isolation, wherein said transistor includes having the first insulation material around each first grid The grid spacer of material and between described grid spacer, there is the of the second insulating materials At least some in one insulating barrier, and wherein said second insulating materials covers the described first grid The source electrode of pole and drain electrode；

Be formed at described first grid and described second grid aligned above one or more absolutely Edge mandrel, wherein said insulation mandrel comprises described first insulating materials；

Forming the mandrel sept around each insulation mandrel, wherein said mandrel sept comprises Described first insulating materials；

It is formed at second insulating barrier with described second insulating materials above described transistor；

By removing described the from the part between described insulation mandrel of described transistor Two insulating materials, formation is connected to the described source electrode of described first grid and the one or more of drain electrode First groove；

Above described second grid, there is described first insulating materials and described by removing The part of two insulating materials, forms the second groove being connected to described second grid；

Fill described first groove and described second groove with conductive material, be connected to formation described First contact of the described source electrode of first grid and drain electrode and be connected to the second of described second grid Contact；

Form the 3rd insulating barrier above described transistor；

By removing the part of described 3rd insulating barrier, formed and reach through described 3rd insulating barrier Described first contact and the 3rd groove of described second contact；And

By conductive material is deposited on described 3rd ditch being formed through described 3rd insulating barrier In groove, formed and be connected to described first contact and the local interlinkage of described second contact.

2. technique as claimed in claim 1, it further includes in single technique with leading Electric material fills described first groove and described second groove.

3. technique as claimed in claim 1, each of which mandrel at least with its underlying gate Equally wide.

4. technique as claimed in claim 1, each of which mandrel sept has from bottom The profile of the wider narrower inclination to top.

5. technique as claimed in claim 1, at least of each of which mandrel sept It point is exposed in each of described first groove.

6. technique as claimed in claim 1, the edge of wherein said insulation mandrel extends warp Cross the edge of described grid.

7. technique as claimed in claim 1, the edge of wherein said mandrel sept extends Edge through described grid spacer.

8. technique as claimed in claim 1, it farther includes by optionally moving Do not remove except the second insulating materials and the technique of the first insulating materials removes the described second insulation Material, forms and is connected to the described source electrode of described first grid and described first groove of drain electrode.

9. technique as claimed in claim 1, it further includes at the described insulating core of formation Form the thin layer with described second insulating materials above described transistor before axle.

10. technique as claimed in claim 1, wherein said first contact includes by described core The gradient that the gradient of between centers parting determines.

11. techniques as claimed in claim 1, it further includes at is filled by conductive material Described transistor is planarized after described first groove and described second groove.

12. techniques as claimed in claim 1, wherein use CAD (CAD) The corrosion-resisting pattern defining described first groove and described second groove of design is to complete described the One groove and the formation of described second groove.

13. techniques as claimed in claim 1, it further includes at and optionally removes One insulating materials rather than in the technique of the second insulating materials, by having above described second grid The part of described first insulating materials removes, so that described second groove and described second grid Alignment.