CN103943552B - Semiconductor integrated circuit manufacture method - Google Patents
Semiconductor integrated circuit manufacture method Download PDFInfo
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- CN103943552B CN103943552B CN201310141616.6A CN201310141616A CN103943552B CN 103943552 B CN103943552 B CN 103943552B CN 201310141616 A CN201310141616 A CN 201310141616A CN 103943552 B CN103943552 B CN 103943552B
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- adhesive layer
- patterned adhesive
- copper
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- 238000000034 method Methods 0.000 title claims abstract description 90
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000012790 adhesive layer Substances 0.000 claims abstract description 78
- 229910052751 metal Inorganic materials 0.000 claims abstract description 74
- 239000002184 metal Substances 0.000 claims abstract description 74
- 239000010410 layer Substances 0.000 claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 230000008569 process Effects 0.000 claims abstract description 23
- 239000000463 material Substances 0.000 claims description 22
- 239000010949 copper Substances 0.000 claims description 20
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 15
- 238000004581 coalescence Methods 0.000 claims description 14
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 13
- 239000011572 manganese Substances 0.000 claims description 12
- 239000010936 titanium Substances 0.000 claims description 12
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 11
- 229910052707 ruthenium Inorganic materials 0.000 claims description 11
- 238000005516 engineering process Methods 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 7
- PWHULOQIROXLJO-UHFFFAOYSA-N Manganese Chemical compound [Mn] PWHULOQIROXLJO-UHFFFAOYSA-N 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 229910017052 cobalt Inorganic materials 0.000 claims description 6
- 239000010941 cobalt Substances 0.000 claims description 6
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 6
- 229910052748 manganese Inorganic materials 0.000 claims description 6
- 229910052715 tantalum Inorganic materials 0.000 claims description 6
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 6
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- GXDVEXJTVGRLNW-UHFFFAOYSA-N [Cr].[Cu] Chemical compound [Cr].[Cu] GXDVEXJTVGRLNW-UHFFFAOYSA-N 0.000 claims description 5
- JRBRVDCKNXZZGH-UHFFFAOYSA-N alumane;copper Chemical compound [AlH3].[Cu] JRBRVDCKNXZZGH-UHFFFAOYSA-N 0.000 claims description 5
- 230000004888 barrier function Effects 0.000 claims description 5
- HPDFFVBPXCTEDN-UHFFFAOYSA-N copper manganese Chemical compound [Mn].[Cu] HPDFFVBPXCTEDN-UHFFFAOYSA-N 0.000 claims description 5
- WCCJDBZJUYKDBF-UHFFFAOYSA-N copper silicon Chemical compound [Si].[Cu] WCCJDBZJUYKDBF-UHFFFAOYSA-N 0.000 claims description 5
- IUYOGGFTLHZHEG-UHFFFAOYSA-N copper titanium Chemical compound [Ti].[Cu] IUYOGGFTLHZHEG-UHFFFAOYSA-N 0.000 claims description 5
- RPYFZMPJOHSVLD-UHFFFAOYSA-N copper vanadium Chemical compound [V][V][Cu] RPYFZMPJOHSVLD-UHFFFAOYSA-N 0.000 claims description 5
- 229910052741 iridium Inorganic materials 0.000 claims description 5
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052762 osmium Inorganic materials 0.000 claims description 5
- SYQBFIAQOQZEGI-UHFFFAOYSA-N osmium atom Chemical compound [Os] SYQBFIAQOQZEGI-UHFFFAOYSA-N 0.000 claims description 5
- 229910052763 palladium Inorganic materials 0.000 claims description 5
- 229910052697 platinum Inorganic materials 0.000 claims description 5
- 229910052702 rhenium Inorganic materials 0.000 claims description 5
- WUAPFZMCVAUBPE-UHFFFAOYSA-N rhenium atom Chemical compound [Re] WUAPFZMCVAUBPE-UHFFFAOYSA-N 0.000 claims description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- 229910001069 Ti alloy Inorganic materials 0.000 claims description 4
- BVSORMQQJSEYOG-UHFFFAOYSA-N copper niobium Chemical compound [Cu].[Cu].[Nb] BVSORMQQJSEYOG-UHFFFAOYSA-N 0.000 claims 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims 1
- 229910052709 silver Inorganic materials 0.000 claims 1
- 239000004332 silver Substances 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 238000005240 physical vapour deposition Methods 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 239000010931 gold Substances 0.000 description 7
- 230000008021 deposition Effects 0.000 description 6
- 238000000059 patterning Methods 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- AMWRITDGCCNYAT-UHFFFAOYSA-L hydroxy(oxo)manganese;manganese Chemical compound [Mn].O[Mn]=O.O[Mn]=O AMWRITDGCCNYAT-UHFFFAOYSA-L 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- IIQVQTNFAKVVCM-UHFFFAOYSA-N copper niobium Chemical compound [Cu][Nb][Nb] IIQVQTNFAKVVCM-UHFFFAOYSA-N 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- OTEKOJQFKOIXMU-UHFFFAOYSA-N 1,4-bis(trichloromethyl)benzene Chemical compound ClC(Cl)(Cl)C1=CC=C(C(Cl)(Cl)Cl)C=C1 OTEKOJQFKOIXMU-UHFFFAOYSA-N 0.000 description 1
- 229910017083 AlN Inorganic materials 0.000 description 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 238000005054 agglomeration Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 150000001335 aliphatic alkanes Chemical class 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000003763 carbonization Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000006386 neutralization reaction Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920000052 poly(p-xylylene) Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- HWEYZGSCHQNNEH-UHFFFAOYSA-N silicon tantalum Chemical compound [Si].[Ta] HWEYZGSCHQNNEH-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53233—Copper alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
- H01L23/53252—Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
- H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a kind of method manufacturing semiconductor integrated circuit (IC).The method includes：Substrate is provided.Patterned adhesive layer is formed on substrate.Deposited metal layer in patterned adhesive layer.Apply high temperature thermal process to coalesce metal level, thus forming self-forming metal parts (SFMF), and dielectric layer between SFMF.
Description
Technical field
The present invention relates to semiconductor applications, more particularly, to semiconductor integrated circuit manufacture method.
Background technology
Semiconductor integrated circuit (IC) industry development is rapid.Due to IC design and material progress technically so that IC
It is continuously updated the replacement, IC of new generation has less but more complicated circuit than prior-generation IC.In the evolution of IC, generally
Increase the functional density quantity of interconnection devices (that is, in each chip area), but reduce physical dimension (that is, by system
Make the available minimal parts of technique (or line)).
The advantage of this scaled technique is to usually enhance production efficiency and reduce relevant cost.However,
This scaled technique also increases IC processing and the complexity manufacturing.In order to realize these progress it would be desirable to IC adds
Work also will have similar development with manufacture view.Partly lead when mos field effect transistor (MOSFET) is such
Body device pass through different technology nodes scaled when, wire and the phase contributing to wiring between transistor and other devices
The cross tie part closing dielectric material serves even more important effect in raising IC aspect of performance.Although existing manufacture IC device
Method generally has been able to meet expected application target, but, still can not meet the requirement of all aspects.For example, for mutually
Even the metal wire aspect of part mechanical development one more robustness still suffers from challenging.It is desirable that increasing in this field.
Content of the invention
For solving the above problems, this application provides a kind of method manufacturing semiconductor integrated circuit (IC), the method bag
Include：Substrate is provided；Form patterned adhesive layer above substrate；Disposed thereon metal in patterned adhesive layer and substrate
Layer；Application thermal process is to coalesce metal level, thus forming self-forming metal parts (SFMF) above patterned adhesive layer, its
In, the top of SFMF has random coalescence face；And the disposed thereon dielectric layer in SFMF.
Wherein, patterned adhesive layer is included selected from cobalt (Co), ruthenium (Ru), manganese (Mn), tantalum (Ta), tantalum nitride (TaN), titanium
(Ti), one or more of group that the alloy of titanium nitride (TiN), tungsten (W) and these materials is formed material.
Wherein, the thickness of patterned adhesive layer is aboutTo aboutIn the range of.
Wherein, patterned adhesive layer includes Co, and the thickness of Co is aboutTo aboutIn the range of.
Wherein, metal level is included selected from copper (Cu), stannum (Sn), silver-colored (Ag), golden (Au), palladium (Pd), platinum (Pt), rhenium
(Re), iridium (Ir), ruthenium (Ru), osmium (Os), copper manganese (CuMn), copper aluminum (CuAl), copper titanium (CuTi), copper vanadium (CuV), copper chromium
(CuCr), one or more of group that copper silicon (CuSi) and copper niobium (CuNb) are formed material.
Wherein, the thickness of metal level is aboutTo aboutIn the range of.
Wherein, metal level includes Cu, and the thickness of Cu is aboutTo aboutIn the range of.
Wherein, with about 200 DEG C to about 700 DEG C of temperature range application thermal process.
Wherein, with about 350 DEG C to about 500 DEG C of temperature range, thermal process is applied to metal level.
Wherein, from the point of view of overlooking, the shape of the shape of the SFMF of formation patterned adhesive layer corresponding with above substrate
Shape is roughly the same.
Wherein, further include：Before dielectric layer, deposit barrier layer.
Wherein, dielectric layer includes low-k materials.
Additionally, additionally providing a kind of method manufacturing semiconductor integrated circuit (IC), the method includes：Offer has conduction
The substrate of part；Form patterned adhesive layer above substrate, wherein, patterned adhesive layer has the firstth area and the secondth area,
Wherein, the firstth area is aligned with least a portion of corresponding conductive component, and there is not conductive component in the second region；Deposition
Metal level, with overlay pattern adhesive layer；Application thermal process is to coalesce metal level, thus being formed above patterned adhesive layer
Self-forming metal parts (SFMF), wherein, the top of SFMF has random coalescence face；And adjacent to SFMF dielectric layer.
Wherein, patterned adhesive layer is included selected from cobalt (Co), ruthenium (Ru), manganese (Mn), tantalum (Ta), tantalum nitride (TaN), titanium
(Ti), one or more of group that the alloy of titanium nitride (TiN), tungsten (W) and these materials is formed material.
Wherein, the thickness of patterned adhesive layer is aboutTo aboutIn the range of.
Wherein, metal level is included selected from copper (Cu), stannum (Sn), silver-colored (Ag), golden (Au), palladium (Pa), platinum (Pt), rhenium
(Re), iridium (Ir), ruthenium (Ru), osmium (Os), copper manganese (CuMn), copper aluminum (CuAl), copper titanium (CuTi), copper vanadium (CuV), copper chromium
(CuCr), one or more of group that copper silicon (CuSi) and copper niobium (CuNb) are formed material.
Wherein, from the point of view of overlooking, the shape of SFMF is roughly the same with the shape of corresponding patterned adhesive layer.
Wherein, with the temperature range application thermal process between about 200 DEG C and about 700 DEG C.
Additionally, additionally providing a kind of semiconductor integrated circuit (IC), this IC includes：Substrate, has apparatus assembly；Patterning
Adhesive layer, positioned at the top of substrate, patterned adhesive layer includes the firstth area and the secondth area, in the firstth area, patterned adhesive layer
It is aligned with least a portion of apparatus assembly, and in the second region, there is not apparatus assembly；Multiple self-forming metal parts
(SFMF), positioned at the top of patterned adhesive layer and in the firstth area and the secondth area, the top of SFMF has random coalescence face,
Wherein, from the point of view of overlooking, the shape of each SFMF is all substantially similar with the shape of the corresponding part of patterned adhesive layer；With
And dielectric layer, between multiple SFMF.
Wherein, SFMF includes being formed at the copper (Cu) above patterned adhesive layer.
Brief description
When reading in conjunction with the accompanying drawings, the present invention may be better understood according to the following detailed description.It should be emphasized that
, according to the standard practices in industry, various parts are not drawn to scale and are intended solely for illustrative purposes.Actual
On, in order to clearly discuss, the quantity of various parts and size can be arbitrarily increased or reduce
Fig. 1 shows the flow process of the case method of manufacture semiconductor integrated circuit (IC) according to various aspects of the invention
Figure；And
Fig. 2 to Fig. 6 shows the sectional view of the example semiconductor IC device in the fabrication stage of method according to Fig. 1.
Specific embodiment
The following disclosure provides multiple difference embodiments or example, for realizing the different characteristic of the present invention.Hereinafter will retouch
The particular instance stating assembly with arrangement is to simplify the present invention.Certainly, these are only examples and are not intended to limit the present invention.This
Outward, in the following description, carrying out the first technique and can include carrying out after the first technique at once before the second technique
The embodiment of two techniques can carry out the embodiment between the first technique and the second technique it is also possible to include other techniques.For
Simplify and clear, various parts can be drawn according to different proportion.Additionally, in the following description, above second component or
The upper first component that formed can include the embodiment of first component and second component directly contact it is also possible to inclusion miscellaneous part can
To be formed between first component and second component so that the embodiment that is not directly contacted with of first component and second component.
Fig. 1 shows the one of the method 100 of the one or more semiconductor device of manufacture according to various aspects of the invention
The flow chart of individual embodiment.Referring to the semiconductor device 200 shown in Fig. 2-Fig. 6, method 100 is discussed further below.
Referring to Fig. 1 and Fig. 2, method 100, with step 102 for beginning, provides substrate 210.Substrate 210 includes silicon.Alternatively
Or additionally, substrate 210 may include other basic quasiconductors, such as germanium.Substrate 210 may also comprise compound semiconductor, such as carbonization
Silicon, GaAs, indium arsenide and indium phosphide.Substrate 210 may include alloy semiconductor, such as SiGe, silicon germanium carbide, gallium arsenic and phosphorus
Change gallium indium.In one embodiment, substrate 210 includes epitaxial layer.For example, substrate 210 can have covering on bulk semiconductor
Epitaxial layer.Additionally, substrate 210 may include semiconductor-on-insulator (SOI) structure.For example, substrate 210 may include by technique
What (e.g., note oxygen isolation (SIMOX) or other appropriate technologies (e.g., wafer engages and grinds)) was formed buries oxygen (BOX) layer.
Substrate 210 may also comprise the different p-type doped region realized by the technique of such as ion implanting and/or ion diffusion
And/or N-shaped doped region.These doped regions include n trap, p trap, lightly doped district (LDD), heavy doping source electrode and drain electrode (S/D) and not
Same channel doping side (channel doping profile), is configured so as to form different integrated circuit (IC) devices
Part, such as complementary metal oxide semiconductor field effect transistor (CMOSFET), imaging sensor and/or light emitting diode
(LED).Substrate 210 can further include the part of other functions, is such as formed at the resistor in substrate and on substrate or electric capacity
Device.
Substrate 210 may also comprise different insulating elements.Different components in substrate 210 are separated and leave by insulating element.
Insulating element includes the different structure being formed by using different process technologies.For example, to may include shallow trench exhausted for insulating element
Edge (STI) part.The formation of STI may include in substrate 210 etching groove and with isolator material (e.g., silicon oxide, nitridation
Silicon or silicon oxynitride) fill this groove.The groove being filled can have multiple structure, such as has the nitridation for filling groove
The thermal oxide layer of silicon.(CMP) can be chemically-mechanicapolish polished with excessive isolator material smooth insulating element after polishing
Top surface.
Substrate 210 may also comprise the grid stacking being formed by dielectric layer and electrode layer.Dielectric layer may include boundary layer (IL)
With high k (HK) dielectric layer, wherein, high k (HK) dielectric layer is by suitable technology, e.g., chemical vapor deposition (CVD), atom
Layer deposition (ALD), physical vapour deposition (PVD) (PVD), thermal oxide, and combinations thereof or other suitable technology depositions form.Electrode layer
May include the single or multiple lift being formed by ALD, PVD, CVD or other suitable technology, such as metal level, laying, wet layer
And adhesive layer.
Substrate 210 may also comprise multiple interlayer dielectric (ILD) layer and conductive component, wherein, multiple ILD layer and conductive component
Integrated to form interconnection structure, this interconnection structure is configured to connect different p-types and N-shaped doped region and other functional parts
(e.g., gate electrode), is consequently formed Functional integrated circuit.In an example, substrate 210 may include of interconnection structure
Point, and interconnection structure includes multilayer interconnection (MLI) structure and the ILD layer integrating with MLI structure, to provide electric cloth
Line, thus the different components in substrate 210 are connected to input/output power supply and signal.Interconnection structures include different gold
Belong to line, contact and throughhole member (or through hole plug).Metal wire provides the electric wiring of level.Contact provide silicon substrate and
Vertical connection between metal wire, and throughhole member provides the vertical connection between the metal wire in different metal layer.
Part 210 includes apparatus assembly 214.In one embodiment, apparatus assembly 214 includes conductive component.Conductive part
Part 214 may include a part for interconnection structure.For example, conductive component 214 includes contact, metal throuth hole or metal wire.Pass through
Technique including photoetching, etching and deposition can form conductive component 214.In another embodiment, conductive component 214 includes electricity
A part for pole, capacitor, resistor or resistor.Alternatively, conductive component 214 may include doped region (e.g., source electrode or leakage
Pole) or gate electrode.In another embodiment, conductive component 214 is provided in the silicon on corresponding source electrode, drain electrode or gate electrode
Compound part.Silicide part can be formed by self-aligned silicide (silicide or salicide) technology.
Referring to Fig. 1 and Fig. 3, method 100 proceeds to step 104, is formed and have first thickness (t above substrate 2101)
Patterned adhesive layer 310.Patterned adhesive layer 310 may include cobalt (Co), ruthenium (Ru), manganese (Mn), tantalum (Ta), tantalum nitride
(TaN), titanium (Ti), titanium nitride (TiN), tungsten (W) or other suitable materials.By physical vapour deposition (PVD) (PVD), chemical gas
Mutually deposition (CVD), metal organic chemical vapor deposition (MOCVD), ald (ALD) or other suitable techniques can be sunk
Amass into patterned adhesive layer 310.Patterned adhesive layer 310 can be patterned by photoetching and etch process.Patterning is viscous
Close floor 310 and include the first area 312 and the second area 314, wherein, at least a portion of the first area 312 and corresponding apparatus assembly 214
Be aligned, and there is not apparatus assembly 214 in the second area 314.For example, in the first area 312, patterned adhesive layer 310 is complete
Cover corresponding apparatus assembly 214 and extend in substrate 210.Again for example, in the first area 312, the patterning of formation
Adhesive layer 310 is aligned with corresponding apparatus assembly 214, but does not extend in substrate 210.Second area 314 and the first area 312 it
Between exist distance (d).
Referring to Fig. 1 and Fig. 4, method 100 proceeds to step 106, wherein, in step 106, in substrate 210 and patterning
The disposed thereon of adhesive layer 310 has second thickness (t2) metal level 410.Metal level 410 includes the gold with high surface energy
Belong to and metal alloy, e.g., copper (Cu), stannum (Sn), silver-colored (Ag), golden (Au), palladium (Pd), platinum (Pt), rhenium (Re), iridium (Ir), ruthenium
(Ru), osmium (Os), copper manganese (CuMn), copper aluminum (CuAl), copper titanium (CuTi), copper vanadium (CuV), copper chromium (CuCr), copper silicon (CuSi),
Copper niobium (CuNb) or other suitable metals.Can be by PVD, CVD, ALD, electrochemical plating (ECP) or other suitable works
Skill deposited metal 410.
Referring to Fig. 1 and Fig. 5, method 100 proceeds to step 108, and wherein, in step 108, application high temperature thermal process is with poly-
Knot metal level 410 and formation self-forming metal parts (SFMF) 420 in patterned adhesive layer 310, this SFMF420 has width
W and height h.During thermal process, in the metal level 410 in an area, initially form space, there is not figure in this zone
Case adhesive layer 310, then, crumb form is grown in these spaces.Finally, metal level 410 coalesces completely with patterning bonding
SFMF420 is formed on the top of layer 310.From the point of view of overlooking, the shape of SFMF420 and corresponding patterned adhesive layer 310
Shape is roughly the same.Observe the top of SFMF420, it has random coalescence face.In the present embodiment, patterned adhesive layer
The 310 width w defining SFMF420, and the height h of SFMF420 is the thickness of metal level 410 and the combination of width w.Correspond to
The different ratios of w and h, the top shape in the random coalescence face of SFMF420 can be substantially different.For example, it is possible to know, ratio
(w/h) bigger, the center at the top in coalescence face is more flat and marginal position is round.
In the present embodiment, configure the first thickness (t of patterned adhesive layer 3101), the first of patterned adhesive layer 310
The distance between area 312 and the second area 314 (d), the second thickness (t of metal level 4102) and a group of temperature of thermal process make a reservation for
Index, to realize being formed SFMF420 above patterned adhesive layer 310.There is no the area of patterned adhesive layer 310 inside it
In, it is kept completely separate metal level 410.For example, the first thickness (t of Co patterned adhesive layer 3101) betweenArriveModel
In enclosing, and the second thickness (t of Cu layer 4102) betweenArriveIn the range of.The temperature of thermal process arrives between 200 DEG C
In the range of 700 DEG C.Again for example, deposit Co patterned adhesive layer, its thickness betweenArriveIn the range of, and in Co figure
Deposited cu layer on case adhesive layer, its thickness betweenArriveIn the range of.Temperature between 350 DEG C to 500 DEG C it
Between under conditions of, thermal process is applied to Cu layer.In one embodiment, the second area 314 of layout adhesive layer 310,
To form virtual SFMF in low metal component density area.
In one embodiment, configuration is formed at SFMF420 in the first area 312, with provide in substrate apparatus assembly and
Vertical connection between the metal wire of different metal layer, and configure the SFMF420 being formed in the second area 314, with identical gold
Belonging in layer provides vertical electric wiring.
Referring to Fig. 1 and Fig. 6, method 100 proceeds to step 110, dielectric layer 510 between SFMF420, by each
SFMF420 is isolated from each other.Dielectric layer 510 includes dielectric material, such as silicon oxide, silicon nitride, there is the dielectric of dielectric constant (k)
Material or other suitable dielectric materials layers, wherein, this dielectric constant (k) is less than dielectric constant (therefore, the quilt of thermal oxidation silicon
Referred to as low-k dielectric material layer).In different examples, low k dielectric may include, and for example, fluorinated silica glass (FSG), carbon are mixed
Miscellaneous silicon oxide, fluoride amorphous carbon, Parylene, BCB (alkane and hexichol based polymer), SiLK (Michigan, USA Midland
City's DOW Chemical), polyimides and/or other materials.In another example, low k dielectric may include ultralow k (XLK)
Dielectric material.The technique forming dielectric layer 510 can use rotary coating or CVD.
In one embodiment, before dielectric layer 510, barrier layer 430 is deposited on SFMF420.Barrier layer 430
May include tantalum (Ta), titanium (Ti), manganese (Mn), cobalt (Co), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN),
Titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), manganese oxide (MnO), aluminium nitride, aluminium oxide or other suitable materials.Logical
Cross PVD, CVD, ALD or other suitable techniques can deposit barrier layer 430.
Additionally, carrying out CMP to remove excessive dielectric layer 510.In one embodiment, CMP removes SFMF420's
The part at top the top surface by the top surface planarizing dielectric layer 510 of SFMF420.
Before method 100, after its neutralization, additional step can be provided, for the additional embodiment of method 100, description
Some steps can be replaced, removed or adjustment order.For example, it is possible to repeat step 104 to 110, to form new metal/Jie
Electrical interconnection.
Based on foregoing description, the invention provides the method manufacturing IC part.Method includes：By coalescing high surface energy
Metal carrys out pattern metal by using bonding differentiation using patterned adhesive layer forming metal wire, and in agglomeration process
Line.This method provide the metal wire being formed by deposition and thermal process.The method shows formation undersized robustness gold
Belong to line.
The invention provides manufacturing the different embodiments of semiconducter IC, compared with existing additive method, these embodiments
There are one or more improvement.In one embodiment, the method manufacturing semiconductor integrated circuit (IC) includes：Substrate is provided；
Form patterned adhesive layer above substrate；Deposited metal layer in patterned adhesive layer；And application thermal process, to coalesce
Metal level, thus form self-forming metal parts (SFMF) above patterned adhesive layer.The top of SFMF has irregularly
Coalescence face.Method is also included within dielectric layer between SFMF.
In another embodiment, the method manufacturing semiconducter IC includes：The substrate with conductive component is provided；And
The top of substrate forms patterned adhesive layer.Patterned adhesive layer has the firstth area, and this firstth area is with corresponding conductive component extremely
Few part be aligned.Method also includes：Deposited metal layer in patterned adhesive layer；And application thermal process, to coalesce metal
Layer, thus form self-forming metal parts (SFMF) above patterned adhesive layer.The top of SFMF has random coalescence
Face.Method is additionally included in dielectric layer between SFMF.
In another embodiment, semiconductor device includes the substrate with apparatus assembly and is located at the pattern above substrate
Change adhesive layer.Patterned adhesive layer has the firstth area and the secondth area, wherein, in the firstth area, patterned adhesive layer and device group
At least a portion be aligned of part, and there is not apparatus assembly in the second region.Semiconductor device is also included with random coalescence
The self-forming metal parts (SFMF) in face, wherein, SFMF is formed at the patterning in the firstth area and the secondth area by metal coalescence
On adhesive layer.The top of SFMF has random coalescence face.In terms of depression angle, the shape of SFMF and patterned adhesive layer right
Answer the shape of part substantially similar.SFMF is formed with pattern, and it is roughly the same with the patterned adhesive layer above substrate.Quasiconductor
Device also includes the dielectric layer between SFMF.
The part of some embodiments is discussed above so that those of ordinary skill in the art may be better understood the present invention
Various aspects.It will be understood by those skilled in the art that can easily design using based on the present invention or
Change other for the process and the structure that reach with embodiment identical purpose described herein and/or realize same advantage.This
Field those of ordinary skill it should also be appreciated that this equivalent constructions are without departing from the spirit and scope of the present invention, and not
In the case of deviating from the spirit and scope of the present invention, multiple changes, replacement and change can be carried out.
Claims (20)
1. a kind of method manufacturing semiconductor integrated circuit (IC), methods described includes：
Substrate is provided；
Form patterned adhesive layer above described substrate；
Disposed thereon metal level in described patterned adhesive layer and described substrate；
Application thermal process is with the described metal level not existed above the region of described patterned adhesive layer of described substrate
Form space, and the overlying regions with described patterned adhesive layer in described substrate coalesce described metal level, thus in institute
The top stating patterned adhesive layer forms self-forming metal parts (SFMF), wherein, the top tool of described self-forming metal parts
There is random coalescence face；And
Disposed thereon dielectric layer in described self-forming metal parts.
2. method according to claim 1, wherein, described patterned adhesive layer is included selected from cobalt (Co), ruthenium (Ru), manganese
(Mn), in the group that tantalum (Ta), tantalum nitride (TaN), titanium (Ti), the alloy of titanium nitride (TiN), tungsten (W) and these materials are formed
One or more material.
3. method according to claim 1, wherein, the thickness of described patterned adhesive layer existsArriveScope
Interior.
4. method according to claim 1, wherein, described patterned adhesive layer includes Co, and the thickness of described Co existsArriveIn the range of.
5. method according to claim 1, wherein, described metal level include selected from copper (Cu), stannum (Sn), silver-colored (Ag),
Golden (Au), palladium (Pd), platinum (Pt), rhenium (Re), iridium (Ir), ruthenium (Ru), osmium (Os), copper manganese (CuMn), copper aluminum (CuAl), copper titanium
(CuTi), one or more of group that copper vanadium (CuV), copper chromium (CuCr), copper silicon (CuSi) and copper niobium (CuNb) are formed material
Material.
6. method according to claim 1, wherein, the thickness of described metal level existsArriveIn the range of.
7. method according to claim 1, wherein, described metal level includes Cu, and the thickness of described Cu existsArrive
In the range of.
8. method according to claim 1, wherein, applies described thermal process with 200 DEG C to 700 DEG C of temperature range.
9. method according to claim 1, wherein, with 350 DEG C to 500 DEG C of temperature range, described thermal process is applied
In described metal level.
10. method according to claim 1, wherein, from the point of view of overlooking, the described self-forming metal parts of formation
The shape of shape described patterned adhesive layer corresponding with above described substrate is roughly the same.
11. methods according to claim 1, wherein, further include：
Before depositing described dielectric layer, deposit barrier layer.
12. methods according to claim 1, wherein, described dielectric layer includes low-k materials.
A kind of 13. methods manufacturing semiconductor integrated circuit (IC), methods described includes：
The substrate with conductive component is provided；
Form patterned adhesive layer above described substrate, wherein, described patterned adhesive layer has the firstth area and the secondth area,
Wherein, described firstth area is aligned with least a portion of described conductive component accordingly, and does not exist in described secondth area
Described conductive component；
Deposited metal layer, to cover described patterned adhesive layer；
Application thermal process is to coalesce described metal level, thus forming self-forming metal parts above described patterned adhesive layer
(SFMF), wherein, the top of described self-forming metal parts has random coalescence face；And
Neighbouring described self-forming metal parts dielectric layer.
14. methods according to claim 13, wherein, described patterned adhesive layer include selected from cobalt (Co), ruthenium (Ru),
The group that manganese (Mn), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), the alloy of titanium nitride (TiN), tungsten (W) and these materials are formed
One or more of material.
15. methods according to claim 13, wherein, the thickness of described patterned adhesive layer existsArriveScope
Interior.
16. methods according to claim 13, wherein, described metal level is included selected from copper (Cu), stannum (Sn), silver
(Ag), golden (Au), palladium (Pa), platinum (Pt), rhenium (Re), iridium (Ir), ruthenium (Ru), osmium (Os), copper manganese (CuMn), copper aluminum (CuAl),
One of group that copper titanium (CuTi), copper vanadium (CuV), copper chromium (CuCr), copper silicon (CuSi) and copper niobium (CuNb) are formed or many
Plant material.
17. methods according to claim 13, wherein, from the point of view of overlooking, the shape of described self-forming metal parts
Roughly the same with the shape of corresponding described patterned adhesive layer.
18. methods according to claim 13, wherein, apply described thermal technology with the temperature range between 200 DEG C and 700 DEG C
Skill.
A kind of 19. semiconductor integrated circuit (IC), described integrated circuit includes：
Substrate, has apparatus assembly；
Patterned adhesive layer, positioned at the top of described substrate, described patterned adhesive layer includes the firstth area and the secondth area, described
In firstth area, described patterned adhesive layer is aligned with least a portion of described apparatus assembly, and in described secondth area, no
There is described apparatus assembly；
Multiple self-forming metal parts (SFMF), positioned at the top of described patterned adhesive layer and in described firstth area and described
In 2nd area, the top of described self-forming metal parts has random coalescence face, and wherein, from the point of view of overlooking, each is from one-tenth
The shape of type metal parts is all substantially similar with the shape of the corresponding part of described patterned adhesive layer；And
Dielectric layer, between the plurality of self-forming metal parts.
20. semiconductor integrated circuit according to claim 19, wherein, described self-forming metal parts includes being formed at institute
State the copper (Cu) above patterned adhesive layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/745,060 US9214383B2 (en) | 2013-01-18 | 2013-01-18 | Method of semiconductor integrated circuit fabrication |
| US13/745,060 | 2013-01-18 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6566262B1 (en) * | 2001-11-01 | 2003-05-20 | Lsi Logic Corporation | Method for creating self-aligned alloy capping layers for copper interconnect structures |
| US6607982B1 (en) * | 2001-03-23 | 2003-08-19 | Novellus Systems, Inc. | High magnesium content copper magnesium alloys as diffusion barriers |
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| KR20000027291A (en) * | 1998-10-27 | 2000-05-15 | 김영환 | Method for forming metallization of semiconductor device |
| KR100764458B1 (en) * | 2004-02-04 | 2007-10-05 | 삼성전기주식회사 | Electrode layer, light generating device comprising the same and method of forming the same |
| US20060138668A1 (en) * | 2004-12-27 | 2006-06-29 | Hung-Wen Su | Passivation structure for semiconductor devices |
| US7655556B2 (en) * | 2007-03-23 | 2010-02-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structures for semiconductor devices |
| US7915703B2 (en) | 2009-05-13 | 2011-03-29 | Cree, Inc. | Schottky diodes containing high barrier metal islands in a low barrier metal layer and methods of forming the same |
| US8076241B2 (en) * | 2009-09-30 | 2011-12-13 | Tokyo Electron Limited | Methods for multi-step copper plating on a continuous ruthenium film in recessed features |
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2013
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6607982B1 (en) * | 2001-03-23 | 2003-08-19 | Novellus Systems, Inc. | High magnesium content copper magnesium alloys as diffusion barriers |
| US6566262B1 (en) * | 2001-11-01 | 2003-05-20 | Lsi Logic Corporation | Method for creating self-aligned alloy capping layers for copper interconnect structures |
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| US9214383B2 (en) | 2015-12-15 |
| US20140203437A1 (en) | 2014-07-24 |
| CN103943552A (en) | 2014-07-23 |
| KR101386749B1 (en) | 2014-04-17 |
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