CN103928609B - Three-dimensional phase change memory device and manufacturing method thereof - Google Patents

Abstract

The invention discloses a three-dimensional phase change memory device and a manufacturing method thereof, wherein the three-dimensional phase change memory device is used for storing multiple bits in each memory cell; the memory cell is represented by a non-overlapping range of resistances established by different amorphous phase thicknesses of the phase change memory material in the memory cell. An access array may underlie a plurality of conductive layers separated from each other and from the access array by insulating layers. The conductive pillar array extends through the plurality of conductive layers and contacts the corresponding access array. The phase change memory element is arranged between the conductive column and the conductive layer. The circuit programs data in the memory cell using programming pulses having a pulse shape determined by the resistance range of the memory cell prior to programming and the data value stored.

Description

Three-dimensional phase change memory device and manufacturing method thereof

technical field

The present invention relates to a high-density memory element, and in particular to a memory device in which memory cells are arranged in a three-dimensional array in multiple planes and a manufacturing method thereof.

Background technique

As the size of integrated circuits gradually shrinks to a critical value, designers have begun to look for multi-plane technology of stacked memory cells to achieve higher storage capacity per bit and lower cost. In some techniques, multiple conductive planes may intersect each other through an array of conductive pillars. Individual memory cells are selected by corresponding conductive pillars and conductive planes. However, in this technology, a rectifier or a diode must be configured for each memory cell in the array, thus causing process difficulty and increasing cost. Reference may be made to the document titled "Integrated Circuit 3d Memory Array And Manufacturing Method" in US Patent Publication No. 2010-0270593-A1.

Therefore, the present invention provides a three-dimensional integrated circuit memory device and a method of manufacturing the same, which has low manufacturing cost and includes reliable, small-volume memory elements.

Contents of the invention

The invention relates to a memory device, which includes a first conductor, a second conductor and a storage unit. The memory cell includes a phase change memory material in an interface between the first conductor and the second conductor, wherein only the non-zero thickness of an amorphous phase of the phase change memory material is representative of storage in the memory cell For data, none of the data values stored in the plurality of memory cells corresponds to a crystalline phase of the phase change memory material.

According to the present invention, a memory device is provided, which includes an access array, multiple conductive layers, a conductive column array, and multiple memory cells. The conductive layers are separated from each other and from the access array by a plurality of insulating layers. The conductive pillar array extends through the conductive layer, and the conductive pillars in the conductive pillar array correspond to contact with the access devices in the access array. A current path of the memory cell has a phase-change memory material, and the current path is between the corresponding conductive pillars and the corresponding conductive layers. The phase-change memory material in all memory cells stores data values, and the phase-change memory material is in the In the current path, there are different thicknesses in an amorphous phase.

According to the present invention, an operating method of a memory device is proposed, the memory device includes a plurality of phase-change memory cells, and the operating method includes the following steps. receiving data to program a selected phase change memory cell, the data having one of a plurality of data values stored in the selected memory cell, the data value being determined by a plurality of resistance ranges established in the phase change memory cell Representatively, the resistance range is achieved using the corresponding thickness of the amorphous phase memory material through the current path in the memory cell. Provide a programming pulse through the selected phase-change memory cell, the programming pulse is used to program the data in the memory cell, the memory cell has multiple data values, the data value is represented by the non-overlapping range of multiple resistances, and the non-overlapping range of the resistance The range includes a range of resistances established in the memory cell by different amorphous phase thicknesses of the phase change memory material across the interface region.

In order to have a better understanding of the above and other aspects of the present invention, the following specific examples, together with the accompanying drawings, are described in detail as follows:

Description of drawings

FIG. 1 is a cross-sectional view of a multi-level memory cell structure according to an embodiment of the present invention.

FIG. 2 illustrates a top view of conductive pillars and memory material layers of a multi-level memory cell structure according to an embodiment of the present invention.

FIG. 3 is a schematic diagram illustrating the structure of FIG. 1 .

FIG. 4 is a partial schematic diagram of four conductive pillars in the three-dimensional memory array as in FIG. 3 .

FIGS. 5A to 5D illustrate the volume of the amorphous phase in individual memory cells of the multi-level structure shown in FIG. 1 to represent data values in the memory structure.

6A-6D show graphs of temperature versus time in the active region that roughly correspond to the pulse shape and are used for switching from a lower volume to a higher volume.

7A-7C are graphs of temperature versus time in the active region that roughly correspond to the pulse shape and are used for switching from a higher volume to a lower volume.

8 is a flow diagram representing a control logic sequence that may be used to program a memory cell, including selecting a pulse shape based on the initial state and target state of the memory cell.

9 is a cross-sectional view of a horizontal stack memory structure with programmed memory cells, with phase change material disposed on the liners of the vertical conductive pillars.

10 is a cross-sectional view of a horizontal stack memory structure with programmed memory cells, where the horizontal conductors include phase change material.

11 to 14 illustrate various stages of the manufacturing process of the three-dimensional memory structure according to the embodiment of the present invention.

FIG. 15 illustrates a stage of the manufacturing process of the three-dimensional memory structure according to the embodiment of the present invention.

16A-16B are partial flowcharts for fabricating a three-dimensional memory structure.

FIG. 17 shows a simplified block diagram of an integrated circuit according to an embodiment of the present invention.

【Symbol Description】

10: Semiconductor body

11, 42, 62, 63, 1110: bit line

12: Shallow trench isolation structure

13: drain

14: channel

15: Source

16, 18, 21, 22, 24-1～24-n, 604, 634, 636, 820, 822, 824, 826, 828: insulating layer

17, 43, 60, 61, 1106: word line

19: Silicide layer

20: Contact pad

23-1～23-n, 602-1～602-8, 632-1～632-8, 708, 710, 712, 714, 808, 810, 812, 814, 850: conductive layer

25, 734, 735: column center

27, 606, 732, 733: Liners

29, 702, 802: dielectric layer

30: area

40, 68, 69, 70, 71, 600, 630, 855: conductive pillar

41, 64, 65, 66, 67, 601, 651, 700: access device

44-1～44-n, 72-1～72-n, 73-1～73-n, 74-1～74-n, 75-1～75-n: storage elements

45-1～45-n: conductive plane

46: Face Decoder

47: Ground plane:

100: storage unit access layer

300, 610, 612, 614, 616, 618, 620, 622, 624, 640, 642, 644, 646, 648, 650, 652, 654, 860, 862, 864, 866: storage unit

302: phase change memory element

304, 306: heating electrodes

312, 314: surface

308-1～308-4, 605, 607, 609, 611, 613, 615, 617, 619, 635, 637, 639, 641, 643, 645, 647, 649, 852: amorphous phase volume

400, 410: leading edge

402, 412, 577: Peak

404, 414: trailing edge

550: Part One

552: Part Two

574: Phase

580, 582, 584, 900~911: process steps

608, 658: layer decoder

704, 706, 806: plug

720, 722, 724, 726, 740: Insulators

730, 731: through hole

800: access array

851: Patch

1100: integrated circuit

1102: Three-dimensional memory array

1104: column decoder

1108: row decoder

1112: layer decoder

1114: line segment

1116, 1120: bus

1118: Page buffer

1122: Data input line

1124: Other circuits

1126: data output line

detailed description

The following is a more detailed description of the present invention based on the embodiments, together with the drawings shown in FIGS. 1 to 17 .

FIG. 1 is a cross-sectional view of a multi-level memory cell structure according to an embodiment of the present invention. In this embodiment, the memory cells are formed on an integrated circuit substrate including an access array. The access array includes access devices arranged in a pillar array to connect to individual conductive pillars (conductive pillars include, for example, a pillar core 25 and a liner 27 ). In this embodiment, the access device is a part of an integrated circuit substrate including the memory cell access layer 100 .

The access array of this embodiment includes a semiconductor body 10 having a shallow trench isolation structure 12 , and the shallow trench isolation structure 12 is patterned into lines and formed on the surface. Between the shallow trench isolation structures 12, ions are deposited and implanted to form buried diffused bit lines 11, which extend in a direction perpendicular to the plane of entry or exit of the drawing. The access device of the core 25 is composed of a vertical field-effect transistor (field-effect transistor, FET). The field-effect transistor has a drain 13, a channel 14 and a source 15, and is covered by a gate dielectric layer 29. surrounded by. An insulating layer 16 is situated above the semiconductor body 10 . A word line 17 runs through the array and surrounds the channel 14 of the vertical field effect transistor. In this embodiment, the insulating layer 18 is located on the word line 17 . A silicide layer 19 is formed on top of the source electrode 15 . In this embodiment, contact pads 20 (eg, a heat-resistant metal layer such as tungsten) are patterned and formed on the silicide layer 19 . The insulating layers 21 and 22 in this embodiment are located on the contact pad 20 . Shown in the figure is a part of an integrated circuit substrate including a memory cell access layer 100 from the contact pad 20 to the semiconductor body 10 (eg bulk silicon).

A plurality of conductive layers 23 - 1 to 23 - n are located on the contact pads 20 and the insulating layer 22 . The insulating layers 24-1 to 24-(n-1) separate the conductive layers 23-1 to 23-n from each other. An insulating layer 24-n covers the top of the conductive layer 23-n. In another embodiment, the access array may be formed on or between multiple conductive layers, for example using thin film transistor technology.

A conductive pillar including a pillar core 25 and a pad 27 extends through a plurality of conductive layers 23 - 1 to 23 - n and insulating layers 24 - 1 to 24 -(n−1). The conductive pillar includes a pillar core 25 and a pad 27 of phase change material. The core 25 may include metal, non-metal or low-resistance phase change material, such as non-metal such as titanium nitride (Titanium Nitride, TiN). When the core 25 includes a phase change material, the liner 27 can include the same phase change material (in this embodiment, the core 25 and the liner 27 can be a single body), and the same phase change material is made of, for example, an additive. , dopants or other phase change materials.

A ring-shaped interface region, such as region 30 , is formed at the intersection of conductive layers 23 - 1 to 23 - n and columnar pad 27 . The phase change material of liner 27 is disposed in the interface region and acts as a memory element of the stacked memory cell on the conductive pillar. The memory elements of individual memory cells provide current paths between the corresponding conductive layers and conductive pillars, and are used to store data values. The data values are determined by the different amorphous phase thicknesses of the phase-change memory materials in the memory cells. Establish.

The phase change material forming liner 27 has a relatively high-resistance amorphous phase and a relatively low-resistance (compared to the amorphous) crystalline phase. In one embodiment, the liner 27 includes a phase change material such as germanium-rich (GexSbyTez), which has relatively high resistance in the as-deposited junction phase. Through this feature, when the state of memory cells formed with only crystalline phase material is switched to the working state in which all memory cells include an amorphous phase capacity, the leakage current is limited, and the memory array is initialized, so that the memory array can be initialized during operation. During the device, inter-layer leakage current protection is provided by providing memory cell reset pulses.

A plurality of conductive layers 23-1 to 23-n are used as heater electrodes of the phase change memory element in the interface area, and the heater electrodes can be defined as conductors with relatively high resistance or small contact areas or both Electrodes, conductors such as titanium nitride, are used to achieve the temperature and current density that change the resistive state of the phase change material. In another implementation structure, the conductive layers 23-1 to 23-n may have phase change materials, and the storage conductive pillars may serve as heating electrodes.

In the interface area of the present structure there are no additional access means, eg diodes. In addition, operating all memory cells such that a minimum volume of amorphous phase material can be maintained in the active area, the phase change memory material is passed through the current path with different thicknesses of the amorphous phase, allowing the memory cell to be in a lowest resistance state It can still have a relatively high resistance to represent a data value. The relatively high resistance of a memory cell acts to block leakage current during accesses to other memory cells, and the memory cell corresponds to a data value in all states. This structure forms a basic array cell for all amorphous three-dimensional phase change memory cells, one or more bits can be accessed in each memory cell, each data value corresponds to the amorphous phase volume of the current path through the memory cell of different thicknesses. If there is only crystalline phase material in the current path between the corresponding conductive layer and the conductive pillar, it means that there is no data value in this structure.

To access a memory cell, a word line and a bit line in the access layer, and a conductive layer are decoded. Different program/erase pulses are provided to selected memory cells passing through transistors in the access layer and the conductive layer. By sensing the resistance range, the size of the amorphous phase volume in the selected memory cell is determined. Related information can be found in Papandreou, et al. Drift-Resilient Cell-State Metric for Multilevel PhaseChange Memory, IEEE, IEDM, 5-7Dec .2011, p.3.5.1-3.5.4.

FIG. 2 shows a top view of the core 25 and pad 27 of the phase change material of the access device as in FIG. 1 , and the conductive layer is omitted in the figure. The liner 27 of phase change material is annular and surrounds the core 25 . The bit lines 11 in the access layer are shown in a first direction, and the word lines 17 in the access layer are shown in a vertical direction. The annular interface between the columnar liner 27 and the layers of conductive material (not shown) defines an interface region that includes programmable memory elements.

FIG. 3 is a schematic diagram illustrating the structure of FIG. 1 . The conductive pillar 40 is coupled to an access transistor 41 , and the access transistor is selected by the bit line 42 and the word line 43 . Most of the memory elements 44 - 1 to 44 - n are connected to the conductive pillar 40 .

Each of the memory elements 44-1 to 44-n is coupled to a corresponding conductive plane 45-1 to 45-n, where the conductive plane is provided by the conductive layer material. A side decoder 46 is coupled to the conductive planes and is configured to connect a selected plane to a reference potential, such as the ground plane 47 . The sense amplifier coupled to the bit line (eg, 42 ) is configured to sense the range of resistance that the selected memory cell reduces to represent the data value.

FIG. 4 is a schematic diagram of a 2×2 partial conductive column array as shown in FIG. 3 in a three-dimensional memory array. The access array includes word lines 60,61 and bit lines 62,63. Access devices 64, 65, 66, 67 are located at the intersections of bit lines and word lines. Each access device is coupled to a corresponding conductive post 68 , 69 , 70 , 71 . Each conductive pillar includes an "n" plane deep stack of storage elements. Therefore, the conductive pillar 68 is coupled to the storage elements 72-1 to 72-n. The conductive pillar 69 is coupled to the memory elements 73-1 to 73-n. The conductive pillar 70 is coupled to the memory elements 74-1 to 74-n. The conductive pillar 71 is coupled to the memory elements 75-1 to 75-n. The conductive layer is not shown in FIG. 4 to avoid excessive clutter. The 2×2 array shown in FIG. 4 can be extended to an array formed by thousands of word lines and thousands of bit lines with any number of planes. In an embodiment, the number n of planes may be an exponent of 2, such as 4, 8, 16, 32, 64, 128, etc., for binary coding.

5A to 5D illustrate the volume of the amorphous phase in the memory cell, which is used to represent the data value in the memory structure. Various amorphous phase volumes have different thicknesses of amorphous phase material through the current path of the memory cell, so that the resistance of the memory cell falls within a predetermined resistance range corresponding to a specific data value. In these figures, the illustrated memory cell 300 includes a phase change memory element 302 disposed between a first heating electrode 304 and a second heating electrode 306 . Similar to FIG. 1 , the first heating electrode 304 and the second heating electrode 306 correspond to one of the plurality of conductive layers and conductive pillars. The first heating electrode 304 is in contact with the phase change memory element on the surface 312 , which may be an annular interface between the conductive layer and the conductive pillar. The second heating electrode 306 is in contact with the phase change memory element on the surface 314 , the surface 314 can be the surface of the conductive pillar, and can be larger than the surface 312 to concentrate the current on the surface 312 .

In FIG. 5A, the phase change memory element 302 includes a phase change memory material located in the current path between the first and second heating electrodes 304 and 306, a portion of which is the amorphous phase volume 308-1, so that The memory cells fall between a first resistance range corresponding to the data value "00". In FIG. 5B, the amorphous phase volume 308-2 is greater than the amorphous phase volume 308-1 such that the memory cell falls between a second resistance range corresponding to the data value "01", the second resistance range being greater than the first resistance scope. In FIG. 5C, the amorphous phase volume 308-3 is greater than the amorphous phase volume 308-2, so that the memory cell falls between a third resistance range corresponding to the data value "10", the third resistance range being greater than the second resistance scope. In FIG. 5D, the amorphous phase volume 308-4 is greater than the amorphous phase volume 308-3, so that the memory cell falls between a fourth resistance range corresponding to the data value "11", the fourth resistance range being greater than the third resistance scope. Of course, the memory cells can be configured such that each memory cell only stores one bit, or each memory cell stores any amount of data.

Here, a memory device having a three-dimensional array includes circuitry for programming data, the circuitry being configured to provide a programming pulse to a selected memory cell, the selected memory cell having a pulse shape that depends on the The resistance range of the memory cell (such as the initial amorphous phase thickness), and the target resistance range of the memory cell after the programming pulse (such as the terminated amorphous phase thickness). The circuit includes logic to determine the resistance range of the selected memory cell, such as a pre-program read sequence and a forming circuit pulse to generate a programming pulse having a Pulse shape. The pulse shape is determined by the range of the determined resistance of the selected memory cell and the range of the target resistance.

Figures 6A-6D show graphs of temperature versus time that roughly correspond to pulse shapes in the active region and are selected by the control logic to build in the memory cell structures described herein, for various size of the amorphous phase thickness. FIG. 6A represents a pulse shape with a relatively steep leading edge 400 that increases to a peak 402 and then falls off rapidly at a trailing edge 404 . The peak 402 clearly reaches a temperature above the melting temperature Tm in the phase change material and remains there for a relatively short time. This pulse is designed to initialize the memory cell from an initial state controlled by the crystalline phase material to a state of a first resistance range established by an amorphous phase volume, the first resistance range corresponding to A data value is, for example, "00". For example, when the memory element as shown in FIG. 5A leaves a relatively large amount of crystalline material, the pattern drops rapidly due to the relatively short time above the melting temperature and the steep trailing edge 404, so that the volume of the amorphous phase is sufficient. Cover the contact area between the horizontal conductor and the phase change material.

FIG. 6B represents a pulse shape, the same basic structure as FIG. 6A , with a relatively steep leading edge 410 that increases to a peak 412 and then falls off rapidly at a trailing edge 414 . The peak 412 is designed to reach a temperature above the melting temperature Tm in the phase change material for a moderate amount of time. This pulse is designed to switch a memory cell from a lower resistance range to a second resistance range established by the amorphous phase volume. The second resistance range may correspond to a data value such as "01". The pulses depicted in FIG. 6B result in an amorphous phase volume such as that depicted in FIG. 5B , which is greater than the volume of the amorphous phase caused by the pulses in FIG. 6A .

Figure 6C represents a pulse shape with the same basic structure as Figures 6A and 6B, with a relatively steep leading edge that increases to a peak and then falls off rapidly at the trailing edge. The peak is designed to reach a temperature above the melting temperature Tm in the phase change material for a second longest intermediate time. This pulse is designed to switch a memory cell from a lower resistance range to a state of a third resistance range established by the amorphous phase volume, which may correspond to a data value such as "10". The pulse shown in FIG. 6C results in an amorphous phase volume such as that shown in FIG. 5C that is greater than the volume of the amorphous phase caused by the pulse in FIG. 6B .

Figure 6D represents a pulse shape with the same basic structure as Figures 6A, 6B and 6C, with a relatively steep leading edge that increases to a peak and then falls off rapidly at the trailing edge. The peak is designed to reach a temperature above the melting temperature Tm in the phase change material and to maintain it for the longest time among the pulses. This pulse is designed to switch a memory cell from a lower resistance range to a state of a fourth resistance range established by the amorphous phase volume. The fourth resistance range may correspond to a data value such as "11". The pulse shown in FIG. 6D results in an amorphous phase volume such as that shown in FIG. 5D that is greater than the volume of the amorphous phase caused by the pulse in FIG. 6C .

7A to 7C are suitable for increasing the size of the volume of the amorphous phase in the memory cell. To reduce the size of the amorphous phase volume, a different pulse shape is required. FIG. 7A shows a pulse shape in the form of a temperature versus time graph, which can form a transition from a high resistance state to a resistance state with a smaller amorphous phase volume. The high resistance state, for example, corresponds to the data value "01 The resistance state of ", the resistance state of the amorphous phase volume is based on a resistance state corresponding to the data value "00". The pulse includes a first portion 550 in which the temperature of the phase change volume is increased above a crystallization transition temperature TC and a second portion 552 in which the temperature of the phase change volume The temperature is sharply increased to a peak 577 above a melting temperature. The energy supplied during the first part of the pulse is used to re-crystallize the amorphous phase volume in preparation for the second part of the pulse, which is used to set the target amorphous phase of the pulse phase volume. Stage 574 exceeds the melting temperature Tm to a peak, and the energy provided by stage 574 is approximately corresponding to the volume of the amorphous phase.

FIG. 7B shows a pulse shape that can be used to switch from a higher resistance state to a lower resistance state of an amorphous phase volume. The high resistance state is, for example, the resistance state corresponding to the data value "10". The resistance state of the crystal phase volume corresponds to the data value "01". In this embodiment, the pulse shape of FIG. 7B is the same basic configuration as that of FIG. 7A. In one embodiment, the difference is the energy provided above the melting temperature. In another embodiment, the difference is the length of the initial crystalline state, and the energy provided beyond the melting temperature.

FIG. 7C shows another pulse shape that can be used to switch from a higher resistance state to a lower resistance state of an amorphous phase volume. The high resistance state is, for example, the resistance state corresponding to the data value "11", The resistance state of the amorphous phase volume corresponds to the data value "10". Likewise, in this embodiment, the pulse shape in FIG. 7C is the same basic configuration as those in FIGS. 7A and 7B . In one embodiment, the difference is the energy provided above the melting temperature. In another embodiment, the difference is the length of the initial crystalline state, and the energy provided beyond the melting temperature.

Thus, programming of memory devices according to embodiments of the present invention may include control logic that selects a pulse shape based on the initial and target states of the memory cells.

8 is a flow diagram representing a control logic sequence that may be used to program a memory cell, including selecting a pulse shape based on an initial state and a target state of the memory cell. A memory device including a three-dimensional memory structure described herein may receive programming instructions to establish a specific data value in a target memory cell, or a target word or page of memory cells (580). The device controller then performs a pre-program read operation to determine the initial resistance state of the target memory cell (582). The controller then provides a programming pulse (584) based on the initial resistance state and the target data value, the programming pulse having an appropriate pulse shape selected from FIGS. 6A-6D and 7A-7C.

FIG. 9 is a cross-sectional view of a stacked memory structure with programmed memory cells having amorphous phase thicknesses of different sizes. The different sizes of the amorphous phase thicknesses cause the memory cells to fall between different resistance ranges corresponding to the stored data values. The stacked memory structure includes a conductive pillar 600 having a plurality of conductive layers 602-1 to 602-8 and a plurality of insulating layers (eg 604) separating the plurality of conductive layers. The programmable element of each memory cell is located in a portion of the memory material of the liner 606 of memory material located in the intersection of the conductive pillar 600 and the corresponding conductive layer. Each conductive layer in the plurality of conductive layers is coupled to a layer of decoder 608 .

The stacked memory structure includes eight memory cells, 610 , 612 , 614 , 616 , 618 , 620 , 622 and 624 in this embodiment. The memory cells are formed in liners 606 located between the corresponding conductive layers 602 - 1 to 602 - 8 and the conductive pillars 600 . An access device 601 in the access layer is used to select the drawn conductive pillars. Likewise, a layer decoder 608 is used to select a planar conductive layer.

Each memory cell 610, 612, 614, 616, 618, 620, 622, and 624 has an annular amorphous phase volume 605, 607, 609, 611, 613, 615, 617, and 619 of phase change material in the interface, The interface is formed on the periphery of the pads 606 surrounding the corresponding conductive layers 602-1 to 602-8. The resistance of each memory cell depends in part on the size of the amorphous phase volume. In this embodiment, the memory cells 610, 614, 618, and 622 have a resistance falling between a first resistance range, and the first resistance range may correspond to the data value "0", which is formed by the smaller-sized amorphous phase. Volumes 605, 609, 613 and 617 are represented. The memory cells 612, 616, 620, and 624 have a resistance falling between a second resistance range, which may correspond to the data value "1", and is formed by the larger-sized amorphous phase volumes 607, 611, 615 with 619 stands.

10 is a cross-sectional view of another form of stacked memory structure, wherein the conductive layer includes a phase change material and has programmed memory cells, so that the conductive layer has different sizes of amorphous phase thickness. The different sizes of the amorphous phase thicknesses cause the memory cells to fall between different resistance ranges corresponding to the stored data values. The stacked memory structure includes a conductive pillar 630 . The conductive pillar 630 extends through a top insulating layer 636, a plurality of conductive layers 632-1 to 632-8, and a plurality of insulating layers (eg, 634) separating the plurality of conductive layers. The programmable element of each memory cell is located in a portion of the memory material in the corresponding conductive layer. Each conductive layer in the plurality of conductive layers is coupled to a layer of decoder 658 .

The stacked memory structure includes eight memory cells, 640 , 642 , 644 , 646 , 648 , 650 , 652 and 654 in this embodiment. The memory cells are formed at the interfaces of the corresponding conductive layers 632 - 1 to 632 - 8 and the conductive pillars 630 . An access device 651 in the access layer is used to select the drawn conductive pillars.

Each memory cell 640, 642, 644, 646, 648, 650, 652, and 654 has an annular amorphous phase volume 635, 637, 639, 641, 643, 645, 647, and 649 of phase change material in the interface, The interface is formed around the interior of the pads surrounding the corresponding conductive layers 632-1 to 632-8. The resistance of each memory cell depends in part on the size of the amorphous phase volume. In this embodiment, the memory cells 640, 644, 648, and 652 have a resistance falling between a first resistance range, and the first resistance range may correspond to the data value "0", which is formed by the smaller-sized amorphous phase. Volumes 635, 639, 643 and 647 are represented. The memory cells 642, 646, 650, and 654 have a resistance falling between a second resistance range, which may correspond to the data value "1", and is formed by the larger-sized amorphous phase volumes 637, 641, 645 with 649 reps.

11 to 14 illustrate various stages of the manufacturing process of the three-dimensional memory structure according to the embodiment of the present invention. The fabrication process includes forming an access array 700 on a substrate. This stage can be accomplished using CMOS technology, for example, standard horizontal transistors or vertical transistors as shown in FIG. 11 . In the embodiment shown in FIG. 11 , the fabrication process includes forming an ILD layer 702 on the access array, and forming contact plugs 704 , 706 through the ILD layer 702 . The top surfaces of the contact plugs 704 , 706 are exposed to the top surface of the ILD layer 702 . Over the interlevel dielectric layer 702, insulating material (isolators 720, 722, 724, 726) and conductive material (708, 710, 712, 714) are alternately formed. A capping dielectric layer 728 is formed over the topmost layer of conductive material. The dielectric material may include silicon nitride, silicon oxide, or other suitable insulating materials used to form memory or formed by combining dielectric materials. The conductive material used to form the conductive layers 708, 710, 712, 714 includes a conductive "heater" material such as titanium nitride, titanium aluminum nitride, tantalum nitride ( tantalum nitride) and so on. In other embodiments, the conductive layer may include a refractory metal, such as tungsten. In other embodiments, the conductive layer may comprise a conductor such as copper or aluminum with low electrical resistance. The conductive layer is deposited by a blanket deposition process, and planar conductors and insulating layers are alternately formed on the top surfaces of the contact plugs 704 and 706 according to the selected material. Of course, in a memory implementation, there may be an array of thousands or tens of thousands of contact plugs under the stack of conductive layers.

FIG. 12 illustrates the stage in the fabrication process where contact plugs 704, 706 are exposed, after etching vias 730, 731 through the conductive layer stack. The vias 730, 731 may be circular or other shapes such as rectangles etc., depending on the fabrication technique used to form the vias. In one embodiment, the sidewalls of the through holes 730 and 731 are substantially vertical.

As shown in FIG. 13, the next stage of the manufacturing process is to form liners 732, 733 between the vias, including selecting a phase change material at the interface between the conductive layers as the memory element of the memory cell. In one embodiment, the phase change material may include a relatively high resistance as a crystalline phase, such as depositing a material such as Ge _{x Sby Tez} filled with germanium. After depositing the high resistance material, it is an initial step to initialize all memory cells so that the memory cells include at least one small volume of amorphous phase material to control intralayer leakage as discussed above.

FIG. 14 shows a stage of the manufacturing process after filling the remaining area of the via hole with studs 734, 735 of conductive material, such as a crystalline phase change material. In one process, the liners 732, ₇₃₃ may be deposited as a _germanium -filled material _GexSbyTez . Then, after forming a liner with sufficient thickness, the deposition method can be changed to a _{GexSbyTez material} with less _germanium . In another embodiment, the cores 734, 735 of the conductive posts may comprise different types of conductive materials as discussed above.

As shown in FIG. 14, after forming the conductive pillars, the conductive material may be planarized and a cap insulator 740 may be formed on the stack.

FIG. 15 illustrates a three-dimensional memory structure according to another embodiment of the present invention. In this structure, the memory device includes an access array 800, the access array 800 has an inner dielectric layer 802 and a conductive plug 806, the inner dielectric layer 802 is located on the access array 800, the conductive plug 806 extending through the interlayer dielectric layer 802 . The insulating layers 820 , 822 , 824 , 826 , 828 and the conductive layers 808 , 810 , 812 , 814 are deposited in a cladding form and stacked alternately. However, in this embodiment the overlying conductive layer is patterned to provide patches of phase change material at the vias forming the conductive pillars. In this embodiment, the memory cell includes a phase change material patch 851 surrounding the conductive pillar 855 . The balanced conductive layer 850 includes a conductor compatible phase change material, such as titanium nitride, metal, or other compatible conductive material. Amorphous phase volume 852 is formed around the interior of the interface of patch 851 of phase change material and conductive pillar 855 .

The embodiment shown in FIG. 15 includes four storage units 860 , 862 , 864 , 866 . Each memory cell has an amorphous volume corresponding to a data value. In this embodiment, memory cells 860, 864 and 866 have a smaller amorphous volume corresponding to a lower resistance range, and memory cell 862 has a larger amorphous volume corresponding to a higher resistance scope. In an embodiment, an entire patch of phase change material may be set in the amorphous phase to establish a resistance range where the highest value represents a data value.

FIGS. 16A-16B include a flowchart of a fabrication method for fabricating the structure as depicted in FIGS. 11-14 . According to the present invention, a first step 900 includes forming a memory cell access layer, including bit lines, word lines, access devices, and contact pads. At this stage, peripheral circuitry on the integrated circuit substrate is also formed. After this stage, the top surface of the memory cell access layer in the memory region of the memory device has an array of contact pads, including contact plugs 704, 706 as shown in FIG. 11 . At this stage, standard CMOS fabrication techniques can be applied, including all necessary patterning and etching processes, to form surrounding circuitry and access devices. The contact pads and interconnection circuitry in the memory cell access layer should be made of a refractory metal such as tungsten so that the thermal budget involved in depositing a large number of stacked layers will not interfere with the underlying interconnection circuitry (underlying interconnects).

Next, an interlayer dielectric layer (eg 702) is deposited on the memory cell access layer (901). The interlayer dielectric layer can be silicon dioxide, silicon oxynitride, silicon nitride or other interlayer dielectric materials. In the next step, the conductive layer and the insulating layer are deposited alternately. Drape deposition provides multiple conductive layers (eg 708, 710, 712, 714) as electrode planes. The conductive layer can be relatively highly doped n-type polysilicon (n+ polysilicon), heating material, metal, phase change material or other conductive material depending on the selected morphology. Generally, the thickness of the conductive layer can be 50 nanometers. The insulating layer insulates the conductive layers from each other. In one embodiment, the insulating layer may have a thickness of 50 nanometers. In other embodiments, there may be thicker or thinner conductive and insulating materials as desired or needed for a particular implementation. Next, a photolithography patterning process is performed, and the storage column via (903) is opened, and the storage column via passes through most of the conductive planes corresponding to the contact pads on the access layer of the memory unit. A reactive ion etching process may be performed to form deep and high proportion vias through the silicon dioxide and conductive layers to provide conductive pillar vias.

After opening the via, a liner of phase change material is deposited on the sidewall of the memory pillar via (904). Phase change materials can be deposited using atomic layer deposition or chemical vapor deposition techniques. Suitable materials include chalcogenides, such as _{chalcogenides} filled with _germanium material _GexSbyTez . Generally, the thickness of the phase change material layer can be 5 to 50 nanometers, or more or less.

The resulting layer of phase change material can be anisotropically etched to open the bottom of the conductive pillar via and expose the underlying contact pad. In the next step, the central electrode material is deposited on the conductive pillar via.

Continuing to FIG. 16B, after depositing the central electrode material, the defining structures are etched by a chemical mechanical polishing process or other planarization process (906).

Next, an interlayer insulating layer is deposited on the structure (907).

After forming the plurality of conductive layers, a taper etch process is used to define contact areas on the perimeter of the conductive layers (908). After patterning the perimeter of the conductive layer, an insulating fill is deposited and planarized over the structure. Next, the vias are opened through the insulating fill to the contact pattern at the periphery of the conductive layer.

In this embodiment, the bias arrangement state machine 1128 is used as a controller to control the bias arrangement supply voltage 1130 , for example, to provide a programming voltage according to the previously described programming technique for programming memory cells. In the art, controllers may be implemented as special-purpose logic circuitry. In another embodiment, the controller includes a general purpose processor that executes a computer program on the same integrated circuit to control the operation of the device. In yet another embodiment, mixed special purpose logic circuits and general purpose processors may be used for processor implementation. The controller is configured to program a value in a memory cell having a data value represented by a non-overlapping range of a plurality of resistors, the non-overlapping range of a plurality of resistors including a resistance range formed by the memory cell The phase change through the current path is established by the thickness of the individual amorphous phases of the memory material. Using the voltage supply and logic circuitry in block 1130, the controller is configured to provide a programming pulse to a selected memory cell having a pulse shape based on the range of memory cell resistance prior to providing the programming pulse, and the programmed Determined by the target resistance range of the memory cell after the pulse. The logic of the controller may include a sequence logic for determining the resistance range of the selected memory cell and a pulse forming circuit for generating programming pulses having pulse shapes as shown in FIGS. 6A-6D and 7A-7C, The programming pulse is in response to the determined resistance range and the target resistance range of the selected memory cell.

The vias are filled with tungsten or other contact material and a metallization process is provided to provide interconnection between the contact pattern to the conductive layer and the planar decoding circuitry on the device (910). Finally, a back end of line (BEOL) process is performed to complete the integrated circuit (911).

FIG. 17 shows a simplified block diagram of an integrated circuit according to an embodiment of the present invention. Integrated circuit 1100 includes a three-dimensional memory array 1102 having programmed memory cells of various resistance ranges greater than or equal to a threshold high resistance range. A column decoder 1104 is coupled to a plurality of word lines 1106 and arranged along a column of the memory array 1102 . A row decoder 1108 is coupled to the plurality of bit lines 1110 and arranged along a row of the memory array 1102 for reading data to or programming data from the memory cells in the array 1102 . A layer of decoders 1112 is coupled to most electrode planes on line segment 1114 of memory array 1104 . Addresses are provided to row decoder 1108 , column decoder 1104 and layer decoder 1112 via bus 1116 . In this embodiment, a page buffer 1118 is coupled to the row decoder 1108 through a data bus 1120 . Data is transferred to the page buffer 1118 of the integrated circuit via data input lines 1122 from internal or external input/output ports or other data sources on the integrated circuit. In the illustrated embodiment, other circuits 1124 are included in integrated circuits, such as a general purpose processor, special purpose application circuitry, or a system-on-chip -a-chip functionality) a mix of modules. Data is transmitted from the page buffer 1118 to the I/O port on the integrated circuit through the data output line 1126, or transmitted to other internal or external data terminals connected to the integrated circuit.

A fully amorphous, multi-bit per memory cell, phase-change memory cell configuration in a three-dimensional memory structure is described herein. A word line and a bit line are included in an access array and connected to a storage conductive column. The word line and the bit line are used for decoding a transistor or other access devices. The storage conductive column extends through the planar conductor, and has a phase change memory cell located in an interface where the planar conductor crosses the conductive column.

The sidewalls of the storage conductive columns are contacted and surrounded by the multi-layered conductive layer. A memory cell including a current path is formed in each intersection between the corresponding conductive pillar and the conductive layer.

In order to isolate the leakage current between each layer, only the amorphous phase volume with different thicknesses passing through the current path in the phase change material is used to store data.

In the present invention, a programming procedure can be used to program all amorphous phase states. The memory cell structures, manufacturing methods, and operating methods described herein are applicable to high-density three-dimensional memory arrays. However, this technique can also be applied to single layer arrays as well as smaller groups of phase change memory cells.

To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims (8)

1. A memory device comprising: an access array; a plurality of conductive layers separated from each other and from the access array by a plurality of insulating layers; an array of conductive pillars extending through the plurality of conductive layers, the conductive pillars in the array of conductive pillars correspondingly contacting the access devices in the access array; A plurality of memory cells having a phase change memory material in a current path of the plurality of memory cells, the current path being between the corresponding conductive pillars and the corresponding conductive layers, all of the plurality of memory cells The phase change memory material stores data values, and the phase change memory material has different thicknesses in an amorphous phase in the current path; and A circuit, in the plurality of memory cells, the circuit is coupled to the access array and the plurality of conductive layers, and the circuit for programming data has a plurality of data values, and these data values are determined by non-conductive layers of a plurality of resistors. The overlapping ranges represent that the non-overlapping ranges of the resistances include a resistance range established by different amorphous phase thicknesses of the phase change memory material. 2. The memory device of claim 1 , wherein different non-zero thicknesses of an amorphous phase of the phase change memory material represent data stored in the memory cell, none of which is stored in the plurality of memory cells The data value of is corresponding to a crystalline phase of the phase change memory material. 3. The memory device according to claim 1, wherein the circuit comprises a logic and a pulse, the logic is used to determine a resistance range of a selected memory cell, the pulse forming circuit is used to generate a programming pulse, The programming pulse has a pulse shape selected from a resistance range corresponding to the selected memory cell and a target resistance range. 4. A method of manufacturing a memory device, comprising: forming an access array; forming a plurality of conductive layers, the plurality of conductive layers are located above or below the access array, the plurality of conductive layers are separated from each other and from the access array by a plurality of insulating layers; An array of conductive pillars is formed, the array of conductive pillars extends through the plurality of conductive layers, the conductive pillars in the array of conductive pillars correspond to the access devices in the access array, and multiple conductive pillars are defined in the plurality of conductive layers. interface regions between the conductive posts and the plurality of conductive layers; forming a plurality of memory cells in the interface areas, the interface areas include a current path between the corresponding conductive pillars and the plurality of conductive layers, each memory element includes a phase change memory material; and Forming a circuit coupled to the access array and the plurality of conductive layers for programming data in the plurality of memory cells, the plurality of memory cells have a plurality of data values, and these data values are non-overlapped by a plurality of resistors As represented by the ranges, the non-overlapping ranges of the resistances include a range of resistances established with different amorphous phase thicknesses of the phase change memory material through the interface regions in the plurality of memory cells. 5. The method of claim 4, wherein forming the plurality of conductive layers comprises blanket depositing the phase change memory material, followed by forming a plurality of patches of the phase change memory material. 6. The manufacturing method according to claim 4, wherein forming the plurality of conductive layers comprises: forming a plurality of cladding layers of conductive material; and A plurality of cladding layers of insulating materials are formed, and the cladding layers of insulating materials are interposed between the cladding layers of conductive materials. 7. The manufacturing method according to claim 4, wherein forming the array of conductive pillars comprises: defining a via through the plurality of conductive layers; depositing a first phase change memory material layer on the sidewall of the via; and The via is filled with a second phase change memory material. 8. A memory device comprising: a first conductor; a second conductor; a plurality of memory cells comprising phase change memory material in an interface between the first conductor and the second conductor, wherein an amorphous phase of the phase change memory material has different non-zero thicknesses, representing data stored in the memory cell, none of the data values stored in the plurality of memory cells corresponds to a crystalline phase of the phase change memory material; an access device coupled to the first conductor; and a circuit, coupled to the access device and the second conductor, the circuit is used to program data in the memory cell, and the circuit has a plurality of data values determined by non-overlapping ranges of a plurality of resistors Representatively, the non-overlapping range of resistances is established with different amorphous phase thicknesses of the phase change memory material in the memory cell.