CN103928336A - PMOS transistor and manufacturing method thereof - Google Patents

Abstract

The present invention provides a PMOS transistor and a preparation method thereof. The present invention adopts a method of sequentially epitaxially growing a first stress adjustment layer, a second stress adjustment layer and a stress maintenance layer when forming a source region and a drain region of a PMOS transistor, wherein, The lattice constants of the first stress adjustment layer and the second stress adjustment layer increase sequentially; when the epitaxial second stress adjustment layer is doped with an element with a larger lattice constant than the Ge element, the second stress adjustment layer forms an insulating layer. Most of the source region and the drain region provide greater compressive stress for the channel, so that it has higher carrier mobility and improves the working current of the device; the second stress adjustment layer between the substrate and the second A stress adjustment layer is used as a stress buffer layer to reduce defects caused by excessive lattice mismatch between the two; the present invention adopts the first and second stress adjustment layers spaced apart from each other to form a sandwich structure to further reduce the stress of the second stress adjustment layer. Defects caused by excessive lattice mismatch with the substrate.

Description

A kind of PMOS transistor and preparation method thereof

technical field

The invention belongs to the technical field of semiconductor devices, and relates to a transistor and a preparation method thereof, in particular to a PMOS transistor and a preparation method thereof.

Background technique

For some time to come, silicon-based complementary metal-oxide-semiconductor (CMOS) transistors are the basic units in modern logic circuits, including PMOS and NMOS, and each PMOS or NMOS transistor is located on a doped well, and is composed of A p-type or n-type source region, a drain region, and a channel (Channel) between the source region and the drain region in the substrate on both sides of the gate (Gate).

In the existing semiconductor technology, the method for forming a transistor generally includes: providing a silicon substrate, forming a well region and an isolation structure in the silicon substrate; forming a gate dielectric layer and a gate on the surface of the silicon substrate in sequence; Sidewalls are formed around it; ion implantation is performed on the silicon substrate with the sidewalls, gate dielectric and gate as a mask to form source and drain, and the well region between the source and drain is the channel region.

With the development of semiconductor technology, the feature size of devices in integrated circuits is getting smaller and smaller. When the manufacturing process of complementary metal oxide semiconductors progresses to the micron level, since the channel between the source/drain regions becomes shorter, when the length of the channel region is reduced to a certain value, a short channel will be generated. Channel Effect (Short Channel Effect) and Hot Carrier Effect (HotCarrier Effect) and thus cause the device to fail to operate. In other words, since the existence of the short channel effect will affect the performance of the device, it also hinders the further reduction of the feature size of the device in the integrated circuit.

In order to avoid short-channel effects and hot-carrier effects, the source/drain design of CMOS with micron-scale and below manufacturing processes will adopt a lightly doped drain (Lightly Doped Drain, LDD) structure, that is, in The portion adjacent to the source/drain region under the gate structure forms a low-doped region with a shallower depth and the same doping type as the source/drain region, so as to reduce the electric field of the channel region.

The goal of the current research on the basic technology of integrated circuits is to obtain higher unit integration, higher circuit speed, lower power consumption per unit function and unit function cost. In the process of shrinking device size proportionally, higher integration and operating frequency mean greater power consumption. Reducing the power supply voltage VDD is a general choice to reduce circuit power consumption, but the reduction of VDD will cause the drive of the device Decreased power and speed. Reducing the threshold voltage and thinning the thickness of the gate dielectric can improve the current driving capability of the device, but at the same time it will lead to an increase in the subthreshold leakage current and the gate leakage current, thereby increasing the static power consumption. This is the current "power consumption" faced by ICs. -speed" dilemma.

Improving device channel mobility is the key to solving the above dilemma. On the basis of a substantial increase in channel mobility, on the one hand, a lower VDD and a higher threshold drain voltage can be used, and at the same time, sufficient current drive capability and speed of the device can be ensured.

It is known that introducing tensile stress into the channel of N-type metal-oxide-semiconductor field-effect transistor (NMOSFET) can improve the channel mobility of NMOSFET, and introducing compressive stress into the channel of P-type metal-oxide-semiconductor field-effect transistor (PMOSFET) The channel mobility of the PMOSFET can be improved.

Current strained silicon technology is mainly divided into global strain and local strain. The global strain technology means that the stress is generated by the substrate and can cover all transistor regions fabricated on the substrate. This stress is usually biaxial. Materials that can generate global strain include SiGe on Insulator (SGOI), SiGe virtual substrate, etc. Local straining techniques typically apply stress to the semiconductor channel region only locally in the semiconductor device. Local strain technology mainly includes embedded silicon germanium (SiGe) or silicon carbide (SiC) in the source and drain regions, dual stress layers (Dual Stress Layers, DSL) and shallow trench isolation (ShallowTrench Isolation, STI), etc. The global strain is complicated to manufacture and the cost is high, while the local strain has good compatibility with the traditional CMOS manufacturing process and the manufacturing method is simple, so only a small increase in cost is required to improve the performance of semiconductor devices, so it is widely used in the industry.

For PMOS transistors, embedded silicon germanium (SiGe) technology can effectively improve hole mobility, thereby improving the performance of PMOS transistors. The so-called embedded silicon germanium technology refers to forming a SiGe epitaxial layer in the silicon substrate next to the channel of the PMOS transistor. The SiGe epitaxial layer will generate compressive stress on the channel, thereby improving the mobility of holes.

However, in order to achieve the purpose of further improving the carrier mobility in devices with smaller dimensions, it is necessary to seek new breakthroughs in enhancing the stress on the device channel.

Contents of the invention

In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a PMOS transistor and its preparation method. The technical problem solved by the present invention is to further enhance the compressive stress generated by the source region and the drain region of the device on the channel. , so as to further increase the carrier mobility in the channel to increase the working current of the device.

In order to achieve the above object and other related objects, the present invention provides a method for preparing a PMOS transistor. The method at least includes the following steps: providing a semiconductor substrate, and forming a PMOS transistor including a source region on the top of the semiconductor substrate of the prefabricated PMOS transistor. , the active region of the drain region and the channel region, and the source region and the drain region exert compressive stress on the channel region; wherein, the specific steps for preparing the source region and the drain region are:

1) forming trenches on the top of the substrate where the source region and the drain region are pre-prepared;

2) In the trench, first epitaxially grow the first stress adjustment layer, and then epitaxially grow the second stress adjustment layer, wherein the lattice constants of the substrate, the first stress adjustment layer and the second stress adjustment layer increase in turn;

3) Repeat step 2) n times, n is an integer and greater than or equal to 0;

4) When the upper surface of the second stress adjustment layer is on the same plane as the upper surface of the substrate, epitaxially grow on the upper surface of the trench filled with the first stress adjustment layer and the second stress adjustment layer A stress-retaining layer, wherein the material of the stress-retaining layer is consistent with the material of the first stress-regulating layer or the second stress-regulating layer.

Optionally, when n is greater than or equal to 1 in the step 3), the first stress adjustment layer and the second stress adjustment layer epitaxially grown in the trench are separated from each other to form a sandwich structure.

Optionally, during the epitaxial growth of the first stress adjustment layer and/or the second stress adjustment layer in the step 2), the gas containing B element is also introduced at the same time, so as to form the first stress adjustment layer doped with B element and /or a second stress regulating layer.

Optionally, the stress holding layer has a thickness of 10-20 nm.

Optionally, the thickness of the first stress adjustment layer is 2-10 nm.

Optionally, the second stress adjustment layer located between the two first stress adjustment layers has a thickness of 20-30 nm.

Optionally, the substrate material is any one of Si, Si _1-x C _x or Si _1-xy Ge _y C _x , wherein the range of x is 0.01~0.1, and the range of y is 0.1~0.3; The first stress adjustment layer is a SiGe layer; the second stress adjustment layer is a SiSn layer or a SiPb layer.

The present invention also provides a PMOS transistor, and the PMOS transistor includes at least:

An active region is formed with a channel region, a source region and a drain region, and the source region and the drain region apply compressive stress to the channel region, the source region and the drain region are formed in a semiconductor substrate top;

The source region and the drain region include a stress-holding layer and m groups of first stress-adjusting layers stacked in sequence under the stress-holding layer and a second stress-adjusting layer formed on the first stress-adjusting layer, Wherein, m is an integer greater than or equal to 1, and the lattice constants of the substrate, the first stress adjustment layer and the second stress adjustment layer increase sequentially, and the material of the stress holding layer is consistent with the first stress The material of the adjustment layer or the second stress adjustment layer is the same.

Optionally, when m is greater than or equal to 2, the first stress adjustment layer and the second stress adjustment layer that are spaced apart form a sandwich structure.

Optionally, the first stress adjustment layer and/or the second stress adjustment layer contains B doping elements.

Optionally, the stress holding layer has a thickness of 10-20 nm.

Optionally, the thickness of the first stress adjustment layer is 2-10 nm.

Optionally, the second stress adjustment layer located between the two first stress adjustment layers has a thickness of 20-30 nm.

Optionally, the substrate material is any one of Si, Si _1-x C _x or Si _1-xy Ge _y C _x , wherein the range of x is 0.01~0.1, and the range of y is 0.1~0.3; The first stress adjustment layer is a SiGe layer; the second stress adjustment layer is a SiSn layer or a SiPb layer.

As mentioned above, a PMOS transistor of the present invention and its preparation method have the following beneficial effects: In order to further improve the compressive stress of the source region and the drain region in the PMOS transistor to the channel, the present invention will increase the pressure on the source region and the drain region. In the epitaxial growth of the pole region, the Sn element or the Pb element whose atomic weight and lattice constant are larger than the Ge element and which are in the same group as the substrate are used to replace the Ge element for doping. Therefore, from the PMOS transistor source region and In terms of the compressive stress generated by the drain region on the channel, compared with the use of simple SiGe as the source region and drain region in the prior art, the present invention uses a second stress adjustment layer with a lattice constant larger than SiGe to form an insulating layer. Most of the source region and the drain region can provide greater compressive stress for the channel, further realize higher carrier mobility in the channel, and then improve the working current of the device; in addition, the present invention A first stress adjustment layer is formed between the adjustment layer and the substrate as a stress buffer layer to reduce defects caused by excessive lattice mismatch between the second stress adjustment layer and the substrate; at the same time, the present invention adopts stress retention The layer maintains the stress of the first and second stress adjustment layers epitaxially grown in the source region and the drain region, avoiding stress release in the source region and the drain region; further, the source region and the drain region of the present invention, The sandwich structure composed of the first and second stress adjustment layers spaced apart from each other is also adopted, while further reducing the defects caused by excessive lattice mismatch between the second stress adjustment layer and the substrate, it ensures the Compared with the prior art, the source region and the drain region of the sandwich structure can provide larger compressive stress for the channel.

Description of drawings

1 to 4 are schematic structural diagrams of each step of a method for manufacturing a PMOS transistor in Embodiment 1 of the present invention, wherein FIG. 4 is a schematic structural diagram of a PMOS transistor formed by the manufacturing method.

5 to 7 are schematic structural diagrams of each step of a method for manufacturing a PMOS transistor in Example 2 of the present invention, wherein FIG. 7 is a schematic structural diagram of a PMOS transistor formed by the manufacturing method.

Component designation description

1 Substrate

2 Groove

3 gate dielectric layer

4 grid

5 source region, drain region

51 The first stress adjustment layer

52 Second stress adjustment layer

53 Stress holding layer

Detailed ways

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

See Figures 1 through 7. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.

For PMOS transistors, embedded silicon germanium (SiGe) technology can effectively improve hole mobility, thereby improving the performance of PMOS transistors. The so-called embedded silicon germanium technology refers to forming a SiGe epitaxial layer in the silicon substrate next to the channel of the PMOS transistor. The SiGe epitaxial layer will generate compressive stress on the channel, thereby improving the mobility of holes.

However, in order to achieve the purpose of further improving the carrier mobility in devices with smaller dimensions, it is necessary to seek new breakthroughs in enhancing the stress on the device channel.

In view of this, the present invention provides a kind of preparation method of PMOS transistor, comprises the following steps at least: Provide a semiconductor substrate, form the source region, drain region and channel region on the top of the semiconductor substrate of prefabricated PMOS transistor active region, and the source region and the drain region exert compressive stress on the channel region; wherein, the specific steps of preparing the source region and the drain region are: 1) on the top of the substrate Pre-preparing the positions of the source region and the drain region respectively to form trenches; 2) In the trenches, first epitaxially grow the first stress adjustment layer, and then epitaxially grow the second stress adjustment layer, wherein the The lattice constants of the substrate, the first stress adjustment layer, and the second stress adjustment layer increase sequentially; 3) Repeat step 2) n times, where n is an integer and greater than or equal to 0; 4) When the second stress adjustment layer When the upper surface is on the same plane as the upper surface of the substrate, a stress holding layer is epitaxially grown on the upper surface of the groove filled with the first stress adjusting layer and the second stress adjusting layer, wherein the stress holding layer The material is consistent with the material of the first stress adjustment layer or the second stress adjustment layer.

In the present invention, when the second stress adjustment layer is epitaxially grown, an element with a larger lattice constant than Ge is used for doping, so that the second stress adjustment layer forms most of the source region and the drain region, providing a more stable channel. The large compressive stress makes it have higher carrier mobility, thereby increasing the operating current of the device; the first stress adjustment layer formed between the second stress adjustment layer and the substrate acts as a stress buffer layer to reduce both Defects caused by excessive lattice mismatch between them; at the same time, the present invention uses the stress holding layer to carry out stress holding on the first and second stress adjusting layers epitaxially grown in the source region and the drain region, avoiding the source stress release in the region and the drain region; the source region and the drain region of the present invention also adopt a sandwich structure consisting of the first and second stress adjustment layers spaced apart from each other, further reducing the excessive gap between the second stress adjustment layer and the substrate. Defects caused by lattice mismatch.

Embodiment one

As shown in Fig. 1 to Fig. 4, the present invention provides a kind of preparation method of PMOS transistor, described preparation method at least comprises the following steps: provide a semiconductor substrate 1, on the top of substrate 1 of prefabricated PMOS transistor, form region, the active region of the drain region and the channel region, and the source region and the drain region exert compressive stress on the channel region; wherein, the specific steps of preparing the source region and the drain region are as follows :

Step 1) is first performed, as shown in FIG. 1 , grooves 2 are respectively formed on the top of the substrate 1 where the source region and the drain region are pre-prepared, wherein the shape of the cross section of the groove 2 is not It can be circular or sigma-shaped, etc. In this embodiment, the cross-sectional shape of the groove 2 is shown in FIG. 1 . It should be pointed out that in FIG. 1 , between the trenches 2 and formed on the surface of the substrate 1 are the gate dielectric layer 3 and the gate 4 .

It should be noted that the material of the substrate 1 is Si, Si _1-x C _x , Si _1-xy Ge _y C _x , where x ranges from 0.01 to 0.1, and y ranges from 0.1 to 0.3. In the first embodiment, the substrate 1 is a bulk silicon substrate, but it is not limited thereto. In another embodiment, when the substrate material is silicon, the substrate can also be a layer of silicon on top of the semiconductor substrate. Then go to step 2).

In step 2), as shown in FIG. 2 and FIG. 3 , in the trench 2, the first stress adjustment layer 51 is epitaxially grown first, and then the second stress adjustment layer 52 is epitaxially grown, wherein the substrate 1. The lattice constants of the first stress adjustment layer 51 and the second stress adjustment layer 52 increase sequentially; the first stress adjustment layer 51 is a SiGe layer, and the second stress adjustment layer 52 is a SiSn layer or a SiPb layer; The thickness of the first stress adjustment layer is 2-10nm; when the first stress adjustment layer 51 and/or the second stress adjustment layer 52 are epitaxially grown, the gas containing B element is also introduced at the same time to form a B element-doped The first stress adjustment layer 51 and/or the second stress adjustment layer 52 are used to reduce the resistance of the source region and the drain region.

In the first embodiment, the first stress adjustment layer 51 is a SiGe layer, and the second stress adjustment layer 52 is a SiSn layer. In the first embodiment, when the temperature is 500-800°C, the first stress adjustment layer 51 is epitaxially grown in the trench 2 of the substrate 1 (Si), and the same family as the substrate 1 (Si) is used Ge element is doped and grown, wherein, the flow rate of the doping source containing Ge is 0.1slm~1.0slm, and the feeding time is 10min~30min; further, in the above epitaxial growth process, the gas containing B element is also fed, To form the first stress adjustment layer 51 (SiGe) doped with B element, so as to reduce the resistance of the first stress adjustment layer 51, in the first embodiment, the first stress adjustment layer 51 (SiGe) The thickness is preferably 6nm; then, when the temperature is 500-800°C, continue to epitaxially grow the second stress-regulating layer 52 on the first stress-regulating layer 51, and adopt the element whose atomic weight and lattice constant are larger than Ge and compatible with the substrate. The bottom (Si) is doped with Sn elements of the same group instead of Ge elements. The flow rate of the doping source containing Sn is 0.1slm~1.0slm, and the access time is 10min~60min. At the same time, during the epitaxial growth process, At the same time, the gas containing B element is introduced to form the second stress adjustment layer 52 (SiSn) doped with B element, so as to reduce the resistance of the second stress adjustment layer 52 . It should be noted that, in another embodiment, when the second stress adjustment layer is SiPb, Pb element is used instead of Ge element for doping.

It should be pointed out that, since the atomic weight and lattice constant of Sn are larger than those of Ge, in this embodiment, the second stress adjustment layer 52 (SiSn) has a greater effect on the channel than the first stress adjustment layer 51 (SiGe). The compressive stress in the region is larger, which further realizes higher carrier mobility in the channel, thereby increasing the working current of the device; however, during epitaxial growth, if the atomic lattice mismatch is too large, cracks will occur in the epitaxial layer, forming Excessive defects not only affect the effect of epitaxy, but also cause large defects at the PN junction of the source and drain regions, resulting in increased leakage current of the device. Therefore, the second stress is epitaxially grown in the trench 2 Before the adjustment layer 52 (SiSn), the first stress adjustment layer 51 (SiGe) is epitaxially grown on the substrate (Si), so that the first stress adjustment layer 51 (SiGe) is formed as a stress buffer layer Between the second stress adjustment layer 52 (SiSn) and the substrate 1 (Si), so as to reduce the excessive lattice mismatch between the second stress adjustment layer 52 (SiSn) and the substrate (Si) The defects caused thereby avoid the increase of device leakage current; further, the first stress adjustment layer 51 (SiGe) is limited to a thin layer with a thickness of 2~10nm to ensure that the first stress adjustment layer 51 and the second stress adjustment layer In the composite layer of layer 52, the proportion of the second stress adjustment layer 52 is much larger than the proportion of the first stress adjustment layer 51, so that the composite layer can enhance the compressive stress than the traditional SiGe The effect is more obvious. Then go to step 3).

In step 3), repeat step 2) n times, n is an integer and greater than or equal to 0; when n in step 3) is greater than or equal to 1, the first stress adjustment layer and the first stress adjustment layer grown in the trench 2 are epitaxially grown The second stress adjustment layers are spaced apart from each other to form a sandwich structure; the thickness of the second stress adjustment layer 52 located between the two first stress adjustment layers 51 is 20-30 nm. In the first embodiment, if the n is 0, in the trench 2 , each of the first stress adjustment layer 51 and the second stress adjustment layer 52 is epitaxially grown in one layer. It should be pointed out that, for the specific situation when n is greater than 0, please refer to the second embodiment. Then go to step 4).

In step 4), as shown in FIG. 4 , when the upper surface of the second stress adjustment layer 52 is epitaxially grown on the same plane as the upper surface of the substrate 1 , the first stress adjustment layer 52 filled with The upper surface of the groove 2 of the layer 51 and the second stress adjustment layer 52 epitaxially grows the stress holding layer 53, thereby forming the first stress adjustment layer 51, the second stress adjustment layer 52 and the stress holding layer in the substrate 1. 53 source region 5 and drain region 5 . Wherein, the material of the stress-holding layer 53 is consistent with the material of the first stress-adjusting layer 51 or the second stress-adjusting layer 52, in other words, when the stress-holding layer 53 is epitaxially grown, the gas containing B element can also be introduced at the same time. , to form a stress holding layer 53 doped with B element to reduce the contact resistance of the stress holding layer 53; the thickness of the stress holding layer 53 is 10-20nm.

It should be noted that the present invention uses the stress holding layer 53 to carry out stress holding on the first stress adjustment layer 51 and the second stress adjustment layer 52 epitaxially grown in the source region and the drain region, so as to avoid the stress of the source region and the drain region Polar region stress relief.

In the first embodiment, the material of the stress holding layer 53 is SiGe containing B-doped elements, which is consistent with the material of the first stress adjustment layer 51, and the thickness of the stress holding layer 53 is preferably 15nm.

As shown in Figure 4, the present invention also provides a PMOS transistor, the PMOS transistor at least includes: an active region formed with a channel region, a source region and a drain region, and the source region and the drain region Compressive stress is applied to the channel region, and the source and drain regions are formed on top of the semiconductor substrate 1 .

The source region 5 and the drain region 5 include a stress-holding layer 53 and m groups of sequentially stacked first stress-adjusting layers 51 located under the stress-holding layer 53 and formed on the first stress-adjusting layer 51 The second stress adjustment layer 52, wherein, m is an integer and greater than or equal to 1, and the lattice constants of the substrate 1, the first stress adjustment layer 51 and the second stress adjustment layer 52 increase sequentially, and the stress remains The material of the layer 53 is consistent with the material of the first stress adjustment layer 51 or the second stress adjustment layer 52; when m is greater than or equal to 2, the sandwich formed by the first stress adjustment layer 51 and the second stress adjustment layer 52 spaced apart from each other structure, wherein the lowermost layer of the source region 5 and the drain region 5 is the first stress adjustment layer 51, and the second stress adjustment layer 52 in contact with the stress holding layer 53 is the mth group. At this time, The thickness of the second stress adjustment layer 52 located between the two first stress adjustment layers 51 is 20-30 nm; the material of the substrate 1 is Si, Si _1-x C _x , Si _1-xy Ge _y C _x , wherein, the range of x is 0.01~0.1, and the range of y is 0.1~0.3; the first stress adjustment layer 51 is a SiGe layer; the second stress adjustment layer 52 is a SiSn layer or a SiPb layer; the first stress adjustment layer 52 is a SiSn layer or a SiPb layer; The stress adjustment layer 51 and/or the second stress adjustment layer 52 contains B doping elements, since the material of the stress maintaining layer 53 is consistent with the material of the first stress adjustment layer 51 or the second stress adjustment layer 52, Then the stress maintaining layer 53 may also contain B doping element; the thickness of the first stress adjusting layer is 2-10 nm; the thickness of the stress maintaining layer is 10-20 nm.

It should be noted that the upper surface of the mth group of second stress adjustment layers 52 forms a plane with the upper surface of the substrate 1 , and the stress maintaining layer 53 is located on the plane.

In the first embodiment, as shown in FIG. 4 , in the source region 5 and the drain region 5 , the value of m is 1, in other words, the source region 5 and the drain region 5 include a stress holding layer 53 And a layer of first stress adjustment layer 51 located under the stress maintaining layer 53 and a layer of second stress adjustment layer 52 formed on the first stress adjustment layer 51, and the upper layer of the second stress adjustment layer 52 The surface and the upper surface of the substrate 1 form a plane, and the stress holding layer 53 is located on this plane; the substrate 1 is a bulk silicon substrate, but it is not limited thereto. In another embodiment, when When the substrate material is silicon, the substrate can also be top layer silicon in a semiconductor substrate with an insulating buried layer; the first stress adjustment layer 51 is SiGe, with a preferred thickness of 6nm; Layer 52 is a SiSn layer; the first stress adjustment layer 51 and the second stress adjustment layer 52 contain B doping elements; The material remains the same, at this time, the stress holding layer 53 is SiGe containing B doping elements, and the thickness of the stress holding layer 53 is preferably 15 nm. It should be pointed out that, for the specific situation that the value of m is greater than or equal to 2, please refer to the second embodiment.

A PMOS transistor and a preparation method thereof of the present invention, in order to further improve the compressive stress of the source region and the drain region on the channel in the PMOS transistor, the present invention uses atomic weight and crystallographic Sn element or Pb element, which has a larger lattice constant than Ge element and is in the same group as the substrate, is doped instead of Ge element. Therefore, compressive stress is generated on the channel from the source region and the drain region of the PMOS transistor. From a perspective, compared with the use of pure SiGe as the source and drain regions in the prior art, the present invention uses a second stress adjustment layer with a lattice constant larger than SiGe to form most of the source and drain regions , can provide greater compressive stress for the channel, further realize higher carrier mobility in the channel, and then improve the working current of the device; in addition, the present invention forms a second stress adjustment layer between the second stress adjustment layer and the substrate A stress adjustment layer is used as a stress buffer layer to reduce defects caused by excessive lattice mismatch between the second stress adjustment layer and the substrate; at the same time, the present invention adopts a stress maintaining layer pair in the source region and the drain region The first and second stress adjustment layers grown in the epitaxial layer maintain stress to avoid stress release in the source region and the drain region; further, the source region and the drain region of the present invention also use the first and second layers spaced apart from each other. The sandwich structure composed of the stress adjustment layer further reduces the defects caused by the excessive lattice mismatch between the second stress adjustment layer and the substrate, and at the same time ensures that the source region and the drain of the sandwich structure of the present invention The region can provide a larger compressive stress for the channel than in the prior art.

Embodiment two

The technical solution of embodiment 2 is basically the same as that of embodiment 1, the only difference is that step 2) is repeated n times in step 3) of the preparation method in embodiment 1, and the value of n is 0; the PMOS transistor in embodiment 1 In the source region and the drain region, the value of m of the first stress adjustment layer and the second stress adjustment layer of m groups is 1; in the preparation method of the second embodiment, step 3) is to repeat step 2) n times, the value of n is an integer greater than 0; in the source region and the drain region of the PMOS transistor in the second embodiment, the value of m of the first stress adjustment layer and the second stress adjustment layer of m groups is greater than or equal to 2 , and m is an integer. The similarities between the second embodiment and the first embodiment are not described here one by one, and for the specific description of the similarities, please refer to the first embodiment.

As shown in Figures 5 to 7, the present invention provides a method for preparing a PMOS transistor. The technical solution of the preparation method is basically the same as that in Embodiment 1, wherein the preparation of the source region and drain region in Embodiment 2 For the specific steps in the polar region, please refer to Embodiment 1 for the relevant descriptions of step 1) and step 2), and will not repeat them here. Then go to step 3).

In step 3), repeat step 2) n times, n is an integer and greater than or equal to 0; when n in step 3) is greater than or equal to 1, make the epitaxial growth of the first stress adjustment layer 51 in the trench 2 and the second stress adjustment layer 52 are spaced apart from each other to form a sandwich structure; the thickness of the second stress adjustment layer 52 located between the two first stress adjustment layers 51 is 20-30 nm.

In the second embodiment, as shown in FIG. 5 and FIG. 6, n takes a value of 1, then step 3) is to repeat step 2) once, so that in the trench 2, the first stress adjustment layer 51 and the second stress adjustment layer 52 are epitaxially grown in two layers, and the first stress adjustment layer 51 and the second stress adjustment layer 52 are spaced apart from each other to form a sandwich structure; the thickness of the first stress adjustment layer 5 is 2 to 10 nm, The preferred thickness is 6 nm; the preferred thickness of the second stress adjustment layer 52 located between the two first stress adjustment layers 51 is 25 nm.

It should be pointed out that, in the source region 5 and the drain region 5 of the sandwich structure in the second embodiment, not only the first stress adjustment layer is formed between the second stress adjustment layer 52 (SiSn) and the substrate (Si) 51 (SiGe), and the first stress adjustment layer 51 (SiGe) is also formed between the two second stress adjustment layers 52 (SiSn). The greater the proportion of the second stress adjustment layer 52 and the smaller the proportion of the first stress adjustment layer 51, the better the compressive stress provided, in other words, the source region 5 and the drain region 5 contains only one layer of the first stress adjustment layer 51 and one layer of stress adjustment layer 52 is the best case (as described in Embodiment 1), but because the first stress adjustment layer 51 (SiGe) is limited to 2~ 10nm, very thin, there may still be lattice dislocation (dislocation) defects when the second stress adjustment layer 52 (SiSn) is epitaxially grown, so that the defects in the source region 5 and the drain region 5 will increase, resulting in device leakage. The current increases. Therefore, the sandwich structure is proposed to compromise the effect of increasing the compressive stress of the second stress adjustment layer 52 (SiSn) and the generation of lattice defects. The ultimate purpose of the sandwich structure is still to ensure that in the source region 5 and the drain region 5, compared with the first stress regulation layer 51, the second stress regulation layer 52 occupies most of it, so as to exert its compressive stress increase. Effect.

It should be further pointed out that in the second embodiment, the first stress adjustment layer 52 (SiSn) located between the second stress adjustment layer 52 (SiSn) and the substrate (Si), and the first layer located between two second stress adjustment layers 52 (SiSn) The stress adjustment layer 51 (SiGe) acts as a buffer for transition, and is used to adjust the mismatch of the lattice constant, and further reduce the gap between the second stress adjustment layer 52 and the substrate 1 due to the excessive lattice mismatch. defects; at the same time, the first stress adjustment layer 51 (SiGe) is limited to a thin layer with a thickness of 2~10nm to ensure that in the composite layer of the first stress adjustment layer 51 and the second stress adjustment layer 52, the second The proportion of the stress adjustment layer 52 is much larger than the proportion of the first stress adjustment layer 51, so that the effect of the composite layer in enhancing the compressive stress is more obvious than that of the traditional SiGe alone. Therefore, the sandwich structure of the present invention Compared with the prior art, the source region and the drain region can provide larger compressive stress for the channel.

Then perform the same step 4) as in Embodiment 1. For specific related descriptions, please refer to Embodiment 1 and FIG. 7 .

As shown in FIG. 7 , the present invention also provides a PMOS transistor. In the second embodiment, the technical solution of the PMOS transistor is basically the same as that in the first embodiment, the only difference is that the m group of the second embodiment The value of m of the first stress adjustment layer and the second stress adjustment layer is greater than or equal to 2. For the rest of the same related description, please refer to the specific content of the first embodiment, and will not repeat them here.

When m is greater than or equal to 2, the sandwich structure formed by the first stress adjustment layer 51 and the second stress adjustment layer 52 spaced apart from each other, wherein the bottommost layer of the source region 5 and the drain region 5 is the first stress adjustment layer 51 , the second stress adjustment layer 52 of the mth group is in contact with the stress maintaining layer 53, and at this time, the thickness of the second stress adjustment layer 52 located between the two first stress adjustment layers 51 is 20-30 nm.

In the second embodiment, as shown in FIG. 7, in the source region 5 and the drain region 5, the value of m is 2, in other words, the source region 5 and the drain region 5 include a stress holding layer 53 And the two first stress adjustment layers 51 under the stress maintenance layer 53 and the second stress adjustment layers 52 respectively formed on each of the first stress adjustment layers 51, and the first stress adjustment layers 51 and The sandwich structure formed by the second stress adjustment layer 52; the upper surface of the second group of second stress adjustment layer 52 forms a plane with the upper surface of the substrate 1, and the stress holding layer 53 is located on the plane; the substrate The bottom 1 is a bulk silicon substrate; the first stress adjustment layer 51 is SiGe, with a preferred thickness of 6 nm; the second stress adjustment layer 52 is a SiSn layer, and the second stress adjustment layer 51 between the two first The thickness of the second stress adjustment layer 52 is preferably 25nm; the first stress adjustment layer 51 and the second stress adjustment layer 52 contain B doping elements; the material of the stress holding layer 53 is SiGe, which is the same as the first The material of the stress adjustment layer 51 remains the same, at this time, the stress holding layer 53 is SiGe containing B doping elements, and the thickness of the stress holding layer 53 is preferably 15 nm.

In summary, a PMOS transistor and its preparation method of the present invention, in order to further improve the compressive stress of the source region and the drain region on the channel in the PMOS transistor, the present invention is in the epitaxial growth of the source region and the drain region , use Sn element or Pb element which has larger atomic weight and lattice constant than Ge element and is in the same group as the substrate to replace Ge element for doping. Therefore, from the source region and the drain region of the PMOS transistor to the channel From the perspective of generating compressive stress in the channel, compared with the use of pure SiGe as the source and drain regions in the prior art, the present invention uses a second stress adjustment layer with a lattice constant larger than SiGe to form most of the source region and the drain region, can provide greater compressive stress for the channel, further realize higher carrier mobility in the channel, and then improve the working current of the device; The first stress adjustment layer is formed between them as a stress buffer layer to reduce defects caused by excessive lattice mismatch between the second stress adjustment layer and the substrate; at the same time, the present invention adopts a stress maintenance layer pair in the source The first and second stress adjustment layers epitaxially grown in the region and the drain region maintain stress to avoid stress release in the source region and the drain region; further, the source region and the drain region of the present invention also use the first 1. The sandwich structure formed by the second stress adjustment layer, while further reducing the defects caused by excessive lattice mismatch between the second stress adjustment layer and the substrate, ensures the source of the sandwich structure of the present invention The region and the drain region can provide greater compressive stress to the channel than in the prior art. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.

Claims (14)

1. A preparation method for a PMOS transistor, characterized in that the preparation method at least comprises the following steps: a semiconductor substrate is provided, and the semiconductor substrate top of the prefabricated PMOS transistor is formed to include a source region, a drain region and a trench. The active region of the channel region, and the source region and the drain region exert compressive stress on the channel region; wherein, the specific steps of preparing the source region and the drain region are: 1) forming trenches on the top of the substrate where the source region and the drain region are pre-prepared; 2) In the trench, first epitaxially grow the first stress adjustment layer, and then epitaxially grow the second stress adjustment layer, wherein the lattice constants of the substrate, the first stress adjustment layer and the second stress adjustment layer increase in turn; 3) Repeat step 2) n times, n is an integer and greater than or equal to 0; 4) When the upper surface of the second stress adjustment layer is on the same plane as the upper surface of the substrate, epitaxially grow on the upper surface of the trench filled with the first stress adjustment layer and the second stress adjustment layer A stress-retaining layer, wherein the material of the stress-retaining layer is consistent with the material of the first stress-regulating layer or the second stress-regulating layer. 2. The method for manufacturing a PMOS transistor according to claim 1, characterized in that: when n is greater than or equal to 1 in the step 3), the first stress adjustment layer and the second stress adjustment layer epitaxially grown in the trench The conditioning layers are spaced apart from each other to form a sandwich structure. 3. The method for preparing a PMOS transistor according to any one of claims 1 or 2, characterized in that: in the step 2), when the first stress adjustment layer and/or the second stress adjustment layer are epitaxially grown, the Inject the gas containing B element to form the first stress adjustment layer and/or the second stress adjustment layer doped with B element. 4. The method for manufacturing a PMOS transistor according to claim 1 or 2, characterized in that: the stress holding layer has a thickness of 10-20 nm. 5. The method for manufacturing a PMOS transistor according to claim 1 or 2, characterized in that: the thickness of the first stress adjustment layer is 2-10 nm. 6 . The method for manufacturing a PMOS transistor according to claim 2 , wherein the thickness of the second stress adjustment layer located between the two first stress adjustment layers is 20-30 nm. 7. The preparation method of the PMOS transistor according to claim 1 or 2, characterized in that: the substrate material is any one of Si, Si _1-x C _x or Si _1-xy Ge _y C _x , wherein , the range of x is 0.01-0.1, and the range of y is 0.1-0.3; the first stress adjustment layer is a SiGe layer; the second stress adjustment layer is a SiSn layer or a SiPb layer. 8. A PMOS transistor, characterized in that the PMOS transistor comprises at least: An active region is formed with a channel region, a source region, and a drain region, and the source region and the drain region apply compressive stress to the channel region, the source region and the drain region are formed in a semiconductor substrate top; The source region and the drain region include a stress-holding layer and m groups of first stress-adjusting layers stacked in sequence under the stress-holding layer and a second stress-adjusting layer formed on the first stress-adjusting layer, Wherein, m is an integer greater than or equal to 1, and the lattice constants of the substrate, the first stress adjustment layer, and the second stress adjustment layer increase sequentially, and the material of the stress holding layer is consistent with the first stress The material of the adjustment layer or the second stress adjustment layer is the same. 9 . The PMOS transistor according to claim 8 , wherein when m is greater than or equal to 2, the first stress adjustment layer and the second stress adjustment layer are separated from each other to form a sandwich structure. 10. The PMOS transistor according to claim 8 or 9, characterized in that: the first stress adjustment layer and/or the second stress adjustment layer contains a B doping element. 11. The PMOS transistor according to claim 8 or 9, characterized in that: the stress holding layer has a thickness of 10-20 nm. 12. The PMOS transistor according to claim 8 or 9, characterized in that: the thickness of the first stress adjustment layer is 2-10 nm. 13 . The PMOS transistor according to claim 9 , wherein the thickness of the second stress adjustment layer located between the two first stress adjustment layers is 20-30 nm. 14. The PMOS transistor according to claim 8 or 9, characterized in that: the substrate material is any one of Si, Si _1-x C _x or Si _1-xy Ge _y C _x , wherein x is The range is 0.01-0.1, and the range of y is 0.1-0.3; the first stress adjustment layer is a SiGe layer; the second stress adjustment layer is a SiSn layer or a SiPb layer.