CN103928290B - The lithographic method of crystal round fringes - Google Patents
The lithographic method of crystal round fringes Download PDFInfo
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- CN103928290B CN103928290B CN201310011495.3A CN201310011495A CN103928290B CN 103928290 B CN103928290 B CN 103928290B CN 201310011495 A CN201310011495 A CN 201310011495A CN 103928290 B CN103928290 B CN 103928290B
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- 239000013078 crystal Substances 0.000 title claims abstract description 47
- 238000000034 method Methods 0.000 title claims abstract description 46
- 238000005530 etching Methods 0.000 claims abstract description 40
- 230000003647 oxidation Effects 0.000 claims abstract description 14
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 14
- 239000007789 gas Substances 0.000 claims description 28
- 230000007717 exclusion Effects 0.000 claims description 19
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 13
- 239000001301 oxygen Substances 0.000 claims description 13
- 229910052760 oxygen Inorganic materials 0.000 claims description 13
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 8
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 claims description 8
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 8
- 238000006243 chemical reaction Methods 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- 229910052786 argon Inorganic materials 0.000 claims description 4
- 239000001569 carbon dioxide Substances 0.000 claims description 4
- 229910002092 carbon dioxide Inorganic materials 0.000 claims description 4
- 239000001307 helium Substances 0.000 claims description 4
- 229910052734 helium Inorganic materials 0.000 claims description 4
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 4
- 239000002253 acid Substances 0.000 claims description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 2
- 229910052799 carbon Inorganic materials 0.000 claims 1
- 239000004568 cement Substances 0.000 claims 1
- 239000002131 composite material Substances 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 238000002955 isolation Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000003701 mechanical milling Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000004990 Smectic liquid crystal Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229940095676 wafer product Drugs 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02021—Edge treatment, chamfering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02019—Chemical etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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Abstract
A kind of lithographic method of crystal round fringes, including: wafer is provided, described wafer includes device region and is positioned at the external zones at device region edge, described external zones includes first area and second area, described first area is between device region and second area, and the upper surface of second area is higher than the upper surface of first area；The upper surface of first area and second area being carried out oxidation processes, forms oxide layer, the oxidated layer thickness on described second area is more than the oxidated layer thickness on first area；Remove the oxide layer on first area and the oxide layer of second area upper part thickness；Remaining oxide layer and external zones on etching second area, make the upper surface of first area and the upper surface flush of second area.The lithographic method of crystal round fringes of the present invention improves the flatness of crystal round fringes.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to the lithographic method of a kind of crystal round fringes.
Background technology
Semiconductor wafer is usually to be prepared by single crystal rod (such as silicon ingot), and described single crystal rod is trimmed and grinds
Wear into have one or more for wafer in down-stream the plane of appropriate orientation or recess, then will
Described single crystal rod is cut into single wafer.Generally circular in shape due to wafer, therefore it is also called " wafer ".
In semiconductor fabrication process, wafer is as making classes of semiconductors device (such as MOS device)
Substrate.Multiple semiconductor device can be made on wafer, and in order to cost-effective, generally on wafer
Make identical semiconductor device.Before wafer makes semiconductor device, if first being formed on wafer
Dry isolated groove, forms fleet plough groove isolation structure by fill oxide in isolated groove, defines
The active area (Active Areas is called for short AA) of each semiconductor device.
In existing technique, wafer is formed isolated groove and comprises the steps: first, reference Fig. 1,
Wafer 100 surface is formed and is formed on stop-layer 102, and the part stop-layer 102 on wafer 100 upper surface
Mask layer 104；Then, with continued reference to Fig. 1, mask layer 104 forms etched features 106, described quarter
The position of corrosion figure shape 106 is corresponding with the position of isolated groove to be formed and shape with shape；Then, ginseng
Examine Fig. 2, with mask layer 104 described in Fig. 1 as mask, along etched features 106 etch described mask layer 104,
Stop-layer 102 and wafer 100, form some isolated grooves 108, and remove remaining mask layer 104.
Relatively low owing to being formed at the yield rate of semiconductor device near wafer frontside edge, generally, by wafer 100
Being divided into device region and being positioned at device region edge along wafer 100 radial direction width is the periphery of 5mm to 15mm
District, only forms semiconductor device in device region.Accordingly, before forming semiconductor device, only exist
Form mask layer 104 above device region, and in device region, form isolated groove 108 by etching technics.
Owing to external zones is not used in formation semiconductor device, above external zones, does not form mask layer 104, carving
While erosion forms isolated groove 108, the stop-layer 102 on etching external zones and external zones.But,
When etching forms isolated groove 108, the closer to wafer frontside edge, etching gas plasma density is the lowest,
Etching technics is the least to the etch rate of wafer 100.That is, etching technics is to outside wafer frontside edge
The etch rate enclosing district is less than the etch rate to the external zones near device region, is formed at isolated groove 108
Afterwards, remaining external zones to crystal round fringes thickness-tapered, forms silicon at external zones oblique from device region edge
Face (bevel), the poor flatness of wafer frontside edge, subsequent technique is impacted, Jin Erying
Ring the yield rate being formed at wafer 100 semiconductor-on-insulator device.
In order to improve the flatness of crystal round fringes, improve the yield rate being formed at wafer semiconductor-on-insulator device,
Existing technology utilization bevel etcher (bevel etcher) carries out plasma cleans to the silicon inclined-plane of crystal round fringes.
Concrete, by bevel etcher better-than-average gas ions exclusion region (Process Exclusion Zone,
Referred to as PEZ) model of crystal round fringes of ring and lower plasma exclusion zone ring control plasma cleaning
Enclose, be plasma by radio-frequency power supply by the exciting gas in cleaning procedure, remove the silicon of crystal round fringes
Inclined-plane.
But, removed the poor effect on crystal round fringes silicon inclined-plane by bevel etcher, putting down of crystal round fringes
Whole degree is poor.
The lithographic method on more crystal round fringes silicon inclined-planes refer to the China of Publication No. CN1779924A specially
Profit application.
Summary of the invention
The problem that the present invention solves is to provide the lithographic method of a kind of crystal round fringes, improves the flat of crystal round fringes
Whole degree, and then improve the yield rate being formed at wafer semiconductor-on-insulator device.
For solving the problems referred to above, the invention provides the lithographic method of a kind of crystal round fringes, including:
Thering is provided wafer, described wafer includes device region and is positioned at the external zones at device region edge, described periphery
District includes first area and second area, described first area between device region and second area, and
The upper surface of second area is higher than the upper surface of first area；
The upper surface of first area and second area is carried out oxidation processes, forms oxide layer, described second
Oxidated layer thickness on region is more than the oxidated layer thickness on first area；
Remove the oxide layer on first area and the oxide layer of second area upper part thickness；
Remaining oxide layer and external zones on etching second area, make the upper surface and second of first area
The upper surface flush in region.
Compared with prior art, technical solution of the present invention has the advantage that
Second area upper surface in external zones is higher than to the wafer of first area upper surface, first in the firstth district
Form oxide layer on the upper surface of territory and second area, and make oxidated layer thickness on second area more than the
Oxidated layer thickness on one region, then remove the oxide layer on first area and second area upper part thickness
The oxide layer of degree, then remaining oxide layer and external zones on etching second area, make first area
Upper surface and the upper surface flush of second area.Owing to the oxidated layer thickness on second area is more than the firstth district
The oxidated layer thickness in territory, when removing the oxide layer on first area completely, it is possible to ensures second area
The most oxidized layer of upper surface covers；When etching remaining oxide layer and external zones on second area, by
In etching technics, the etch rate of oxide layer is much smaller than the etch rate to external zones, second can removed
On region during remaining oxide layer, increase the thickness difference of first area and second area, on the second region
After oxide layer is completely removed, due to second area than first area closer to crystal round fringes, second area
Around plasma density is higher, and the etch rate of second area is more than first area by etching technics
Etch rate, can make gradually upper with second area of the upper surface of first area in wafer by etching technics
Surface flushes, and improves the flatness of crystal round fringes, and final raising is formed at the one-tenth of semiconductor device in wafer
Product rate.
Further, when etching remaining oxide layer and external zones on second area in bevel etcher,
The temperature of bevel etcher better-than-average gas ions exclusion region ring more than by plasma exclusion region ring and
The temperature in annular reaction chamber that lower plasma exclusion zone ring is constituted, make etching technics near first-class from
The etch rate of the first area of daughter exclusion region ring increases, and then makes etching technics to first area
Etch rate is close with to the etch rate of second area, progressively reduces the thickness of first area and second area
It is poor to spend, and makes the upper surface of first area and the upper surface flush of second area eventually through etching technics, carries
The flatness of high crystal round fringes.
Accompanying drawing explanation
Fig. 1 ~ Fig. 2 is the schematic diagram that existing technique forms isolated groove on wafer；
Fig. 3 ~ Fig. 8 is the schematic diagram of one embodiment of lithographic method of crystal round fringes of the present invention.
Detailed description of the invention
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The detailed description of the invention of the present invention is described in detail.
Elaborate a lot of detail in the following description so that fully understanding the present invention, but this
Bright other can also be used to be different from alternate manner described here implement, therefore the present invention is not by following
The restriction of disclosed specific embodiment.
The most as described in the background section, after forming isolated groove on wafer, remaining external zones is from device
Part area edge is incremented by crystal round fringes thickness, on external zones formation silicon inclined-plane, and the poor flatness of crystal round fringes,
Have impact on and be formed at the yield rate of semiconductor device in wafer.And existing remove wafer by bevel etcher
The poor effect of bezel.
Inventor through research find, existing by bevel etcher remove crystal round fringes silicon beveling effect not
Good caused by following reason: when crystal round fringes being carried out plasma cleans by bevel etcher, more lean on
Smectic rounded edge, the density of etching plasma is the biggest, the biggest to the etch rate of wafer, i.e. etches work
The etch rate of external zones is successively decreased to device region edge by skill by crystal round fringes, is easily caused crystal round fringes
Overetch, after making etching, the thickness of crystal round fringes is less than the thickness of other parts in external zones, is changing
The flatness aspect effect of kind crystal round fringes is limited.
For drawbacks described above, the invention provides the lithographic method of a kind of crystal round fringes, in external zones
Second area upper surface higher than the wafer of first area upper surface, first upper to first area and second area
Surface carries out oxidation processes, forms oxide layer, and makes the oxidated layer thickness on second area more than the firstth district
Oxidated layer thickness on territory；Uniformly etch described oxide layer again, in the oxidation removed completely on first area
During layer, it is ensured that the most oxidized layer of second area covers；Then etching second area on remaining oxide layer with
And external zones, owing to etching technics is much smaller than the etch rate to external zones to the etch rate of oxide layer,
The thickness difference of first area and second area when removing remaining oxide layer on second area, can be increased,
After oxide layer is completely removed on the second region, due to second area than first area closer to wafer limit
Edge, around second area, plasma density is higher, and the etch rate of second area is more than by etching technics
Etch rate to first area, can by etching technics make in wafer the upper surface of first area gradually with
The upper surface flush of second area, improves the flatness of crystal round fringes, and final raising is formed in wafer half
The yield rate of conductor device.
It is described in detail below in conjunction with the accompanying drawings.
With reference to Fig. 3 ~ Fig. 8, by being formed with the etching of crystal round fringes of isolated groove to wafer of the present invention
The lithographic method at edge is described further.
With reference to Fig. 3, it is provided that wafer 20, described wafer 20 includes device region 202 and is positioned at device region 202
The external zones at edge, described external zones includes first area 204a and second area 206a, described firstth district
Territory 204a is between device region 202 and second area 206a, and the upper surface of second area 206a is high
Upper surface in first area 204a.
In the present embodiment, the material of described wafer 20 is silicon.Described device region 202 is as forming quasiconductor
The substrate of device.Described external zones width along wafer 20 radial direction can be according to concrete processing technology
Being adjusted, the present invention is without limitation.
In the present embodiment, the upper surface of described first area 204a is inclined-plane, described second area 206a
Upper surface be horizontal plane, the upper surface of second area 206a is higher than the upper surface of first area 204a.
In another embodiment, described external zones upper surface is inclined-plane, by first area 204a near device
Part district 202 1 lateral edges to second area 206a away from the external zones thickness of first area 204a mono-lateral edges
It is incremented by.
In yet another embodiment, the upper surface of described external zones can be also stepped, and second area 206a
Upper surface higher than the upper surface of first area 204a, but the invention is not restricted to this.
With reference to Fig. 4, for wafer in Fig. 3 20 along the sectional view in AA direction.Device region 202 is formed
Isolated groove 210, follow-up by the formation fleet plough groove isolation structure of fill oxide in isolated groove 210
(not shown), is formed at the active area of semiconductor device in device region 202 to define.
In the present embodiment, in forming Fig. 4 before isolated groove 210, also in described wafer 20 surface shape
Become stop-layer 208, as the stop in chemical mechanical milling tech when being subsequently formed fleet plough groove isolation structure
Layer, it is to avoid wafer 20 is caused damage by chemical mechanical milling tech.The material of described stop-layer 208 can be
Silicon nitride.
Form isolated groove 210 in Fig. 4, and formed in isolated groove fleet plough groove isolation structure can include as
Lower step:
Wafer 20 is provided；
Form the stop-layer 208 covering wafer 20 surface；
Device region 202 upper surface is formed mask layer (not shown), described mask layer is formed with etching
Figure, the shape of described etched features and position and shape and the position pair being subsequently formed isolated groove 210
Should；
With described mask layer as mask, the stop-layer 208 in etched features etched features district 202 and device
Part district 202, forms isolated groove 210；
Oxidation is formed in described isolated groove 210 and on the stop-layer 208 of isolated groove 210 both sides
Thing (not shown)；
Described oxide is planarized, to the stopping exposed on device region 202 by chemical mechanical milling tech
Layer 208, forms fleet plough groove isolation structure (not shown).
It should be noted that owing to not depositing on the upper surface of first area 204a and second area 206a
Mask layer, while forming isolated groove 210, is also consumed by first area 204a and second area 206a
On stop-layer 208 and the first area 204a and second area 206a of segment thickness.
Also, it should be noted owing to first area 204a and second area 206a is near wafer 20 edge,
And when etching forms isolated groove 210, the closer to wafer 20 edge, etching gas plasma close
Spend the lowest, cause etching technics that the etch rate of first area 204a is more than the quarter to second area 206a
Erosion speed.After isolated groove 210 is formed, the upper surface of second area 206a is higher than first area 204a
Upper surface, remaining external zones from device region 202 edge to wafer 20 edge thickness be incremented by, in periphery
District forms silicon inclined-plane.
With reference to Fig. 5, the upper surface of first area 204a and second area 206a in Fig. 4 is carried out at oxidation
Reason, forms oxide layer 212a.
The upper surface of first area 204a and second area 206a is carried out oxidation treatment method is oxygenous
Bulk plasmon processes.Described oxygen-containing gas be oxygen or oxygen with in carbon dioxide, argon and helium
One or several mixed gas.
It is also preferred that the left described oxygen-containing gas is oxygen and the one in carbon dioxide, argon and helium or several
The mixed gas planted, carbon dioxide, argon and/or helium in mixed gas can improve oxidation processes
Speed, and improve the uniformity of formed oxide layer.
Concrete, upper table to first area 204a in Fig. 4 and second area 206a in bevel etcher
Face carries out oxidation processes, with by bevel etcher better-than-average gas ions exclusion region ring and lower plasma
Wafer 20 surface carrying out oxidation processes is defined by the annular reaction chamber that exclusion region ring is constituted, and only exists
Oxide layer 212a is formed on the upper surface of first area 204a and second area 206a.Owing to inclined-plane etches
Concrete structure and the using method of machine are well known to those skilled in the art, do not repeat them here.
When the upper surface of first area 204a and second area 206a is carried out oxidation processes, due to
Around two region 206a, the density of oxygen-containing gas plasma is more than oxygen-containing gas around the 204a of first area etc.
The density of gas ions, is formed at the thickness of oxide layer 212a on second area 206b more than being formed at the
The thickness of oxide layer 212a on one region 204b.
With reference to Fig. 6, remove in Fig. 5 in bevel etcher and be positioned at oxide layer 212a on the 204b of first area
And it is positioned at oxide layer 212a of second area 206b upper part thickness, second area 206b remains
Oxide layer 212b of segment thickness.
In the present embodiment, remove and be positioned at oxide layer 212a on the 204b of first area and be positioned at the secondth district
The method of oxide layer 212a of territory 206b upper part thickness is wet etching.The solution of described wet etching
For hydrofluoric acid solution, in hydrofluoric acid solution, Fluohydric acid. is 1:100 ~ 1:2000 with the volume ratio of water.
Owing to wet-etching technology is to the removal rate of oxide layer 212a on the 204b of first area and to second
On the 206b of region, the removal rate of oxide layer 212a is equal, and oxide layer 212a on second area 206b
Thickness more than the thickness of oxide layer 212a on the 204b of first area, removing first area 204b completely
On oxide layer 212a time, second area 206b there remains oxide layer 212b of segment thickness.
In another embodiment, other etching sides that oxide layer 212a uniformly can be etched can also be used
Method is removed oxide layer 212a on the 204b of first area and is positioned at second area 206b upper part thickness
Oxide layer 212a.
With reference to Fig. 7 and Fig. 8, in bevel etcher, etch in Fig. 6 remaining oxygen on second area 206b
Change layer 212b and external zones, make in Fig. 8 the upper surface of first area 204d with second area 206c's
Upper surface flush.
In the present embodiment, remaining oxide layer 212b and periphery on second area 206b in etching Fig. 6
The gas in district is fluoro-gas, such as CF4、C2F6And SF6In one or several.
Before oxide layer 212b on second area 206b is completely removed, owing to fluoro-gas is to oxygen
The etch rate changing layer 212b is less than the etch rate to the first area 204b that material is silicon, can go
During oxide layer 212b on second area 206b, the thickness of removal first area 204b is made to be more than
Remove the thickness of removing oxide layer 212b.With reference to Fig. 7, after oxide layer 212b is completely removed in figure 6,
First area 204c upper surface increases with the thickness difference of second area 206b upper surface.
After oxide layer 212b on second area 206b is completely removed, due to second area 206b ratio
First area 204c is closer to wafer 20 edge, and around second area 206b, etching gas plasma is close
Du Genggao, the etch rate of second area 206b in Fig. 7 is more than first area 204c by etching technics
Etch rate, but due to the thickness difference of first area 204c upper surface Yu second area 206b upper surface
Relatively big, first area 204d upper surface and second area 206c upper surface flush can be made by etching technics,
Improve the flatness at wafer 20 edge, and then improve the yield rate being formed at semiconductor device.
In the present embodiment, in bevel etcher, etch in Fig. 6 remaining oxide layer on second area 206b
When 212b and external zones, the temperature of bevel etcher better-than-average gas ions exclusion region ring is 0 DEG C ~ 150
DEG C, the temperature of bevel etcher better-than-average gas ions exclusion region ring is more than by plasma exclusion region
The temperature in the annular reaction chamber that ring and lower plasma exclusion zone ring are constituted.
Owing to the temperature of bevel etcher better-than-average gas ions exclusion region ring is more than the temperature of reaction chamber, make
The etch rate of the first area 204b near plasma exclusion region ring is increased by etching technics, enters
And make etching technics to the etch rate of first area 204b near plasma exclusion region ring with right
First area 204b and the etch rate of second area 206b away from plasma exclusion region ring
Close, the upper surface of first area 204d and the upper table of second area 206c is made eventually through etching technics
Face flushes, and improves the flatness at wafer 20 edge.
Although the present invention is open as above with preferred embodiment, but it is not for limiting the present invention, appoints
What those skilled in the art without departing from the spirit and scope of the present invention, may be by the disclosure above
Technical solution of the present invention is made possible variation and amendment by method and technology contents, therefore, every does not takes off
From the content of technical solution of the present invention, it is any that above example is made by the technical spirit of the foundation present invention
Simple modification, equivalent variations and modification, belong to the protection domain of technical solution of the present invention.
Claims (12)
1. the lithographic method of a crystal round fringes, it is characterised in that including:
Thering is provided wafer, described wafer includes device region and is positioned at the external zones at device region edge, described periphery
District includes first area and second area, described first area between device region and second area, and
The upper surface of second area is higher than the upper surface of first area；
The upper surface of first area and second area is carried out oxidation processes, forms oxide layer, described second
Oxidated layer thickness on region is more than the oxidated layer thickness on first area；
Remove the oxide layer on first area and the oxide layer of second area upper part thickness；
Remaining oxide layer and external zones on etching second area, make the upper surface and second of first area
The upper surface flush in region.
2. the lithographic method of crystal round fringes as claimed in claim 1, it is characterised in that to first area and the
The upper surface in two regions is carried out on oxidation processes, the oxide layer removed on first area and second area
The oxide layer of segment thickness is carried out in bevel etcher.
3. the lithographic method of crystal round fringes as claimed in claim 1, it is characterised in that to first area and the
It is oxygen-containing gas Cement Composite Treated by Plasma that the upper surface in two regions carries out the method for oxidation processes.
4. the lithographic method of crystal round fringes as claimed in claim 3, it is characterised in that described oxygen-containing gas is
Oxygen or oxygen and the mixed gas of one or more in carbon dioxide, helium and argon.
5. the lithographic method of crystal round fringes as claimed in claim 1, it is characterised in that remove on first area
Oxide layer and the method for oxide layer of second area upper part thickness be wet etching.
6. the lithographic method of crystal round fringes as claimed in claim 5, it is characterised in that described wet etching
Solution is hydrofluoric acid solution.
7. the lithographic method of crystal round fringes as claimed in claim 6, it is characterised in that described hydrofluoric acid solution
Middle Fluohydric acid. is 1:100～1:2000 with the volume ratio of water.
8. the lithographic method of crystal round fringes as claimed in claim 1, it is characterised in that on etching second area
Remaining oxide layer and external zones are carried out in bevel etcher.
9. the lithographic method of crystal round fringes as claimed in claim 8, it is characterised in that on etching second area
When remaining oxide layer and external zones, the temperature of bevel etcher better-than-average gas ions exclusion region ring
Being 0 DEG C～150 DEG C, in bevel etcher, the temperature of reaction chamber is less than plasma exclusion region ring
Temperature.
10. the lithographic method of crystal round fringes as claimed in claim 8, it is characterised in that on etching second area
The gas of remaining oxide layer and external zones is fluoro-gas.
The lithographic method of 11. crystal round fringes as claimed in claim 10, it is characterised in that described fluoro-gas is
CF4、C2F6And SF6In one or several.
The lithographic method of 12. crystal round fringes as claimed in claim 1, it is characterised in that table on described external zones
Face is inclined-plane, by first area near device region one lateral edges to second area away from side, first area
The external zones thickness at edge is incremented by.
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| CN108666203B (en) * | 2017-04-01 | 2020-11-27 | 中芯国际集成电路制造(上海)有限公司 | Method for improving edge appearance of wafer |
| CN109273358A (en) * | 2018-08-31 | 2019-01-25 | 上海华力集成电路制造有限公司 | The side wall lithographic method of wafer |
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