CN103926807B - A kind of silicon slice alignment method - Google Patents
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Abstract
The open a kind of silicon slice alignment method of the present invention, including: position on silicon chip of step 1, input fine alignment coordinate points and the coordinate up and down of fine alignment flow process work stage motion；Step 2, using the distance between the upper station of fine alignment flow process and next station as the constraint function of zero distance, or will first find the nearest-neighbors point between a upper station of fine alignment flow process and next station, and they are connected with each other as constraint function, then use travelling salesman's algorithm optimization, increase by a penalty when meeting constraints as weight；Step 3, searching algorithm is utilized to carry out problem solving；Step 4, output solving result.
Description
Technical Field
The invention relates to the field of integrated circuit equipment manufacturing, in particular to a silicon wafer alignment method for photoetching equipment.
Background
In the field of lithography machines, the yield Throughout of the whole machine is one of three core indexes of the lithography machine, and in order to improve the yield, each lithography machine manufacturer tries to dig the potential continuously, a double-workpiece-table system is invented in the prior art, wherein 16 alignment marks on a silicon wafer are precisely aligned at a measurement position of the whole machine so as to improve the alignment precision.
In the field of super-large integrated circuit manufacturing, in order to solve the Problem of path optimization of complex multi-point punching, for example, in US7054798, a Traveling Sales Problem algorithm (TSP) is combined to perform approximate calculation on a single in-plane punching path to obtain a shortest processing path, thereby improving the processing efficiency.
The research on the problem can be divided into three influencing factors, wherein the first is system track and scheme planning; secondly, the motion performance of the workpiece table; third is alignment strategy and cell technique. And analyzing by combining a basic movement time formula T = S/V, wherein T is the time required by movement, S is the movement distance required to be reached, and V is the movement speed. The work flow T combining specific stations and processes can be divided into two types, T1 is the time required for moving between two stations, and T2 is the time required for working at a certain station. I.e. T = T1+ T2.
One of the influencing factors is system trajectory and scheme planning, i.e. which scheme and method are adopted to realize the alignment of a plurality of marking points on the silicon chip, and the sequence and motion trajectory of the marking points. The time consumed in moving between any two points in the system trajectory planning belongs to T1, which is the time required for moving between two stations.
The second factor is the motion performance of the workpiece table. For background information on workpiece stage motion performance, reference is made to the paper, authors: munhua et al, ultra-precise point-to-point motion three-order trajectory planning precision control, journal of mechanical engineering, Vol. 44(1), 2008, pp.127-132. generally, a workpiece stage motion model is planned to be a three-order or four-order model for simulation. As shown in fig. 1, fig. 1 is a conceptual diagram of a motion model of a stage in a lithography machine. Table one shows a typical stage motion performance parameter.
Watch 1
For the motion with the distance between two points being relatively close (10 mm-100 mm), according to the motion model and rule of the workpiece table, the acceleration and deceleration between the short distances is usually not enough to increase the velocity of the workpiece table to a larger motion velocity, and the maximum velocity of the workpiece table is usually only increased to 200 mm/s to 400mm/s in the distance segment, as shown in table 1. That is, in this stroke, the workpiece stage is actually in a working state with a low movement speed, although the workpiece stage has the capability of reaching a large stepping speed (more than 1000 mm/s). In this context, it is to be noted that for short-distance workpiece stage stepping movement, during the exposure and measurement of the lithography machine, the micro-stage of the workpiece stage is frequently in the process of acceleration start and deceleration stop, and the actual movement speed of the workpiece stage is not high for most of the time. The workpiece table model with the above performance is decomposed and calculated, and an approximate model and a curve of the movement distance corresponding to the movement time in the following stepping mode can be obtained, as shown in fig. 2.
The third influencing factor is the alignment strategy and cell technology. There are usually multiple movement modes of the silicon wafer alignment mark, such as a video capture mark, as shown in fig. 3, scanning in the X direction and then scanning in the Y direction; or first scanning in the Y direction and then scanning in the X direction. As shown in fig. 4, such as an aerial image imaging marker, or scanning the alignment marker along a 45 degree angle. Because the actual size of the alignment mark is extremely small, generally between 400 micrometers and 500 micrometers, and the proportion of the actual size of the alignment mark is less than 1% compared with the physical distance between marks, the difference caused by the difference of the mark alignment unit technology and the movement mode can be ignored in the actual engineering.
And because the moving speed is lower, generally 3mm/s to 30mm/s, and the speed is lower compared with the average speed (400 mm/s to 600 mm/s) of the workpiece stage movement, and is only 4% -5%, in model simplification and engineering calculation, we can assume that the workpiece stage is static during alignment and carry out unit alignment of the alignment mark points. The time spent technically on the alignment unit is T2, the time required to work at a certain workstation.
A silicon wafer fine alignment process and an algorithm used in the prior art are shown in fig. 5, and the alignment method specifically includes: the silicon chip fine alignment effectively shortens the alignment scanning path of the interferometer and improves the alignment precision by adopting a simple bending algorithm (simple means alignment algorithm) according to the existing n silicon chip fine alignment marks on the silicon chip. The algorithm approximately equally divides all the silicon chip fine alignment marks into m groups along the increasing sequence of the y direction, the scanning paths with even numbers increase the sequence along the x direction, and the odd numbers are opposite. And then connecting the scanning paths according to the group numbers from small to large. Thus, a scanning alignment path of the silicon wafer fine alignment mark is planned.
The detailed scanning path planning process of the traditional silicon wafer fine alignment path calculation method can be divided into the following steps:
step 1, dividing the alignment marks into A1, A2 and … An sets according to the y direction:
a) setting the number of sets to be 0 (the sets do not contain any silicon chip alignment mark);
b) selecting the position (xj, yj) which is not in the set and has the minimum y value in all the silicon chip alignment marks;
c) selecting yk-yj < y _ tolerance in all marks (xk, yk), wherein the range of the y _ tolerance is initially determined to be more than 0 and less than or equal to 100 (mm);
d) setting the selected flag to the new set Ai;
e) repeating the steps b, c and d until all the alignment marks on the silicon wafer are selected.
And 2, arranging the marks in each set Ai in the positive direction of x: ai are arranged from small to large in sequence, and if i is an odd number, the marks in Ai are arranged in a reverse direction.
Aiming at specific problems, the total distance of the simple bending algorithm of the prior art scheme is more than 1500 mm.
In view of the foregoing, there is a need in the art for a new alignment method that improves alignment efficiency while ensuring alignment accuracy.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention provides a silicon wafer alignment method which can improve the alignment efficiency while ensuring the alignment accuracy.
In order to achieve the above object, the present invention discloses a silicon wafer alignment method, comprising: step 1, inputting the position of a precise alignment coordinate point on a silicon wafer and the upper and lower coordinates of the motion of a precise alignment process workpiece table; step 2, taking the distance between the previous station and the next station of the fine alignment process as a constraint function of zero distance, or firstly finding the nearest neighbor point between the previous station and the next station of the fine alignment process, connecting the nearest neighbor points with each other to be used as the constraint function, then optimizing by adopting a traveling quotient algorithm, and adding a penalty function as weight when the constraint condition is met; step 3, solving the problem by utilizing a search algorithm; and 4, outputting a solving result.
The step 1 specifically comprises: step 1.1, starting from any preparation station p0(x0, y 0) in a silicon wafer exposure process, driving a silicon wafer stage by a motion control unit to drive a silicon wafer to move n alignment marks on the surface of the silicon wafer related to the preparation station one by one to the vertical direction of a mark scanning unit according to the sequence corresponding to positions p1, p2, … … and pn, wherein the n alignment marks are respectively positioned at p1(x1, y1) and p2(x2, y2), … … and pn (xn, yn), and the sequence is characterized in that the total stroke formed by connecting the positions of the marks traversed by the sequence in a straight line is shortest, namely the coordinates (xi, yi), (xj, yj) of any two points pi and pj in front and back in the traversal sequence meet the shortest total stroke, i = 0-n-1, j = i + 1-n;
step 1.2 the calculation formula is as follows:wherein
Andan X value and a Y value representing the position of the last coordinate of the last working position;andan X value and a Y value representing a position coordinate of a next working first coordinate; the last working position is a position for adjusting the silicon wafer field by field, and the next working position is a position for exchanging and waiting two workpiece tables.
In step 2, the constraint function that the distance between the previous station and the next station of the fine alignment process is taken as the zero distance specifically includes: the distance between the last of the fine alignment working positions and the next of the fine alignment working positions is preset to be 0 when calculating; firstly, finding nearest neighbor points between a previous station and a next station of a fine alignment process, and connecting the nearest neighbor points with the next station to be used as a constraint function; firstly, the nearest neighbor of the precisely aligned 16 coordinate points and the coordinate of the last working position is found, then the nearest neighbor of the precisely aligned 16 coordinate points and the coordinate of the next working position is found, and the evaluation function in the step 2 is a Euclidean function or a chessboard function.
When the evaluation function is a euclidean function, the calculation formula is as follows:the total distance is the shortest,andx and Y values representing the position coordinates ps (xs, ys) in the last position; or represents the X value and the Y value of the working position coordinates p1(X1, Y1) to pn (xn, yn) in the middle working position; or the X value and the Y value of the working bit coordinate pe (xe, ye) in the next working bit, and the middle working bit is the silicon wafer fine alignment working bit.
When the evaluation function is a chessboard function, the calculation formula is as follows:the total distance is the shortest,andx and Y values representing the position coordinates ps (xs, ys) in the last position; or represents the X value and the Y value of the intermediate working position coordinates p1(X1, Y1) to pn (xn, yn); the middle working position is a silicon wafer fine alignment working position.
The search algorithm used in step 3 is one of the following algorithms: greedy algorithm, two-pair exchange, three-pair exchange, heuristic algorithm, simulated annealing, ant-cave algorithm, or genetic algorithm.
The angle of the scan in this step 1.1 is in the X-direction or Y-direction or 45 degree angle direction.
Compared with the prior art, the technical scheme has the advantages that: firstly, the alignment precision of the whole machine is ensured, and the alignment mark points of 16 silicon wafers are aligned in sequence. Secondly, improve accurate alignment efficiency simultaneously, and then improve complete machine efficiency. Thirdly, the efficiency of the fine alignment link is improved by 5 to 25 percent, and the efficiency of the whole machine is improved by + 2 chips/hour. Fourthly, the movement path of the workpiece table is shortened, the loss of the workpiece table is reduced, and the service life of the whole machine is prolonged. Fifth, compatible ATHENA and SMASH alignment sensors. Sixth, compatible precision alignment involves X-direction and Y-direction scanning, and is compatible with 45 degree angle scanning alignment marks.
Drawings
The advantages and spirit of the present invention can be further understood by the following detailed description of the invention and the accompanying drawings.
FIG. 1 is a conceptual diagram of a motion model of a workpiece stage in a lithography machine;
FIG. 2 is an approximate model and curve of motion distance versus motion time in a motion model of a workpiece table;
FIG. 3 is a schematic diagram of an X-direction and then Y-direction scanning mark arrangement during alignment;
FIG. 4 is a schematic view of a scheme for scanning the mark in a 45 degree direction during alignment;
FIG. 5 is a graph of an alignment path under a simple warping algorithm used in the prior art;
FIG. 6 is a system diagram of the whole architecture of the lithography machine;
FIG. 7 is a flow chart of the dual stage lithography machine operation;
FIG. 8 is an algorithmic flow diagram of a first embodiment shown in the present disclosure;
FIG. 9 is an alignment path diagram of the wait bit in the X forward direction in the first embodiment;
FIG. 10 is a diagram of the alignment path of the wait bit in the negative X direction in the first embodiment;
FIG. 11 is an algorithmic flow diagram illustrating a second embodiment of the present invention;
FIG. 12 is an alignment path diagram of the wait bit in the X forward direction in the second embodiment;
fig. 13 is a diagram of an alignment path of the wait bit in the negative X direction in the second embodiment.
Detailed Description
Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
To better illustrate the present solution, the following definitions will be made to aid in understanding the present solution.
Silicon Wafer Alignment apparatus (Wafer Alignment, WA): the silicon wafer alignment device has the function of completing the horizontal position alignment of the silicon wafer and the mask. The radiation beam B is incident on the patterning device (e.g., mask) MA, which is held on the support structure (e.g., mask table) MT, and is patterned by the patterning device. Having traversed the patterning device (e.g., mask) MA, the radiation beam B passes through the projection system PS, which focuses the radiation beam onto a target portion C of the substrate w. With the aid of the second positioner PW and position sensor IF (e.g. an interferometric device, linear encoder or capacitive sensor), the substrate table WT can be moved accurately, e.g. so as to position different target portions C in the path of the radiation beam PB. Similarly, the first positioning device PM and another position sensor can be used to accurately position the patterning device MA with respect to the path of the radiation beam PB, e.g. after mechanical retrieval from a mask library, or during a scan. In general, movement of the patterning device support (e.g. mask table) MT may be realized with the aid of a long-stroke module (coarse positioning) and a short-stroke module (fine positioning), which form part of the first positioner PM. Similarly, movement of the substrate table WT or substrate support may be realized using a long-stroke module (coarse positioning) and a short-stroke module (fine positioning), which form part of the second positioner PW. In the case of a stepper (as opposed to a scanner) the support structure MT may be connected to a short-stroke actuator only, or may be fixed. Patterning device MA and substrate Wo may be aligned using patterning device alignment marks M1, M2 and substrate alignment marks P1, P2 although the substrate alignment marks shown occupy dedicated target portions, they may be located at positions between target portions (known as scribe-lane alignment marks). Similarly, in situations in which more than one die is provided to the patterning device (e.g. mask) MA, the patterning device alignment marks may be provided between the dies.
The silicon Wafer moving table (Wafer Stage, WS) is used for carrying a silicon Wafer and moving the silicon Wafer to a designated position (station) for performing corresponding process operations. The lithographic apparatus may be of a type having two (dual stage) or more substrate tables or "substrate supports" (and/or two or more mask tables or "mask supports"). in such "multiple stage" machines, additional tables and/or support structures may be used in parallel, or preparatory steps may be carried out on one or more tables and/or support structures while one or more other tables and/or support structures are being used for exposure.
The technical scheme provides a high-efficiency silicon wafer fine alignment process and a method. The method combines about 16 precisely aligned alignment mark working positions and the last station and the next station of the precise alignment process, and is an optimization thought scheme applied to local processes by global optimization, so that the working track of a workpiece table is shortest, and the motion efficiency and the yield of the whole workpiece table are improved.
FIG. 6 is a system diagram of the overall architecture of a lithography machine, particularly a typical dual stage lithography machine. The lithography machine is schematically illustrated in the present invention, but the present invention is not only applicable to this type of lithography machine. The photoetching machine comprises a photoetching machine silicon wafer exposure system. The silicon wafer exposure system of the photoetching machine comprises: a Wafer Alignment apparatus and system (WA) 300 comprises a Wafer Alignment apparatus for aligning a Wafer mark (on the upper surface of a Wafer) with a TIS plate (on the upper surface of a Wafer micropositioner) to establish a relationship therebetween. The device comprises a workpiece table, wherein the workpiece table 100 consists of a micro-motion table 110 and a coarse-motion table 120. The silicon wafer 4 is placed on top of the workpiece stage micropositioner 110, and the micropositioner 110 can carry the silicon wafer 4 to move. In addition, a measuring system such as a laser Interferometer 210 (IF) or a sensor such as an optical plane grating (Encoder) is included, which can measure the nanometer-scale precision of the micro-stage 110 and the silicon wafer 4.
A dual stage workflow is depicted in fig. 7. The method comprises the following working steps: a. taking the silicon wafer from the silicon wafer table by the wafer discharging manipulator; b. placing the silicon wafer on a silicon wafer table by a wafer loading mechanical handle; d. searching an accurate zero position, and resetting the laser interferometer; e. aligning to establish a coordinate system of the workpiece table; f. globally leveling a silicon wafer; g. the coarse alignment is used for establishing a silicon wafer coordinate system; h. leveling the silicon wafer field by field; i. carrying out fine alignment on the silicon wafer by referring to the alignment mark; j. exchanging the two workpiece tables; k. searching an accurate zero position, and resetting the laser interferometer; performing coaxial alignment; m, local calibration is carried out on the silicon wafer; n, determining an optimal focal plane 1; determining an optimal focal plane 2; p. performing a scanning exposure.
The technical scheme is based on a traveler problem algorithm and adopts two optimization algorithms. The first is a zero-weight algorithm, that is, the distance between the previous station and the next station of the fine alignment process is taken as a constraint function of the zero distance, that is, the upper and lower working stations are firstly connected, and then optimization is performed by adopting a traveler problem algorithm. The second is nearest neighbor algorithm, that is, nearest neighbor points between the previous station and the next station of the fine alignment process are found first and are connected with each other as a constraint function, and then optimization is performed by adopting a traveler problem algorithm.
The silicon wafer fine alignment method comprises the following steps:
1. starting from any preparation station p0(x0, y 0) in the silicon wafer exposure process, driving a silicon wafer platform by a motion control unit to drive a silicon wafer to move n alignment marks of the silicon wafer surface related to the preparation station one by one in the order corresponding to positions p1, p2, … … and pn to positions p1(x1, y1), p2(x2, y2), … … and pn (xn, yn) in the vertical direction of a mark scanning unit, wherein the sequence is characterized in that the total stroke formed by connecting the positions of the marks traversed by the sequence in a straight line is shortest, namely the coordinates (xi, yi) and (xj, yj) of any two points pi and pj in front and back in the traversal sequence meet the shortest total stroke, wherein i = 0-n-1, and j = i + 1-n;
and the calculation formula comprises the following characteristics:
orThe distance is shortest, wherein
Andx and Y values representing the working bit coordinates ps (xs, ys) in the previous working sequence (h. field-by-field leveling of the silicon wafer);andx and Y values representing the work site coordinates p1(X1, Y1) in the next work order (i. fine silicon wafer alignment);
and the calculation formula comprises the following characteristics:
orThe distance is shortest, whereinAndx and Y values representing the work site coordinates pn (xn, yn) in the previous work sequence (i. fine silicon wafer alignment);andthe X and Y values representing the work bit coordinates pe (xe, ye) in the next work order (j. work stage swap waiting).
2. The mark scanning unit scans the corresponding marks one by one according to the sequence and records the spatial characteristics of the related marks until the scanning and the characteristic recording of the nth alignment mark are completed.
3. The alignment signal processing unit determines the number of fitting points of each sine periodic waveform according to the method of fitting the alignment waveform by using the recorded spatial characteristic information of the n alignment marks so as to obtain an ideal fitting waveform. After calculation, silicon wafer alignment deviation correcting data delta x and delta y of the current station are obtained, and the data are transmitted to a motion control unit;
4. the motion control unit converts the delta x and the delta y into a silicon wafer stage driving signal, and drives the silicon wafer stage to bear the silicon wafer and move to a precise alignment position to complete precise alignment.
5. And finally, the motion control unit drives the silicon wafer to the next preparation station pn +1(xn +1, yn + 1) of the silicon wafer exposure process, such as the working coordinate of the exchange position of the motion table.
The first embodiment of the present invention, the zero weight algorithm, will be described below. Fig. 8 is an algorithmic flow chart of the first embodiment shown in the present invention. The method comprises four steps of inputting data S801, setting constraint boundaries S802, solving problems S803 and outputting results S804. The method specifically comprises the following steps:
s801: data is input. The method comprises the steps of in a fine alignment process of a silicon wafer by referring to an alignment mark, finely aligning the positions of coordinate points (such as 16 or 32) on the silicon wafer, moving the silicon wafer to be right below an alignment sensor by a workpiece table, and secondarily aligning the previous coordinate and the next coordinate of the movement of the workpiece table in the fine alignment process. As shown in fig. 7, the last working position is a coordinate point at which h-field leveling is performed on the silicon wafer, and the next working position j-coordinate point at which two workpiece stages exchange waiting positions.
The calculation formula is as follows:wherein
Andh, representing the last working position, carrying out field-by-field leveling on the silicon wafer, and obtaining the position (X value and Y value) of the last coordinate;
andrepresenting j, two workpiece tables exchange waiting positions, namely the position coordinates (X value and Y value) of the first coordinate;
s802: and setting a constraint boundary, wherein the distance between the last coordinate of the fine alignment working position and the next coordinate of the fine alignment working position is zero weight. When the program needs to calculate the distance between the last of the fine alignment work bits and the next of the fine alignment work bits, they have been assumed equal to 0. In the algorithm processing, in order to meet specific constraint conditions, a penalty function is added to control the relationship. The application of the penalty function here is a weighting of the distance in the traveler problem. If the penalty condition is met, applying a penalty value on the distance; if this condition is not met, no penalty value is imposed.
Two alternative schemes are used for the merit function, the first is the euclidean function and the second is the checkerboard function.
The evaluation function one: the physical Distance between two points is calculated using the Euclidean Distance function (Euclidean Distance).
The calculation formula is as follows:the total distance is shortest, whereinAndx and Y values representing one coordinate.
Andx and Y values representing the working bit coordinates ps (xs, ys) in the previous working sequence (h. field-by-field leveling of the silicon wafer);
or represents the X and Y values of the work site coordinates p1(X1, Y1) to pn (xn, yn) in the intermediate work sequence (i. fine alignment of silicon wafer);
or the X and Y values representing the work bit coordinates pe (xe, ye) in the next work order (j. work stage swap waiting).
And (3) evaluating a function II: and (3) calculating the maximum value of the Distance between the X point and the Y point as an evaluation function by adopting a Chessboard Distance function (Chessboard Distance) according to the characteristic that the long strokes of the X direction and the Y direction of the workpiece table can independently run in parallel.
The calculation formula is as follows:the total distance is shortest, whereinAndx and Y values representing one coordinate.
Andx and Y values representing the working bit coordinates ps (xs, ys) in the previous working sequence (h. field-by-field leveling of the silicon wafer);
or X and Y values representing the work site coordinates p1(X1, Y1) to pn (xn, yn) in the intermediate work sequence (i. fine alignment of silicon wafer).
S803: and (5) solving the problem. Alternative search algorithms include: greedy algorithm, two-pair exchange, three-pair exchange, heuristic algorithm, simulated annealing, ant-cave algorithm and genetic algorithm. They are all approximation algorithms in general, but for problems with low combinatorial complexity like 16-20 points, approximation algorithms usually achieve satisfactory solution results.
S804: and outputting results, wherein the results comprise outputting an optimal scheme, calculating the total distance, calculating the working time, calculating the yield and visualizing the path graph. The result can be seen in the comparison between the silicon wafer fine alignment mark path and the flow in fig. 9 and 10 and the calculation result path of the multiple algorithms in table 2. FIG. 9 is an alignment path diagram of the wait bit in the X forward direction in the first embodiment; fig. 10 is a diagram of an alignment path of the wait bit in the negative X direction in the first embodiment. Fig. 9 the numbers on the coordinate points in fig. 10 in turn represent the order in which the coordinate points are traversed by the planned path.
The embodiment is compatible with precise alignment involving X-direction and Y-direction scanning, and is also compatible with alignment marks scanned at an angle of 45 degrees.
The second embodiment is a nearest neighbor algorithm, which is based on the idea of global optimization, and is a process for designing an optimized path of nearest neighbors of upper and lower work bits, as shown in a program design and an algorithm flowchart of fig. 11.
Is 1101: inputting data, which comprises the positions of coordinate points (such as 16) on the silicon wafer in the fine alignment process of the silicon wafer by referring to the alignment marks, wherein the silicon wafer is driven by the workpiece stage to move to the position right below the alignment sensor, and the last coordinate and the next coordinate of the movement of the workpiece stage in the fine alignment process are included. As shown in fig. 7, the last working position should be the coordinate point of h-field leveling for the silicon wafer, and the next working position j-coordinate point of the two workpiece stages for exchanging the waiting positions.
The second step is that: and (4) setting a constraint boundary, firstly finding a nearest neighbor of the precisely aligned 16 coordinate points and the coordinate of the last work position, and locking. Then the nearest neighbor of the fine alignment 16 coordinate points and the next workstation coordinate is found and locked. In the algorithm processing, in order to meet specific constraint conditions, a penalty function is added to control the relationship. The application of the penalty function here is a weighting of the distance in the traveler problem. If the penalty condition is met, applying a penalty value on the distance; if this condition is not met, no penalty value is imposed.
Two alternative schemes are used for the merit function, the first is the euclidean function and the second is the checkerboard function.
The evaluation function one: the physical Distance between two points is calculated using the Euclidean Distance function (Euclidean Distance).
The calculation formula is as follows:the total distance is shortest, whereinAndx and Y values representing one coordinate.
Andx and Y values representing the working bit coordinates ps (xs, ys) in the previous working sequence (h. field-by-field leveling of the silicon wafer); or represents the X and Y values of the work site coordinates p1(X1, Y1) to pn (xn, yn) in the intermediate work sequence (i. fine alignment of silicon wafer); or the X and Y values representing the work bit coordinates pe (xe, ye) in the next work order (j. work stage swap waiting).
And (3) evaluating a function II: and (3) calculating the maximum value of the Distance between the X point and the Y point as an evaluation function by adopting a Chessboard Distance function (Chessboard Distance) according to the characteristic that the long strokes of the X direction and the Y direction of the workpiece table can independently run in parallel.
The calculation formula is as follows:the total distance is shortest, whereinAndx and Y values representing one coordinate.
Andx and Y values representing the working bit coordinates ps (xs, ys) in the previous working sequence (h. field-by-field leveling of the silicon wafer); or represents the X and Y values of the work site coordinates p1(X1, Y1) to pn (xn, yn) in the intermediate work sequence (i. fine alignment of silicon wafer); or the X and Y values representing the work bit coordinates pe (xe, ye) in the next work order (j. work stage swap waiting).
The third step: and (5) solving the problem. Alternative search algorithms include: greedy algorithm, two-pair exchange, three-pair exchange, heuristic algorithm, simulated annealing, ant-cave algorithm and genetic algorithm. They are all approximation algorithms in general, but for problems with low combinatorial complexity like 16-20 points, approximation algorithms usually achieve satisfactory solution results.
The fourth step: and outputting results, wherein the results comprise outputting an optimal scheme, calculating the total distance, calculating the working time, calculating the yield and visualizing the path graph. The result can be seen in comparison between the silicon wafer fine alignment mark path and the flow in fig. 12 and 13 and the calculation result path of the multiple algorithms in table 2. FIG. 12 is an alignment path diagram of the wait bit in the X forward direction in the first embodiment; fig. 13 is a diagram of an alignment path of the wait bit in the negative X direction in the first embodiment. Fig. 12 the numbers on the coordinate points in fig. 13 in turn represent the order in which the coordinate points are traversed by the planned path.
The embodiment can be compatible with precise alignment involving X-direction and Y-direction scanning, and can also be compatible with 45-degree angle scanning alignment marks.
TABLE 2
Compared with the prior art, the technical scheme has the advantages that: firstly, the alignment precision of the whole machine is ensured, and the alignment mark points of 16 silicon wafers are aligned in sequence. Secondly, improve accurate alignment efficiency simultaneously, and then improve complete machine efficiency. Thirdly, the efficiency of the fine alignment link is improved by 5 to 25 percent, and the efficiency of the whole machine is improved by + 2 chips/hour. Fourthly, the movement path of the workpiece table is shortened, the loss of the workpiece table is reduced, and the service life of the whole machine is prolonged. Fifth, compatible ATHENA and SMASH alignment sensors. Sixth, compatible precision alignment involves X-direction and Y-direction scanning, and is compatible with 45 degree angle scanning alignment marks.
The embodiments described in the specification are only preferred embodiments of the present invention, and the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit the present invention. Those skilled in the art can obtain technical solutions through logical analysis, reasoning or limited experiments according to the concepts of the present invention, and all such technical solutions are within the scope of the present invention.
Claims (6)
1. A silicon wafer alignment method is characterized by comprising the following steps:
step 1, inputting the position of a precise alignment coordinate point on a silicon wafer and the upper and lower coordinates of the motion of a precise alignment process workpiece table;
step 2, taking the distance between the previous station and the next station of the fine alignment process as a constraint function of zero distance, or firstly finding the nearest neighbor point between the previous station and the next station of the fine alignment process, connecting the nearest neighbor points with each other to be used as the constraint function, then optimizing by adopting a traveling quotient algorithm, and adding a penalty function as weight when the constraint condition is met;
step 3, solving the problem by utilizing a search algorithm;
step 4, outputting a solving result; wherein,
the step 1 specifically comprises:
step 1.1, starting scanning from any preparation station p0(x0, y 0) in a silicon wafer exposure process, driving a silicon wafer platform by a motion control unit to drive a silicon wafer to move n alignment marks on the surface of the silicon wafer related to the preparation station one by one to the vertical direction of a mark scanning unit according to the sequence corresponding to positions p1, p2, … … and pn, wherein the n alignment marks are respectively positioned at p1(x1, y1), p2(x2, y2), … … and pn (xn, yn), the sequence is characterized in that the total stroke formed by connecting the positions of the marks traversed by the sequence in a straight line is shortest, namely the coordinates (xi, yi), (xj, yj) of any two points pi and pj before and after the sequence are shortest, and i = 0-n-1, j = i + 1-n;
step 1.2 the calculation formula is as follows:whereinandan X value and a Y value representing the position of the last coordinate of the last working position;andan X value and a Y value representing a position coordinate of a first coordinate of a next working position; the last working position is a position for field-by-field leveling of the silicon wafer, and the next working position is a position for exchanging and waiting two workpiece tables.
2. The silicon wafer alignment method of claim 1, wherein the step 2 of using the distance between the previous station and the next station of the fine alignment process as a constraint function of the zero distance specifically comprises: the distance between the last of the fine alignment working positions and the next of the fine alignment working positions is preset to be 0 when calculating; firstly, finding nearest neighbor points between a previous station and a next station of a fine alignment process, and connecting the nearest neighbor points with the next station to be used as a constraint function; firstly, the nearest neighbor of the precisely aligned 16 coordinate points and the coordinate of the last workstation is found, and then the nearest neighbor of the precisely aligned 16 coordinate points and the coordinate of the next workstation is found.
3. The silicon wafer alignment method of claim 1, wherein the weighted distance is calculated using an evaluation function, and when the evaluation function is a euclidean function, the calculation formula is as follows:the total distance is the shortest,andx and Y values representing the position coordinates ps (xs, ys) in the last position; or represents the X value and the Y value of the working position coordinates p1(X1, Y1) to pn (xn, yn) in the middle working position; or the X and Y values representing the working bit coordinates pe (xe, ye) in the next working bit,andand the X value and the Y value represent the coordinates p1(X1, Y1) of the next working position, and the middle working position is a silicon wafer fine alignment working position.
4. As claimed in claimThe silicon wafer alignment method is characterized in that the weighting distance is obtained by calculation using an evaluation function, and when the evaluation function is a chessboard function, the calculation formula is as follows:the total distance is the shortest,andx and Y values representing the position coordinates ps (xs, ys) in the last position; or represents the X value and the Y value of the middle working position coordinates p1(X1, Y1) to pn (xn, yn),andthe X value and the Y value representing the working position coordinate p1(X1, Y1) in the next working position; the middle working position is a silicon wafer fine alignment working position.
5. The silicon wafer alignment method of claim 1, wherein the search algorithm used in the step 3 is one of the following algorithms: greedy algorithm, two-pair exchange, three-pair exchange, heuristic algorithm, simulated annealing, ant-cave algorithm, or genetic algorithm.
6. The silicon wafer alignment method of claim 1, wherein the angle of scanning in step 1.1 is along the X-direction or Y-direction or 45 degree angle direction.
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