CN103915530A - High-voltage flip-chip LED structure and manufacturing method thereof - Google Patents

Abstract

The invention relates to a high-voltage flip chip LED structure and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: providing a chip substrate; depositing a first passivation layer; forming a common connection layer; depositing a second passivation layer; depositing a mirror layer; etching two conductive channels; and providing two bonding metal layers. The chip substrate comprises a sapphire substrate and a plurality of LED chips thereon, and the LED chips are electrically connected in series by forming a fully transparent common connection layer after forming a first passivation layer. Then, a second passivation layer is deposited to form a flat passivation surface, so that the mirror layer formed thereon can have the same level height, and the reflected light has no optical path difference. Finally, a bonding metal layer is arranged for conducting electricity. The invention can obtain the high-voltage flip chip LED structure with the full transparent electrode and no optical path difference in light emission.

Description

High-voltage flip-chip LED structure and manufacturing method thereof

technical field

The invention relates to an LED structure and a manufacturing method thereof, in particular to a high-voltage flip-chip LED structure and a manufacturing method thereof.

Background technique

In recent years, light-emitting diodes (LEDs) have gradually become the main products in the lighting market, and their small size, high efficiency and environmental protection have been affirmed. Therefore, major manufacturers are all committed to developing LED structures and processes with higher luminous efficiency and high yield.

FIG. 1 is a conventional flip-chip LED structure. As shown in FIG. 1 , a known flip-chip LED structure 100 includes: LED substrate 110, N-pole electrode 150, P-pole electrode 160, welding pad 140, barrier layer 180, reflective layer 120, patterned insulating layer 170 , a conductive layer 190 and an epitaxial stack 130 . Wherein, the epitaxial stack 130 includes: an N-type semiconductor layer 131 , a light emitting layer 132 and a P-type semiconductor layer 133 . In order to increase the light extraction rate, the conventional flip-chip LED structure 100 uses the reflective layer 120 to reflect the light emitted by the light emitting layer 132 so that it emits light in the forward direction. However, the different heights of the reflective layer 120 will cause the reflected light to have an optical path difference.

Currently, the high-voltage LED structure can be achieved by connecting multiple LED chip epitaxial structures in series on the same substrate. It is known that the high-voltage LED structure can simplify the LED packaging process, improve luminous efficiency, and has great competitive potential in the future lighting market. Therefore, how to use the high-voltage LED structure to design a high-voltage flip-chip LED structure that can greatly improve the above-mentioned optical path difference is a problem. important subject.

Contents of the invention

The object of the present invention is to overcome the problems existing in the existing flip-chip LED structure, and provide a high-voltage flip-chip LED structure and a manufacturing method thereof, wherein the manufacturing method includes the following steps: providing a chip substrate; depositing a first passivation layer ; forming a common electrical connection layer; depositing a second passivation layer; depositing a mirror layer; etching two conductive channels; and setting two bonding metal layers. The technical problems to be solved by the present invention include: manufacturing a high-voltage flip-chip LED structure with fully transparent electrodes and reflective layers on the same plane.

The invention provides a method for manufacturing a high-voltage flip-chip LED structure, which includes: providing a chip substrate, wherein the chip substrate includes: a sapphire substrate; and a plurality of LED chips are formed on the sapphire substrate separately from each other, and each LED chip is from bottom to top An N-type layer, a quantum well layer, a P-type layer and a transparent conductive oxide layer are formed on it, and the N-type layer exposes the N-type surface, and the LED chip includes a first LED chip and a second LED chip; depositing a first passivation layer , which deposits a first passivation layer around the LED chip; forms a common electrical connection layer, which after removing the first passivation layer on each transparent conductive oxide layer and each N-type surface, respectively A first electrical connection layer and a second electrical connection layer are formed on each transparent conductive oxide layer and each N-type surface, and a third electrical connection layer is formed to connect the first electrical connection layer of the LED chip with another adjacent The second electrical connection layer of the LED chip, the first electrical connection layer, the second electrical connection layer and the third electrical connection layer form a common electrical connection layer; the second passivation layer is deposited on the first passivation layer and the common electrical connection layer connect the layer and form a flat passivation surface; deposit a mirror layer, which deposits a mirror layer on the passivation surface; etch two conductive channels, which are respectively etched from the mirror layer down to the first electrical connection layer and the first LED chip. Etching down to the second electrical connection layer of the second LED chip to form the conductive path; and setting two bonding metal layers, which respectively fill bonding metal in each conductive path, and setting the bonding metal layer on the mirror layer , to respectively bond with the bonding metal, and the bonding metal layers are separated from each other.

Preferably, the aforementioned manufacturing method further includes forming a plurality of microstructures on the backside surface of the sapphire substrate.

Preferably, the aforementioned manufacturing method further includes bonding a circuit board, which is electrically connected to the conductive metal on the circuit board through the bonding metal layer.

Preferably, in the aforementioned manufacturing method, the mirror layer is composed of a distributed Bragg reflector and metal.

Preferably, in the aforementioned manufacturing method, the metal is aluminum or silver.

Preferably, in the aforementioned manufacturing method, the surface of the bonding metal layer is electroplated with a gold film.

The present invention also provides a high-voltage flip-chip LED structure, which includes: a chip substrate, wherein the chip substrate includes: a sapphire substrate; and a plurality of LED chips, which are separately formed on the sapphire substrate, and each LED chip is formed from bottom to top N-type layer, quantum well layer, P-type layer and transparent conductive oxide layer, and the N-type layer exposes the N-type surface, the LED chip includes a first LED chip and a second LED chip; a first passivation layer, which is set On the side of each LED chip; a common electrical connection layer, which includes: a first electrical connection layer, which is located on each transparent conductive oxide layer; a second electrical connection layer, which is located on each N-type surface; and The third electrical connection layer, which connects each adjacent first electrical connection layer and the second electrical connection layer and covers the first passivation layer on the side of each LED chip; the second passivation layer, which covers the first electrical connection layer A passivation layer and a common electrical connection layer to form a flat passivation surface; a mirror layer, which is arranged on the passivation surface; two bonding metals, which pass through the mirror layer and the second passivation layer to respectively connect with the first LED chip The first electrical connection layer of the second LED chip is connected to the second electrical connection layer; and two bonding metal layers are respectively arranged on the mirror layer and bonded to the bonding metal, and the bonding metal layers are separated from each other.

Preferably, the aforementioned high-voltage flip-chip LED structure further includes a circuit board, which is electrically connected to the bonding metal layer through conductive metal.

Preferably, in the aforementioned high-voltage flip-chip LED structure, the mirror layer is composed of a distributed Bragg reflector and metal.

Preferably, in the aforementioned high-voltage flip-chip LED structure, the metal is aluminum or silver.

Preferably, in the aforementioned high-voltage flip-chip LED structure, the surface of the bonding metal layer is electroplated with a gold film.

Preferably, in the aforementioned high-voltage flip-chip LED structure, the backside surface of the sapphire substrate further includes a plurality of microstructures.

By implementing the present invention, at least the following progressive effects can be achieved:

1. A flip-chip LED structure with fully transparent electrodes can be obtained to increase luminous efficiency.

2. A flip-chip LED structure in which the reflective layer is located on the same plane can be obtained to reduce the optical path difference.

The above description is only an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the contents of the description, and in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable , the following preferred embodiments are specifically cited, and in conjunction with the accompanying drawings, the detailed description is as follows.

Description of drawings

FIG. 1 is a conventional flip-chip LED structure.

FIG. 2 is a flowchart of a manufacturing method of a high-voltage flip-chip LED structure according to an embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view of a step of providing a chip substrate according to an embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view of a step of depositing a first passivation layer according to an embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view of etching a first passivation layer according to an embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view of a step of forming a common electrical connection layer according to an embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view of a step of depositing a second passivation layer according to an embodiment of the present invention.

FIG. 8 is a schematic cross-sectional view of a step of depositing a mirror layer according to an embodiment of the present invention.

FIG. 9 is a schematic cross-sectional view of a step of etching two conductive channels according to an embodiment of the present invention.

FIG. 10 is a schematic cross-sectional view of a conductive metal filling according to an embodiment of the present invention.

FIG. 11 is a schematic cross-sectional view of a step of disposing two bonding metal layers according to an embodiment of the present invention.

FIG. 12 is a schematic cross-sectional view of a step of forming multiple microstructures according to an embodiment of the present invention.

FIG. 13 is a schematic cross-sectional view of a step of combining circuit boards according to an embodiment of the present invention.

Fig. 14 is a cross-sectional view of the structure of a high-voltage flip-chip LED according to an embodiment of the present invention.

Fig. 15 is a cross-sectional view of the structure of the high-voltage flip-chip LED according to the embodiment of the present invention.

[Description of main component symbols]

10 Chip substrate 11 Sapphire substrate

111 first surface 112 second surface

113 Microstructure 12 LED chip

12’ 1st LED chip 12” 2nd LED chip

12”’ third LED chip 121 N-type layer

122 N-type surface 123 Quantum well layer

124 P-type layer 125 Transparent conductive oxide layer

20 first passivation layer 30 common electrical connection layer

31 The first electrical connection layer 32 The second electrical connection layer

33 The third electrical connection layer 40 The second passivation layer

41 passivated surface 50 mirror layer

60 Conductive Path 61 Joining Metals

70 bonding metal layer 80 circuit board

81 Conductive metal 100 Flip chip LED structure

110 LED substrate 120 Reflective layer

130 Epitaxial stack 131 N-type semiconductor layer

132 Light-emitting layer 133 P-type semiconductor layer

140 welding pad 150 N electrode

160 P pole electrode 170 patterned insulating layer

180 Barrier layer 190 Conductive layer

Detailed ways

In order to further explain the technical means adopted by the present invention to achieve the intended purpose of the invention and its efficacy, the specific implementation and structure of the high-voltage flip-chip LED structure and its manufacturing method proposed according to the present invention will be described below in conjunction with the accompanying drawings and preferred embodiments. , process, features and effects thereof are described in detail below.

FIG. 2 is a flowchart of a manufacturing method of a high-voltage flip-chip LED structure according to an embodiment of the present invention. FIG. 3 is a schematic cross-sectional view of a step of providing a chip substrate according to an embodiment of the present invention. FIG. 4 is a schematic cross-sectional view of a step of depositing a first passivation layer according to an embodiment of the present invention. FIG. 5 is a schematic cross-sectional view of etching a first passivation layer according to an embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a step of forming a common electrical connection layer according to an embodiment of the present invention. FIG. 7 is a schematic cross-sectional view of a step of depositing a second passivation layer according to an embodiment of the present invention. FIG. 8 is a schematic cross-sectional view of a step of depositing a mirror layer according to an embodiment of the present invention.

FIG. 9 is a schematic cross-sectional view of a step of etching two conductive channels according to an embodiment of the present invention. FIG. 10 is a schematic cross-sectional view of a conductive metal filling according to an embodiment of the present invention. FIG. 11 is a schematic cross-sectional view of a step of disposing two bonding metal layers according to an embodiment of the present invention. FIG. 12 is a schematic cross-sectional view of a step of forming multiple microstructures according to an embodiment of the present invention. FIG. 13 is a schematic cross-sectional view of a step of combining circuit boards according to an embodiment of the present invention. Fig. 14 is a cross-sectional view of the structure of a high-voltage flip-chip LED according to an embodiment of the present invention. Fig. 15 is a cross-sectional view of the structure of the high-voltage flip-chip LED according to the embodiment of the present invention.

<Example of Manufacturing Method of High Voltage Flip-Chip LED Structure>

As shown in FIG. 2, an embodiment of the present invention is a manufacturing method S100 of a high-voltage flip-chip LED structure, which includes: providing a chip substrate (step S10); depositing a first passivation layer (step S20); forming a common electrical connection layer (step S30); deposit a second passivation layer (step S40); deposit a mirror layer (step S50); etch two conductive channels (step S60); and set two bonding metal layers (step S70).

As shown in FIG. 3 , a chip substrate is provided (step S10 ), wherein the chip substrate 10 includes: a sapphire substrate 11 and a plurality of LED chips 12 . The sapphire substrate 11 is used to grow GaN N-type layer 121 (hereinafter referred to as N-type layer 121), quantum well layer 123, GaN P-type layer 124 (hereinafter referred to as P-type layer 124) and transparent conductive oxide layer 125, after which a plurality of LED chips 12 (such as 12', 12" and 12"' in FIG. 111 is the upper surface of the sapphire substrate 11 . The material of the transparent conductive oxide layer 125 is a transparent oxide to improve luminous efficiency, and can conduct electricity.

Therefore, each LED chip 12 forms an N-type layer 121 , a quantum well layer 123 , a P-type layer 124 and a transparent conductive oxide layer 125 from bottom to top in the epitaxy process. At the same time, part of the transparent conductive oxide layer 125 , the P-type layer 124 and the quantum well layer 123 are etched to expose the N-type surface 122 of the N-type layer 121 . In order to describe the LED chips 12 in more detail, the LED chips 12 are respectively named as the first LED chip 12', the second LED chip 12" and the third LED chip 12"' in this embodiment. The first LED chip 12' is the leftmost LED chip 12 on the sapphire substrate 11, the second LED chip 12" is the rightmost LED chip 12 on the sapphire substrate 11, and the third LED chip 12"' is the Between the first LED chip 12' and the second LED chip 12", however, a plurality of third LED chips 12"' may also be arranged.

As shown in FIG. 4, deposit a first passivation layer (step S20), which deposits a first passivation layer 20 around the LED chip 12, so that the first passivation layer 20 covers each N-type layer 121, quantum The sides of the well layer 123 , the P-type layer 124 and the transparent conductive oxide layer 125 and the surfaces of the sapphire substrate 11 , the N-type surface 122 and the transparent conductive oxide layer 125 .

As shown in FIG. 5 , before forming the common electrical connection layer (step S30 ), the first passivation layer 20 located on each transparent conductive oxide layer 125 and each N-type surface 122 is removed by etching.

As shown in FIG. 6, a common electrical connection layer is formed (step S30), and then a common electrical connection layer 30 is formed on the first passivation layer 20 and each exposed N-type surface 122 and each transparent conductive oxide by deposition. surface of layer 125 . For convenience of description, the common electrical connection layer 30 is defined as a first electrical connection layer 31 , a second electrical connection layer 32 and a third electrical connection layer 33 . The first electrical connection layer 31 is formed on the surface of each transparent conductive oxide layer 125 , and the second electrical connection layer 32 is formed on each N-type surface 122 . The third electrical connection layer 33 extends from the first electrical connection layer 31 of the LED chip 12 along the side of the LED chip 12 to the second electrical connection layer 32 of another adjacent LED chip 12 . The third electrical connection layer 33 is used to electrically connect the first electrical connection layer 31 of the LED chip 12 and the second electrical connection layer 32 of another adjacent LED chip 12 .

Wherein, the common electrical connection layer 30 can connect multiple LED chips 12 in series to form a high-voltage LED structure. The material forming the common electrical connection layer 30 can be the same as that of the transparent conductive oxide layer 125 , and the transparent conductive material can prevent the common electrical connection layer 30 from blocking the light emitted by the LED chip 12 , while achieving the purpose of conducting electricity and improving light transmittance.

As shown in FIG. 7, deposit a second passivation layer (step S40), which deposits a second passivation layer 40 on the first passivation layer 20 and the common electrical connection layer 30 exposed to the outside world, and deposits the second passivation layer continuously. The passivation layer 40 covers all the LED chips 12 and forms a flat passivation surface 41 with the same height, so as to provide subsequent processes.

As shown in FIG. 8 , deposit a mirror layer (step S50 ), which deposits a mirror layer 50 on a passivation surface 41 that is flat and has the same height, so the mirror layer 50 deposited thereon is also flat and has the same height, so that the LED chip 12 The emitted light can be reflected by the mirror layer 50 at the same height to obtain reflected light with consistent reflection amount and intensity, and at the same time, the reflected light with no optical path difference can be emitted toward the sapphire substrate 11 . Wherein, the mirror layer 50 may be composed of a distributed Bragg reflector (Distributed Bragg Reflector, DBR) and metal, and the metal may be aluminum or silver.

As shown in FIG. 9, two conductive channels are etched (step S60), which are respectively etched from the mirror layer 50 to the first LED chip 12 through the second passivation layer 40 at positions near the top of the first LED chip 12'. 'The first electrical connection layer 31, and the mirror layer 50 is etched down through the second passivation layer 40 to the second electrical connection layer of the second LED chip 12" at a position near the top relative to the second LED chip 12" 32 to form the conductive channel 60, so that the first electrical connection layer 31 of the first LED chip 12' and the second electrical connection layer 32 of the second LED chip 12" can be exposed.

As shown in FIG. 10, two bonding metal layers are provided (step S70). Firstly, the bonding metal 61 is filled in each conductive channel 60 etched in step S60 respectively, and the surface of the bonding metal 61 is at the same position as the surface of the mirror layer 50. high.

As shown in FIG. 11 , next, the two bonding metal layers 70 are disposed on the mirror layer 50 , and the bonding metal layers 70 are respectively bonded one-to-one with the bonding metal 61 for conduction. Therefore, the bonding metal layer 70 can be electrically connected to the first electrical connection layer 31 of the first LED chip 12' and the second electrical connection layer 32 of the second LED chip 12" respectively by the bonding metal 61. In order to avoid short circuit, The bonding metal layers 70 are separated from each other. Wherein, the surfaces of the bonding metal layers 70 may be electroplated with a gold film to improve electrical conductivity.

As shown in FIG. 1 and FIG. 12 , the manufacturing method S100 may further include forming a plurality of microstructures (step S80 ), which forms a plurality of microstructures 113 on the second surface 112 of the sapphire substrate 11 to destroy total reflection. The second surface 112 is the lower surface of the sapphire substrate 11 , and the microstructure 113 can be a pyramid, a convex lens, or a concave lens.

As shown in Figures 1 and 13, the manufacturing method S100 may further include combining a circuit board (step S90), which inverts the above-mentioned structure, and through electrical connection means, such as metal electrodes or solder balls (solder ball) so that all The bonding metal layer 70 is electrically connected to the conductive metal 81 on the circuit board 80 to form a final high voltage flip-chip LED structure.

<Example of High Voltage Flip Chip LED Structure>

As shown in FIG. 1 and FIG. 14, another embodiment of the present invention is a high-voltage flip-chip LED structure 100, which includes: a chip substrate, a first passivation layer 20, a common electrical connection layer 30, a second passivation layer 40 , mirror layer 50 , two bonding metal layers 61 and two bonding metal layers 70 . The high voltage flip-chip LED structure 100 can be manufactured using the above-mentioned manufacturing method S100.

The chip substrate includes: a sapphire substrate 11 and a plurality of LED chips 12 . Wherein, a plurality of LED chips 12 are separately formed on the first surface 111 of the sapphire substrate 11 , and the first surface 111 is the upper surface of the sapphire substrate 11 . In addition, the second surface 112 of the sapphire substrate 11 can further include a plurality of microstructures 113 to destroy total reflection, and the second surface 112 is the lower surface of the sapphire substrate 11, wherein the microstructures 113 can be cones, convex lenses or concave lenses, etc. structure.

Each LED chip 12 is formed from bottom to top with an N-type layer 121 , a quantum well layer 123 , a P-type layer 124 and a transparent conductive oxide layer 125 . Wherein, the plane area of the quantum well layer 123 , the P-type layer 124 and the transparent conductive oxide layer 125 is smaller than the plane area of the N-type layer 121 , so that the lowermost N-type layer 121 exposes the N-type surface 122 . The material of the transparent conductive oxide layer 125 is a transparent oxide to improve light transmittance and conduct electricity.

In order to describe the LED chips 12 in more detail, the LED chips 12 are respectively named as the first LED chip 12', the second LED chip 12" and the third LED chip 12"' in this embodiment. The first LED chip 12' is the leftmost LED chip 12 on the sapphire substrate 11, the second LED chip 12" is the rightmost LED chip 12 on the sapphire substrate 11, and the third LED chip 12"' is the Between the first LED chip 12' and the second LED chip 12", however, a plurality of third LED chips 12"' may also be arranged, for example, there are two third LED chips 12"' in the embodiment of the present invention.

The first passivation layer 20 is disposed on the side of each LED chip 12 , such as the side of each N-type layer 121 , quantum well layer 123 , P-type layer 124 and transparent conductive oxide layer 125 .

The common electrical connection layer 30 includes: a first electrical connection layer 31 , a second electrical connection layer 32 and a third electrical connection layer 33 . The first electrical connection layer 31 is located on the surface of each transparent conductive oxide layer 125, the second electrical connection layer 32 is located on each N-type surface 122, and the third electrical connection layer 33 is connected to each adjacent third An electrical connection layer 31 and a second electrical connection layer 32 cover the first passivation layer 20 on the side of each LED chip 12 . In other words, the third electrical connection layer 33 extends from the first electrical connection layer 31 end of the LED chip 12 along the side of the LED chip 12 to the second electrical connection layer 32 end of another adjacent LED chip 12, so as to A plurality of LED chips 12 are connected in series to form a high voltage LED structure.

The material forming the common electrical connection layer 30 can be the same as that of the transparent conductive oxide layer 125 , and the transparent conductive material can prevent the common electrical connection layer 30 from blocking light, while achieving the purpose of conducting electricity and improving luminous efficiency.

The second passivation layer 40 covers the first passivation layer 20 and the common electrical connection layer 30 , and covers all the LED chips 12 to form a flat passivation surface 41 , which is further provided for subsequent processes.

The mirror layer 50 is arranged on the passivation surface 41. Since the passivation surface 41 is very flat, the mirror layer 50 on it also has the same horizontal height, and light reflection can be performed at the same height to obtain the same reflection amount and intensity. The reflected light, and the reflected light with no optical path difference between each other can emit light toward the direction of the sapphire substrate 11 . Wherein, the mirror layer 50 may be composed of a distributed Bragg reflector (DBR) and metal, and the metal may be aluminum or silver.

Two bonding metals 61, which respectively pass through the mirror layer 50 and the second passivation from the surface of the mirror layer 50 at positions near the top relative to the first LED chip 12' and at positions near the top relative to the second LED chip 12" The layer 40 is connected to the first electrical connection layer 31 of the first LED chip 12 ′ and the second electrical connection layer 32 of the second LED chip 12 ″ respectively to form an electrical connection.

The two bonding metal layers 70 are respectively disposed on the mirror layer 50 and are one-to-one bonded to the bonding metal 61 to form an electrical connection, and the bonding metal layers 70 are separated from each other to avoid short circuit. Wherein, the surface of the bonding metal layer 70 is electroplated with a gold film to improve electrical conductivity.

As shown in FIG. 15 , the high-voltage flip-chip LED structure 100 may further include a circuit board 80, which is electrically connected to the bonding metal layer 70 by means of a conductive metal 81 on the circuit board 80, and is electrically connected to the circuit board 80. The structure is inverted to form the final high voltage flip chip LED structure 100 . Wherein, the circuit board 80 may also be a ceramic circuit board.

The above is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this field Those skilled in the art, without departing from the scope of the technical solution of the present invention, may use the method and technical content disclosed above to make some changes or modifications to equivalent embodiments with equivalent changes, but if they do not depart from the technical solution of the present invention, Any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention still fall within the scope of the technical solutions of the present invention.

Claims (12)

1. a high manufacture method that covers brilliant LED structure, is characterized in that comprising:

Chip substrate is provided, and wherein this chip substrate comprises: sapphire substrate; And multiple LED chips, be formed separated from each other on this sapphire substrate, each this LED chip forms N-type layer, quantum well layer, P type layer and including transparent conducting oxide layer from lower to upper, and this N-type layer exposes N-type surface, and described LED chip comprises the first LED chip and the second LED chip;

Deposit the first passivation layer, it deposits this first passivation layer around described LED chip;

Form common-battery and connect layer, it is removing position after each this including transparent conducting oxide layer and lip-deep this first passivation layer of each this N-type, respectively at forming the first be electrically connected layer and second layer that is electrically connected on each this including transparent conducting oxide layer and each this N-type surface, and form the 3rd and be electrically connected layer to connect this first this second layer that is electrically connected that is electrically connected layer and adjacent another this LED chip of this LED chip, this first be electrically connected layer, this second layer and the 3rd layer that is electrically connected that is electrically connected forms this common-battery and connects layer;

Deposit the second passivation layer, it is deposited on this first passivation layer and smooth passivated surface is gone up and formed to this common-battery company layer;

Deposition specular layer, it deposits this specular layer on this passivated surface;

Etching two conductive channels, its respectively from this specular layer toward be etched down to this first LED chip this first be electrically connected layer and toward be etched down to this second LED chip this second be electrically connected layer to form described conductive channel; And

Two jointing metal layers are set, and it fills jointing metal at each this conductive channel respectively, and described jointing metal layer is set on this specular layer, and to engage with this jointing metal respectively, and described jointing metal layer is separated from one another.

2. manufacture method as claimed in claim 1, is characterized in that further comprising forming multiple micro-structurals in the back surface of this sapphire substrate.

3. manufacture method as claimed in claim 1, is characterized in that further comprising combined circuit plate, and it is electrically connected with the conducting metal on described jointing metal layer and this circuit board.

4. manufacture method as claimed in claim 1, is characterized in that wherein this specular layer is made up of distribution Bragg reflector and metal.

5. manufacture method as claimed in claim 4, is characterized in that wherein this metal is aluminium or silver.

6. manufacture method as claimed in claim 1, is characterized in that the surface electrical of wherein said jointing metal layer is coated with gold thin film.

7. highly cover a brilliant LED structure, it is characterized in that comprising:

Chip substrate, wherein this chip substrate comprises: sapphire substrate; And multiple LED chips, be formed separated from each other on this sapphire substrate, each this LED chip forms N-type layer, quantum well layer, P type layer and including transparent conducting oxide layer from lower to upper, and this N-type layer exposes N-type surface, and described LED chip comprises the first LED chip and the second LED chip;

The first passivation layer, it is arranged at the side of each this LED chip;

Common-battery connects layer, and it comprises: first layer that is electrically connected, and it is positioned on each this including transparent conducting oxide layer; Second layer that is electrically connected, it is positioned on each this N-type surface; And the 3rd layer that is electrically connected, it connects each adjacent this first be electrically connected layer be covered in this first passivation layer of each this LED chip side of layer and this second that is electrically connected;

The second passivation layer, its coated this first passivation layer and this common-battery connect layer to form smooth passivated surface;

Specular layer, it is arranged on this passivated surface;

Two jointing metals, its through this specular layer and this second passivation layer to join with this first this second layer that is electrically connected that is electrically connected layer and this second LED chip of this first LED chip respectively; And

Two jointing metal layers, it is arranged at respectively on this specular layer and with described jointing metal and engages, and described jointing metal layer is separated from one another.

8. height as claimed in claim 7 covers brilliant LED structure, it is characterized in that it further comprises circuit board, and it is electrically connected with conducting metal and described jointing metal layer.

9. height as claimed in claim 7 covers brilliant LED structure, it is characterized in that wherein this specular layer is made up of distribution Bragg reflector and metal.

10. height as claimed in claim 9 covers brilliant LED structure, it is characterized in that wherein this metal is aluminium or silver.

11. height as claimed in claim 7 cover brilliant LED structure, it is characterized in that the surface electrical of wherein said jointing metal layer is coated with gold thin film.

12. height as claimed in claim 7 cover brilliant LED structure, it is characterized in that wherein the back surface of this sapphire substrate further comprises multiple micro-structurals.