CN103915464B - 1T1R array based on transparent RRAM gated thin film transistor and preparation method thereof - Google Patents

Abstract

The invention discloses a kind of 1T1R array based on transparent RRAM gated thin film transistor and preparation method thereof, described 1T1R array includes logic circuit, signal input circuit, signal output apparatus, power supply Vdd；Wherein said logic circuit includes 1T1R unit, the first transistor；Described 1T1R unit includes resistive resistance and transistor seconds.Described logic circuit connects signal input circuit and signal output apparatus.The present invention is designed by the annexation of transistor AND gate resistive resistance, it is achieved that the logic function that 1T1R array is complicated.

Description

1T1R array based on transparent RRAM gate-controlled thin film transistor and its preparation method

technical field

The invention relates to the technical field of information storage, and more specifically relates to a 1T1R array based on a transparent RRAM gate-controlled thin film transistor and a preparation method thereof.

Background technique

Resistive random access memory (resistive random access memory), that is, RRAM, as a new type of non-volatile memory, realizes high speed (<5ns), high density, low operating voltage (<1V), high Integration and other characteristics, it is a strong competitor for future semiconductor memory. Transparent RRAM devices generally have a metal-insulator-metal structure, by adding a layer of nickel oxide (NiO), titanium oxide (TiO ₂ ), hafnium oxide (HfO ₂ ) or zirconium oxide (ZrO ₂ ) between two layers of conductive metal, etc. The dielectric thin film material with resistive properties realizes the transformation of the resistive material between high and low resistance states, thereby realizing data erasing and writing. Generally speaking, thin film materials can be formed by methods such as sputtering, chemical vapor deposition, atomic layer deposition, and sol-gel.

Thin-film transistor (thin-film transistor), that is, TFT is a transistor technology based on thin-film technology, which can usually be prepared by chemical vapor deposition, sol-gel and other methods. It is widely used in logic circuits. In the traditional RRAM-based 1T1R (1Transistor and 1RRAM Device) structure, thin-film transistors (TFTs) are used as selection transistors, and RRAMs are used as storage units. Their functions are relatively single, and complex logic functions cannot be realized.

Contents of the invention

(1) Technical problems to be solved

The technical problem to be solved by the present invention is how to overcome the shortcoming of the single function of the 1T1R array and realize complex logic functions.

(2) Technical solution

In order to solve the above technical problems, the present invention provides a 1T1R array based on transparent RRAM gate-controlled thin film transistors, the 1T1R array includes a logic circuit, a signal input circuit, a signal output circuit, and a power supply Vdd; wherein the logic circuit includes a 1T1R unit , a first transistor; the 1T1R unit includes a resistance variable resistor and a second transistor;

The second transistor is an NMOS transistor or a PMOS transistor; when the second transistor is an NMOS transistor, the first transistor is a PMOS transistor, and the connection of the 1T1R array is: one end of the resistance variable resistor is connected to the signal input circuit , the other end is connected to the gate of the second transistor, the source of the second transistor is grounded, its drain is connected to the signal output circuit and the drain of the first transistor, and the gate of the first transistor The pole is grounded, and its source is connected to the power supply Vdd;

When the second transistor is a PMOS transistor, the first transistor is an NMOS transistor, and the connection of the 1T1R array is: one end of the resistance variable resistor is connected to the signal input circuit, and the other end is connected to the gate of the second transistor , the source of the second transistor is connected to the power supply Vdd, and its drain is connected to the signal output circuit and the drain of the first transistor; the gate of the first transistor is connected to the power supply Vdd, and its drain is connected to the signal output circuit and the drain of the first transistor; Source ground.

Preferably, there is at least one 1T1R unit, and if there is more than one 1T1R unit, the 1T1R unit is connected in parallel.

A method for preparing a 1T1R array based on a transparent RRAM gate-controlled thin film transistor, characterized in that it comprises the following steps:

S1, making a logic circuit, specifically:

preparing a substrate for the second transistor;

forming a gate on the substrate;

generating a resistive variable resistor at the gate;

forming an insulating layer on the gate;

generating an electrode layer on the resistive variable resistor;

forming a remainder of the second transistor cell on the substrate;

preparing the gate, source and drain of the first transistor;

S2. Prepare a signal input circuit and a signal output circuit;

S3. Correspondingly connecting the signal input circuit and the signal output circuit to the logic circuit respectively.

Preferably, in the step S1, generating the rest of the second transistor unit on the substrate is specifically:

forming a channel layer on the insulating layer;

A source and a drain are respectively formed in the channel layer.

(3) Beneficial effects

The invention provides a 1T1R array based on a transparent RRAM gate-controlled thin film transistor and a preparation method, and realizes complex logic functions of the 1T1R array through the design of the connection relationship between the transistor and the resistance variable resistor.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

Fig. 1 is a kind of structural representation that 1T1R array of the present invention comprises two 1T1R units;

Fig. 2 is another kind of structural representation that 1T1R array of the present invention comprises two 1T1R units;

The preparation method flowchart of Fig. 3 of the present invention;

FIG. 4 is a schematic structural diagram of a second transistor and a resistance variable resistor of the present invention.

Reference signs:

1. Substrate; 2. Gate; 3. Insulation layer; 4. Channel layer; 5. Source; 6. Drain; 7. Resistor; 8. Upper electrode layer.

detailed description

The present invention will be described in further detail below in conjunction with the accompanying drawings and embodiments. The following examples serve to illustrate the present invention, but are not intended to limit the scope of the present invention.

The 1T1R array based on transparent RRAM gate-controlled thin film transistors of the present invention includes a logic circuit, a signal input circuit, a signal output circuit, and a power supply Vdd; wherein the logic circuit includes a 1T1R unit and a first transistor; the 1T1R unit includes a resistance variable resistor and the second transistor; there is at least one 1T1R unit, and if there is more than one 1T1R unit, the 1T1R unit is connected in parallel. The second transistor is an NMOS transistor or a PMOS transistor.

Fig. 1 is a 1T1R array of the present invention including a schematic diagram of a structure of two 1T1R units; when the second transistor in the figure is an NMOS transistor, the first transistor is a PMOS transistor, and the connection of the 1T1R array is: one end of the resistance variable resistor is connected The other end of the signal input circuit is connected to the gate of the second transistor, the source of the second transistor is grounded, and its drain is connected to the signal output circuit and the drain of the first transistor. The gate of the first transistor is grounded, and the source of the first transistor is connected to the power supply Vdd. In the figure, OUT is the output end of the signal output circuit; r1 and r2 are resistance variable resistors; A and B are input signals. The OUT output terminal can form the following logic according to the input A, B signal and RRAM on-off, $\mathrm{out}=\stackrel{\&OverBar;}{r_1}\&CenterDot;\stackrel{\&OverBar;}{r_2}+\stackrel{\&OverBar;}{r_1}\&Center\; Dot;r_2\&Center\; Dot;\stackrel{\&OverBar;}{B}+\stackrel{\&OverBar;}{r_2}\&CenterDot;r_1\&Center\; Dot;\stackrel{\&OverBar;}{A}+r_1\&Center\; Dot;r_2\&CenterDot;\stackrel{\&OverBar;}{A}\&CenterDot;\stackrel{\&OverBar;}{B}.$ By programming r ₁ and r ₂ of 1T1R, different on-off combinations are realized (where 0 means high-impedance state disconnection, 1 means low-impedance state connection), and the logical combination can be obtained as shown in the following table:

It should be pointed out that the input variables are not limited to A and B, and more input terminals can be arbitrarily added on the basis of Fig. 1 . However, it should be noted that the 1T1R units that implement logic functions must appear in parallel.

When realizing the above-mentioned 1T1R array, it is necessary to prepare the second transistor, the resistive variable resistor, etc. on the substrate of the second transistor, specifically:

The substrate 1 is preferably a glass substrate, and may also be some transparent flexible substrates. The drain region is preferably made of conductive materials such as platinum, titanium, copper, aluminum, titanium oxide, nickel, and tungsten. The resistance variable resistor 7 can be made of metal oxide materials such as hafnium oxide, titanium oxide, zirconium oxide, zinc oxide, tungsten oxide, tantalum oxide, or a combination thereof, and the thickness can be 10nm-100nm. The general chemical formula of the oxide thin film that can be used in the channel layer is In-X-Zn-O, wherein, X is silicon, germanium, lanthanum, iridium, etc., and the In-X-Zn-O oxide is doped A thin film of at least one element among metal elements titanium, aluminum, magnesium, zirconium, hafnium, praseodymium, cerium and neodymium. The gate 2 can be made of conductive materials such as FTO and ITO. The source electrode 5 and the drain electrode 6 can be made of platinum, titanium, copper, aluminum, titanium oxide, nickel, tungsten and other conductive materials. The insulating layer 3 may be a dielectric material such as hafnium oxide, zirconium oxide, etc. or a mixture thereof. The upper electrode can be made of conductive materials such as ITO and FTO.

As shown in Figure 4, when the gate-controlled 1T1R array has the structure shown in Figure 1, the preparation method includes steps:

Cleaning the substrate 1: cleaning the glass substrate with an ultrasonic cleaner;

Preparation of gate 2: photolithography out of the gate, using magnetron sputtering technology to grow FTO (fluorine tin oxide) conductive film, using the lift-off method to form gate 2;

Preparation of ZrO2 gate dielectric (insulating layer 3) and resistive switch layer 7: growth of zirconia by sol-gel method, PECVD (PlasmaEnhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition) technology or magnetron sputtering technology or ALD technology Gate dielectric layer and resistive layer thin film;

Preparation of In-Y-Zn-O film (channel layer 4): using a sol-gel method to form an In-Y-Zn-O film;

Preparation of source and drain electrodes: photolithography is carried out on the above samples, deposited by PVD (Physical Vapor Deposition, physical vapor deposition) process, and the source electrode 5 and the drain electrode 6 are formed by a lift-off method to obtain a TFT device;

Prepare the upper electrode: use the gate 2 as the bottom electrode of the RRAM, use the sol-gel process or PVD (Physical Vapor Deposition, physical vapor deposition), CVD (Chemical Vapor Deposition, chemical vapor deposition) or ALD (Atomic layer deposition, atomic layer deposition) ) and other techniques to deposit conductive materials such as ITO and FTO, and perform annealing treatment to form the upper electrode 8 .

The completed structure is shown in the corresponding figure 4.

In the present invention, different resistance values are preset by applying voltage to the resistance variable resistor, so that the signal output circuit can output the required signal.

Fig. 2 is another kind of structure schematic diagram that 1T1R array of the present invention comprises two 1T1R units; When the second transistor is a PMOS transistor, the first transistor is an NMOS transistor, and the connection of the 1T1R array is: the resistance variable resistor One end is connected to the signal input circuit, the other end is connected to the gate of the second transistor, the source of the second transistor is connected to the power supply Vdd, and its drain is connected to the signal output circuit and the first transistor. The drain of the first transistor is connected; the gate of the first transistor is connected to the power supply Vdd, and the source of the first transistor is grounded. In the figure, OUT is the output end of the signal output circuit; r1 and r2 are resistance variable resistors; A and B are input signals. The OUT output terminal can form the following logic according to the input A, B signal and RRAM on-off, $\mathrm{out}=\stackrel{\&OverBar;}{r_1}\&CenterDot;\stackrel{\&OverBar;}{r_2}+\stackrel{\&OverBar;}{r_1}\&CenterDot;r_2\&CenterDot;\stackrel{\&OverBar;}{B}+\stackrel{\&OverBar;}{r_2}\&Center\; Dot;r_1\&Center\; Dot;\stackrel{\&OverBar;}{A}+r_1\&Center\; Dot;r_2\&Center\; Dot;\stackrel{\&OverBar;}{A}\&Center\; Dot;\stackrel{\&OverBar;}{B}.$ By programming r ₁ and r ₂ of 1T1R, different on-off combinations are realized (where 0 means high-impedance state disconnection, 1 means low-impedance state connection), and the logical combination can be obtained as shown in the following table:

It should be pointed out that the input variables are not limited to A and B, and more input terminals can be arbitrarily added on the basis of Fig. 2 . However, it should be noted that the transistors that implement logic functions must appear in parallel. The preparation method of the array shown in FIG. 2 is the same as that of the array shown in FIG. 1 and the materials used, and will not be repeated here.

The present invention also discloses a method for preparing a 1T1R array based on a transparent RRAM gate-controlled thin film transistor, which is summarized as follows, as shown in Figure 3:

S1: preparing a logic circuit;

S2: preparing a signal input circuit and a signal output circuit;

In practice, logic circuits, signal input circuits and signal output circuits can be fabricated on one substrate.

S3: Correspondingly connecting the signal input circuit and the signal output circuit to the logic circuit. The corresponding connection refers to connecting the signal input circuit, the signal output circuit and the logic circuit as required, so that the signal output circuit outputs the required signal.

In practice, the logic circuit is usually prepared first, and then the signal input circuit and signal output circuit are prepared. Taking Figure 4 as an example, the logic circuit prepared in the corresponding step S1 is specifically:

S11: preparing substrate 1;

S12: generating gate material 2 on the substrate;

S13: generating a resistive variable resistor 7 and a TFT insulating layer 3 on the substrate;

S14: generating other units of the transistor on the substrate;

S15: generating an upper electrode layer 8 on the resistive variable resistor 7;

S16: preparing the gate, source and drain of the first transistor.

The generating transistor unit on the substrate described in step S14 is specifically:

S141: forming a channel layer 4 on the insulating layer 3;

S142: Forming a source 5 and a drain 6 on the channel layer 4 respectively.

The varistor 7 can be made of metal oxide materials such as hafnium oxide, titanium oxide, zirconium oxide, zinc oxide, tungsten oxide, tantalum oxide, or a combination thereof, and can be deposited by physical vapor deposition, chemical vapor deposition, atomic layer deposition or sol Gel process formation.

The above embodiments are only used to illustrate the present invention, but not to limit the present invention. Although the present invention has been described in detail with reference to the embodiments, those skilled in the art should understand that various combinations, modifications or equivalent replacements of the technical solutions of the present invention do not depart from the spirit and scope of the technical solutions of the present invention, and all should cover Within the scope of the claims of the present invention.

Claims (4)

1. A 1T1R array based on transparent RRAM gate-controlled thin-film transistors, characterized in that, the 1T1R array includes a logic circuit, a signal input circuit, a signal output circuit, and a power supply Vdd; wherein the logic circuit includes a 1T1R unit, a first transistor ; The 1T1R unit includes a resistance variable resistor and a second transistor; The second transistor is an NMOS transistor or a PMOS transistor; when the second transistor is an NMOS transistor, the first transistor is a PMOS transistor, and the connection of the 1T1R array is: one end of the resistance variable resistor is connected to the signal input circuit , the other end is connected to the gate of the second transistor, the source of the second transistor is grounded, its drain is connected to the signal output circuit and the drain of the first transistor, and the gate of the first transistor The pole is grounded, and its source is connected to the power supply Vdd; When the second transistor is a PMOS transistor, the first transistor is an NMOS transistor, and the connection of the 1T1R array is: one end of the resistance variable resistor is connected to the signal input circuit, and the other end is connected to the gate of the second transistor , the source of the second transistor is connected to the power supply Vdd, its drain is connected to the signal output circuit and the drain of the first transistor, the gate of the first transistor is connected to the power supply Vdd, and its drain is connected to the signal output circuit and the drain of the first transistor. Source ground. 2 . The 1T1R array according to claim 1 , wherein there is at least one 1T1R unit, and when there are more than one 1T1R unit, the 1T1R units are connected in parallel. 3. a preparation method based on the 1T1R array of the transparent RRAM gate-controlled thin film transistor according to claim 1, is characterized in that, comprises the following steps: S1, making a logic circuit, specifically: preparing a substrate for the second transistor; forming a gate on the substrate; generating a resistive variable resistor at the gate; forming an insulating layer on the gate; generating an electrode layer on the resistive variable resistor; forming a remainder of the second transistor cell on the substrate; preparing the gate, source and drain of the first transistor; S2. Prepare a signal input circuit and a signal output circuit; S3. Correspondingly connecting the signal input circuit and the signal output circuit to the logic circuit respectively. 4. The method according to claim 3, characterized in that, in the step S1, generating the rest of the second transistor unit on the substrate is specifically: forming a channel layer on the insulating layer; A source and a drain are respectively formed in the channel layer.