CN103913915B - A kind of array base palte, display floater and display device - Google Patents

Abstract

The invention discloses an array substrate, a display panel and a display device, which can realize the purpose of reducing the peak power during grid scanning without adding driving chips and complicated wiring. The array substrate provides multiple first control circuits and multiple second control circuits; the gate drive circuit is electrically connected to the input terminals of each first control circuit and each second control circuit; all gate lines are divided into first gate line groups and the second gate line group, the output ends of each first control circuit are electrically connected to the gates of a row of TFTs through a gate line in the first gate line group, and the output ends of each second control circuit are respectively connected through the second gate line A gate line in the group is electrically connected to the gates of a row of TFTs; the gate drive circuit is used to alternately provide the first level signal and the second level signal for turning on the TFT synchronously with the frame, and is used to provide the first level signal and the second level signal for turning off the TFT. The third level signal; the first control circuit and the second control circuit respectively selectively pass the first level signal and the second level signal.

Description

Array substrate, display panel and display device

technical field

The present invention relates to the technical field of liquid crystal display, in particular to an array substrate, a display panel and a display device.

Background technique

When a liquid crystal display is performing grid scanning, it usually scans from one end to the other end sequentially. During this scanning process, the peak power is high, which tends to generate more heat and affect the life of the liquid crystal display.

In the prior art, the odd and even rows are usually separated and wired on the array substrate, and driver chips are added to realize the time-sharing scanning of the thin film transistors (Thin Film Transistor, TFT) in the odd and even rows, which can reduce the peak power and reduce the generation of heat. Extend the life of LCD monitors.

However, the time-division scanning adopted in the prior art needs to add more integrated circuit components (Integrate Circuit, IC) for driving because it is completed through odd-even line separation wiring. It can be seen that although the peak power during gate scanning is reduced to a certain extent, the hardware cost is greatly increased.

Contents of the invention

The object of the present invention is to provide an array substrate, a display panel and a display device, so as to achieve the purpose of reducing the peak power during gate scanning without providing more driving chips and complex wiring, thereby saving costs.

The purpose of the present invention is achieved through the following technical solutions:

An embodiment of the present invention provides an array substrate, including a pixel unit array composed of a plurality of pixel units, each of which includes a thin film transistor TFT, and also includes a gate drive circuit, a plurality of gate lines, a plurality of first control circuit and a plurality of second control circuits;

The gate drive circuit is electrically connected to the input terminals of each of the first control circuits and each of the second control circuits;

All the gate lines are divided into a first gate line group and a second gate line group, and the output terminals of each of the first control circuits are respectively connected by one of the gate lines in the first gate line group and the corresponding row. The gates of the TFTs are electrically connected, and the output terminals of each of the second control circuits are electrically connected to the gates of the corresponding row of TFTs through one of the gate lines in the second gate line group;

The gate drive circuit is used to alternately provide a first level signal and a second level signal to turn on the TFT synchronously with the frame alternately, and to provide a third level signal to turn off the TFT;

The first control circuit is configured to pass the first level signal and the third level signal;

The second control circuit is configured to pass the second level signal and the third level signal;

Wherein, the levels of the first level signal, the second level signal and the third level signal are not equal to each other.

In the embodiment of the present invention, the gate drive circuit alternately provides the first level signal and the second level signal to turn on the TFT synchronously with the frame, and the first control circuit and the second The control circuit selectively passes the first level signal and the second level signal respectively. When implementing gate scanning, within the same frame time, only the TFTs in odd rows or only even rows are turned on, thereby reducing the peak power during gate scanning.

Preferably, each of the gate lines in the first gate line group is an odd-numbered row of gate lines, and each of the gate lines in the second gate line group is an even-numbered row of gate lines; or,

Each of the gate lines in the first gate line group is an even-numbered row of gate lines, and each of the gate lines in the second gate line group is an odd-numbered row of gate lines.

Preferably, the gate drive circuit is specifically used for:

The first level signal and the third level signal are sequentially provided in odd frames, and the second level signal and the third level signal are sequentially provided in even frames; or,

The first level signal and the third level signal are sequentially provided in even frames, and the second level signal and the third level signal are sequentially provided in odd frames.

Preferably, the first control circuit includes a first piezoresistor, a second piezoresistor, a third piezoresistor and a first storage capacitor; the first end of the first piezoresistor serves as the first The input end of the control circuit; the second end of the first piezoresistor is electrically connected to the first end of the second piezoresistor and the first end of the third piezoresistor respectively; the second piezoresistor The second end of the sensitive resistor and the second end of the third piezoresistor are both electrically connected to the first end of the first storage capacitor and used as the output end of the first control circuit; the first storage capacitor The second end of the ground;

The second control circuit includes the third varistor, the fourth varistor and the second storage capacitor; the first end of the third varistor is electrically connected to the first end of the fourth varistor As the input end of the second control circuit; the second end of the third varistor and the second end of the fourth varistor are both electrically connected to the first end of the second storage capacitor and used as the The output end of the second control circuit; the second end of the second storage capacitor is grounded.

Preferably, the level of the first level signal is lower than that of the second level signal, and the level of the third level signal is lower than that of the first level signal.

Preferably, the level of the first level signal is lower than that of the second level signal, and the level of the third level signal is lower than that of the first level signal.

Preferably, the first piezoresistor is used to pass the input signal whose level is lower than the second level signal, and prevent the input signal whose level is higher than or equal to the second level signal from passing through;

The second varistor is used to pass an input signal whose level is higher than or equal to the first level signal;

The third varistor is used to pass an input signal whose level is lower than or equal to the third level signal;

The fourth piezoresistor is used to pass an input signal whose level is higher than or equal to the second level signal.

Preferably, the first piezoresistor is specifically used to allow the first level signal and the third level signal to pass through, and prevent the second level signal from passing through;

The second piezoresistor is specifically used to allow the first level signal to pass through and prevent the third level signal from passing through;

The third varistor is specifically configured to allow the third level signal to pass through, and prevent the first level signal and the second level signal from passing through;

The fourth piezoresistor is specifically used to allow the second level signal to pass through, and prevent the first level signal and the third level signal from passing through.

The beneficial effects of the embodiments of the present invention are as follows: the gate drive circuit alternately provides the first level signal and the second level signal to turn on the TFT synchronously with the frame alternately, the first control circuit and the The second control circuit selectively passes the first level signal and the second level signal respectively. When implementing gate scanning, within the same frame time, only the TFTs in odd rows or only even rows are turned on, thereby reducing the peak power during gate scanning. The purpose of reducing the peak power during gate scanning is achieved without providing more driver chips and complex wiring, thereby saving hardware costs.

An embodiment of the present invention also provides a display panel, including the array substrate provided in the above embodiment.

The beneficial effects of the embodiments of the present invention are as follows: the gate drive circuit of the array substrate alternately provides the first level signal and the second level signal to turn on the TFT synchronously with the frame, and the first control The circuit and the second control circuit selectively pass the first level signal and the second level signal respectively. When gate scanning is implemented, only odd-numbered or even-numbered TFTs are turned on within the same frame time, thereby reducing peak power during gate scanning. The purpose of reducing the peak power during gate scanning is achieved without providing more driver chips and complex wiring, thereby saving hardware costs.

An embodiment of the present invention also provides a display device, including the display panel provided in the above embodiment.

The beneficial effects of the embodiments of the present invention are as follows: the gate drive circuit of the array substrate alternately provides the first level signal and the second level signal to turn on the TFT synchronously with the frame , the first control circuit and the second control circuit selectively pass the first level signal and the second level signal respectively. When implementing gate scanning, within the same frame time, only the TFTs in odd rows or only even rows are turned on, thereby reducing the peak power during gate scanning. The purpose of reducing the peak power during gate scanning is achieved without providing more driver chips and complex wiring, thereby saving hardware costs.

Description of drawings

FIG. 1 is a schematic diagram of an array substrate provided by an embodiment of the present invention;

FIG. 2 is a schematic diagram of a first control circuit provided by an embodiment of the present invention;

FIG. 3 is a schematic diagram of a second control circuit provided by an embodiment of the present invention;

FIG. 4 is a schematic diagram of input signals at the input terminals of the first control circuit and the second control circuit according to an embodiment of the present invention.

detailed description

The implementation process of the embodiment of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention. Apparently, the described embodiments are only some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

Referring to FIG. 1, an embodiment of the present invention provides an array substrate, including an array of pixel units 104 composed of a plurality of pixel units 104, each pixel unit 104 includes a thin film transistor TFT 105, and also includes a gate drive circuit 103; Lines, denoted as G1 to G2n, n is a natural number; a plurality of first control circuits 101 and a plurality of second control circuits 102 .

The gate drive circuit 103 is electrically connected to the input terminals of each first control circuit 101 and each second control circuit 102 .

All the gate lines are divided into a first gate line group and a second gate line group, and each gate line in the first gate line group is arranged alternately with the gate lines in the second gate line group.

The output ends of each first control circuit 101 are electrically connected to the gates of a corresponding row of TFTs 105 through a gate line in the first gate line group, and the output ends of each second control circuit 102 are respectively connected through the gate lines in the second gate line group. A gate line is electrically connected to the gates of a corresponding row of TFTs 105 .

The gate driving circuit 103 is used for alternately providing a first level signal and a second level signal for turning on the TFT 105 synchronously with frame alternation, and for providing a third level signal for turning off the TFT 105 .

The first control circuit 101 is used to pass the first level signal and the third level signal; the second control circuit 102 is used to pass the second level signal and the third level signal; wherein, the first level The levels of the signal, the second level signal and the third level signal are not equal to each other.

In the embodiment of the present invention, the gate drive circuit 103 alternately provides the first level signal and the second level signal to turn on the TFT 105 synchronously with the frame alternately, and the first control circuit 101 and the second control circuit 102 control the first level signal respectively. The signal and the second level signal are selectively passed. When implementing gate scanning, only odd-numbered rows of TFTs 105 or only even-numbered rows of TFTs 105 are turned on within the same frame time, thereby reducing peak power during gate scanning.

Preferably, each grid line in the first grid line group is an odd-numbered row grid line, and each grid line in the second grid line group is an even-numbered row grid line; or,

Each gate line in the first gate line group is an even-numbered row gate line, and each gate line in the second gate line group is an odd-numbered row gate line.

For example, the gate line G1, the gate line G3 ..... the gate line G2n-3 and the gate line G2n-3 are used as the first gate line group, and the gate line G2, the gate line G4 ..... the gate line G2n- 2 and the gate line G2n as the second gate line group, specifically refer to FIG. 1 . Alternatively, the gate line G2, the gate line G4 ..... the gate line G2n-2 and the gate line G2n are used as the first gate line group, and the gate line G1, the gate line G3 ..... the gate line G2n-3 and The gate line G2n-3 is used as the second gate line group, and this method is similar to that shown in FIG. 1 , and will not be repeated here.

Preferably, the gate drive circuit 103 is specifically configured to: sequentially provide the first level signal and the third level signal in odd frames, and sequentially provide the second level signal and the third level signal in even frames; or, in The first level signal and the third level signal are sequentially provided in the even frames, and the second level signal and the third level signal are sequentially provided in the odd frames. In this embodiment, signals of different levels may be provided in different frames as required. It should be noted that since both the first control circuit 101 and the second control circuit 102 can pass the third-level signal, therefore, each row of TFTs can be turned off regardless of the odd-numbered frame or the even-numbered frame.

For example: the gate drive circuit 103 provides the first level signal to the input terminal of the first control circuit 101 and the input terminal of the second control circuit 102 in odd frames, and provides the first level signal to the input terminal of the first control circuit 101 and the input terminal of the second control circuit 102 in even frames. The control circuit 102 provides a second level signal. For the first level signal and the third level signal provided by the gate drive circuit 103 in odd frames, the first control circuit 101 makes them pass; but for the second level signal and the third level signal provided by the gate drive circuit 103 in even frames For the third-level signal, since the first control circuit 101 prevents the second-level signal from passing through, in even frames, the first control circuit 101 can only pass the third-level signal. Similarly, for the first level signal and the third level signal provided by the gate drive circuit 103 in odd frames, since the second control circuit 102 will prevent the first level signal from passing through, in odd frames, the second control circuit 102 can only pass the third level signal; for the second level signal and the third level signal provided by the gate driving circuit 103 in even frames, the second control circuit 102 allows it to pass. Therefore, in this embodiment, only odd-numbered TFTs 105 are turned on in odd-numbered frames, and only even-numbered TFTs 105 are turned on in even-numbered frames. In addition, usually every time a row of TFTs 105 is driven, a third level signal is provided to the row of TFTs 105 to turn them off. This embodiment is only for illustration, and the present invention is not limited thereto.

In order to describe the array substrate provided in this embodiment in more detail, a more specific first control circuit 101 and a second control circuit 102 are provided, see FIG. 2 and FIG. 3 respectively.

As shown in Figure 2, the first control circuit 101 includes a first piezoresistor RC1, a second piezoresistor RC2, a third piezoresistor RC3 and a first storage capacitor C1; the first end of the first piezoresistor RC1 As the input terminal IN1 of the first control circuit 101; the second end of the first piezoresistor RC1 is electrically connected with the first end of the second piezoresistor RC2 and the first end of the third piezoresistor RC3 respectively; Both the second end of the sensitive resistor RC2 and the second end of the third piezoresistor RC3 are electrically connected to the first end of the first storage capacitor C1, and serve as the output end OUT1 of the first control circuit 101, and the output end OUT1 is connected to the first end of the first control circuit 101. An odd row of gate lines is electrically connected; the second end of the first storage capacitor C1 is grounded to the power supply GND.

As shown in FIG. 3, the second control circuit 102 includes a third varistor RC3, a fourth varistor RC4 and a second storage capacitor C2; the first end of the third varistor RC3 and the fourth varistor RC4 The first end of the first end is electrically connected as the input end IN2 of the second control circuit 102; the second end of the third piezoresistor RC3 and the second end of the fourth piezoresistor RC4 are electrically connected to the first end of the second storage capacitor C2 It is connected and used as the output terminal OUT2 of the second control circuit 102; the second terminal of the second storage capacitor C2 is grounded to the power supply GND.

For the turn-on level of the TFT 105, within a safe level range higher than the turn-on level, it is stipulated that the odd-numbered row TFT 105 is turned on with the first level signal, and the even-numbered row TFT 105 is turned on with the second level signal; or, The two-level signal turns on the odd-numbered TFTs 105, and the first-level signal turns on the even-numbered TFTs 105. The effect of each element of the first control circuit 101 and the second control circuit 102 is as follows:

The first piezoresistor RC1 is used to allow the input signal whose level is lower than the second level signal VG2 to pass through, and prevent the input signal whose level is higher than or equal to the second level signal VG2 to pass through. It can be seen that the first level signal VG1 and the third level signal VGL can pass through, but the second level signal VG2 cannot pass through.

The second varistor RC2 is used to pass the input signal whose level is higher than or equal to the first level signal VG1 . Since the second piezoresistor RC2 is selected on the basis of the output of the first piezoresistor RC1, and only the first level signal VG1 and the third level signal VGL pass through the first piezoresistor RC1, so the second The two piezoresistors RC2 select the first-level signal VG1 and the third-level signal VGL, and allow the first-level signal VG1 to pass through, while preventing the third-level signal VGL from passing through.

The third varistor RC3 is used for passing the input signal whose level is lower than or equal to the third level signal.

When the third piezoresistor RC3 is applied to the first control circuit 101, since the third piezoresistor RC3 is selected on the basis of the output of the first piezoresistor RC1, what passes through the first piezoresistor RC1 can only be The first level signal VG1 and the third level signal VGL, so the third varistor RC3 selects the first level signal VG1 and the third level signal VGL, and makes the third level signal VGL pass, so that The first level signal VG1 cannot pass through.

When the third piezoresistor RC3 is applied to the second control circuit 102 , the third piezoresistor RC3 allows the third level signal VGL to pass, but prevents the first level signal VG1 and the second level signal VG2 from passing through.

The fourth varistor RC4 is used to pass the input signal whose level is higher than or equal to the second level signal VG2. That is, the second-level signal VG2 is passed, while the first-level signal VG1 and the third-level signal VGL are not allowed to pass.

For example: based on the schematic diagrams of the first control circuit 101 and the second control circuit 102 shown in FIGS. If the TFT 105 in the odd-numbered and even-numbered rows is not scanned at the same time, the level of the first level signal can be lower than that of the second level signal, and the level of the third level signal can be lower than that of the first level signal. flat.

Referring to FIG. 4 , a schematic diagram of signals input from the input terminals of the first control circuit 101 and the second control circuit 102 . Wherein, the gate driving circuit 103 provides input signals S1 , S2 . . . S(2n−1), S2n to the first control circuit 101 and the second control circuit 102 . It should be noted that within one frame time, only the first level signal VG1 and the third level signal VGL are provided to the input terminals of the first control circuit 101 and the second control circuit 102; or, only the first control circuit The input terminals of 101 and the second control circuit 102 provide the second level signal VG1 and the third level signal VGL, and the first control circuit 101 and the second control circuit 102 need to select the input level signal before outputting. The level of the third level signal VGL shown in FIG. 4 is lower than the 0 level indicated by the dotted line.

It can be obtained from the above that the specific functions of the components of the first control circuit 101 and the second control circuit 102 are as follows:

The first varistor RC1 is specifically used to allow the first level signal and the third level signal to pass through, and prevent the second level signal from passing through.

The second piezoresistor RC2 is specifically used to allow the first level signal to pass through and prevent the third level signal from passing through.

The third varistor RC3 is specifically used to pass the third level signal and prevent the first level signal and the second level signal from passing through.

The fourth varistor RC4 is specifically used to allow the second level signal to pass through, and prevent the first level signal and the third level signal from passing through.

It can be seen from the above that, for the first control circuit 101 and the second control circuit 102, within one frame time, no matter whether the gate drive circuit provides the first level signal VG1 or the second level signal VG2, only the odd-numbered lines must be turned on. TFT 105 or TFT 105 of even rows.

As for the turn-off signal VGL shown in FIG. 4 , which is provided to the scanned TFTs, the specific scanning process can be implemented according to the embodiment of the present invention, which will not be repeated here.

The beneficial effects of the embodiments of the present invention are as follows: the gate drive circuit alternately provides the first level signal and the second level signal to turn on the TFT synchronously with the frame alternately, the first control circuit and the The second control circuit selectively passes the first level signal and the second level signal respectively. When implementing gate scanning, within the same frame time, only the TFTs in odd rows or only even rows are turned on, thereby reducing the peak power during gate scanning. The purpose of reducing the peak power during gate scanning is achieved without providing more driver chips and complex wiring, thereby saving hardware costs.

An embodiment of the present invention also provides a display panel, including the array substrate provided in the above embodiment.

The beneficial effects of the embodiments of the present invention are as follows: the gate drive circuit alternately provides the first level signal and the second level signal to turn on the TFT synchronously with the frame alternately, the first control circuit and the The second control circuit selectively passes the first level signal and the second level signal respectively. When implementing gate scanning, within the same frame time, only the TFTs in odd rows or only even rows are turned on, thereby reducing the peak power during gate scanning. The purpose of reducing the peak power during gate scanning is achieved without providing more driver chips and complex wiring, thereby saving hardware costs.

Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and equivalent technologies thereof, the present invention also intends to include these modifications and variations.

Claims (9)

1. An array substrate comprises a pixel unit array consisting of a plurality of pixel units, wherein each pixel unit comprises a Thin Film Transistor (TFT), and the array substrate is characterized by further comprising a grid driving circuit, a plurality of grid lines, a plurality of first control circuits and a plurality of second control circuits;

the grid driving circuit is electrically connected with the input ends of the first control circuits and the second control circuits;

all the grid lines are divided into a first grid line group and a second grid line group, the output end of each first control circuit is electrically connected with the grid electrode of the corresponding row of the TFT through one grid line in the first grid line group, and the output end of each second control circuit is electrically connected with the grid electrode of the corresponding row of the TFT through one grid line in the second grid line group;

the gate driving circuit is used for alternately providing a first level signal and a second level signal for turning on the TFT and providing a third level signal for turning off the TFT synchronously with the frame alternation;

the first control circuit is used for enabling the first level signal and the third level signal to pass through;

the second control circuit is used for enabling the second level signal and the third level signal to pass through;

wherein levels of the first level signal, the second level signal, and the third level signal are different from each other.

2. The array substrate of claim 1, wherein each gate line in the first gate line group is an odd number of rows of gate lines, and each gate line in the second gate line group is an even number of rows of gate lines; or,

each gate line in the first gate line group is an even-numbered line, and each gate line in the second gate line group is an odd-numbered line.

3. The array substrate of claim 1, wherein the gate driver circuit is specifically configured to:

providing the first level signal and the third level signal in sequence in odd frames, and providing the second level signal and the third level signal in sequence in even frames; or,

and sequentially providing the first level signal and the third level signal in an even frame, and sequentially providing the second level signal and the third level signal in an odd frame.

4. The array substrate of any one of claims 1 to 3, wherein:

the first control circuit comprises a first voltage dependent resistor, a second voltage dependent resistor, a third voltage dependent resistor and a first storage capacitor; the first end of the first piezoresistor is used as the input end of the first control circuit; the second end of the first piezoresistor is electrically connected with the first end of the second piezoresistor and the first end of the third piezoresistor respectively; the second end of the second piezoresistor and the second end of the third piezoresistor are both electrically connected with the first end of the first storage capacitor and serve as the output end of the first control circuit; the second end of the first storage capacitor is grounded;

the second control circuit comprises the third piezoresistor, a fourth piezoresistor and a second storage capacitor; the first end of the third piezoresistor and the first end of the fourth piezoresistor are electrically connected as the input end of the second control circuit; the second end of the third piezoresistor and the second end of the fourth piezoresistor are both electrically connected with the first end of the second storage capacitor and serve as the output end of the second control circuit; the second end of the second storage capacitor is grounded.

5. The array substrate of claim 4, wherein a level of the first level signal is lower than a level of the second level signal, and a level of the third level signal is lower than a level of the first level signal.

6. The array substrate of claim 5, wherein:

the first piezoresistor is used for enabling an input signal with the level lower than the second level signal to pass through and preventing an input signal with the level higher than or equal to the second level signal from passing through;

the second piezoresistor is used for enabling an input signal with the level higher than or equal to the first level signal to pass through;

the third piezoresistor is used for enabling an input signal with the level lower than or equal to the third level signal to pass through;

the fourth voltage dependent resistor is used for enabling an input signal with the level higher than or equal to the second level signal to pass through.

7. The array substrate of claim 6, wherein:

the first piezoresistor is specifically used for enabling the first level signal and the third level signal to pass through and preventing the second level signal from passing through;

the second piezoresistor is specifically used for enabling the first level signal to pass through and preventing the third level signal from passing through;

the third piezoresistor is specifically used for enabling the third level signal to pass through and preventing the first level signal and the second level signal from passing through;

the fourth piezoresistor is specifically used for enabling the second level signal to pass through and preventing the first level signal and the third level signal from passing through.

8. A display panel comprising the array substrate according to any one of claims 1 to 7.

9. A display device characterized by comprising the display panel according to claim 8.