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CN103913471B - The method held and plate buries and holds layer contraposition is buried in a kind of inspection - Google Patents

The method held and plate buries and holds layer contraposition is buried in a kind of inspection Download PDF

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CN103913471B
CN103913471B CN201210593685.6A CN201210593685A CN103913471B CN 103913471 B CN103913471 B CN 103913471B CN 201210593685 A CN201210593685 A CN 201210593685A CN 103913471 B CN103913471 B CN 103913471B
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layer
pad
buried
out tray
minimum
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CN103913471A (en
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杨继刚
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Shennan Circuit Co Ltd
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Abstract

本发明属于印刷电路板制造领域,尤其涉及一种检验埋容板埋容层对位的方法。其包括以下步骤:找出每层埋容层的最小隔离盘或焊盘尺寸,于每层埋容层四角落的空白位置,分别制作该层最小隔离盘或焊盘;各所述埋容层上制作的最小隔离盘或焊盘,于水平方向上依次间隔错开一个设定的距离;当所述各埋容层与内层芯板压合形成多层线路板后,按照所述设定的距离,进行钻孔,形成多个贯穿最小隔离盘或焊盘的通孔;将完成钻孔后的所述线路板,在X光机器下检查各所述埋容层和所述内层芯板上的最小隔离盘或焊盘的图形,若所述最小隔离盘或焊盘的图形没有破盘,则该层没有破盘。如此,可直接判定是否破盘以及具体破盘于哪一层。

The invention belongs to the field of printed circuit board manufacturing, and in particular relates to a method for checking the alignment of a buried capacitance layer of a buried capacitance board. It includes the following steps: find out the minimum isolation pad or pad size of each buried capacitance layer, and make the minimum isolation pad or pad of the layer at the blank positions at the four corners of each buried capacitance layer; each buried capacitance layer The minimum isolation pads or pads made on the horizontal direction are sequentially staggered by a set distance; when the embedding layers and the inner core board are pressed together to form a multi-layer circuit board, according to the set distance, drill holes to form a plurality of through-holes that run through the smallest isolation pad or pad; check each of the embedding layers and the inner core board under an X-ray machine with the circuit board after the drilling is completed The pattern of the minimum isolation pad or pad on the layer, if the pattern of the minimum isolation pad or pad is not damaged, then the layer has no damage. In this way, it is possible to directly determine whether the market is broken or not and which floor it is.

Description

一种检验埋容板上埋容层对位的方法A method for checking the alignment of buried capacitor layers on buried capacitor plates

技术领域technical field

本发明属于印刷电路板制造领域,尤其涉及一种检验埋容板上埋容层对位的方法。The invention belongs to the field of printed circuit board manufacturing, and in particular relates to a method for checking the alignment of a buried capacitance layer on a buried capacitance board.

背景技术Background technique

目前,常规PCB在边框上设置用于确认错位的方块铜点,由于每层的方块铜点尺寸大小一样,即便发生错位时,也不能确认具体是哪一层发生了破盘,需要签废板件去板内确认,增加了PCB板的报废。At present, the conventional PCB sets square copper points on the frame to confirm the misalignment. Since the size of the square copper points on each layer is the same, even if the misalignment occurs, it is impossible to confirm which layer is broken. It is necessary to sign the scrap board The parts are confirmed in the board, which increases the scrapping of the PCB board.

尤其在埋容材料非常薄时,在PCB加工过程中容易错位,X光机检查时出现每层叠加图形移位阴影,钻孔后无法直观判断是否破盘,需要借助取切片在显微镜下观察,需要耗时一个小时左右。Especially when the embedding material is very thin, it is easy to be misplaced during the PCB processing process. When the X-ray machine checks, there will be a shift shadow of each layer of superimposed graphics. After drilling, it is impossible to visually judge whether the disk is broken. It needs to be observed under a microscope by taking a slice. It takes about an hour.

综上所述,现有的埋容层对位检测方法,不易观察和判定破盘情况,且报废率高。To sum up, the existing buried layer alignment detection method is not easy to observe and judge the failure, and the scrap rate is high.

发明内容Contents of the invention

本发明的目的在于提供一种检验埋容板埋容层对位的方法,旨在解决现有技术中不易观察和判定多层线路板的破盘情况,且多层线路板检测报废率高的问题。The purpose of the present invention is to provide a method for inspecting the alignment of the embedding layer of the embedded capacitor board, aiming at solving the problem that it is difficult to observe and judge the failure of the multilayer circuit board in the prior art, and the detection and scrapping rate of the multilayer circuit board is high question.

本发明是这样实现的,一种检验埋容板埋容层对位的方法,包括以下步骤:The present invention is achieved in this way, a method for checking the alignment of the buried capacity layer of the buried capacity plate, comprising the following steps:

找出每层埋容层的最小隔离盘或焊盘尺寸;Find the minimum isolation pad or pad size for each buried capacitance layer;

于每层埋容层四角落的空白位置,分别制作该层的最小隔离盘或焊盘;In the blank positions at the four corners of each buried capacitor layer, respectively make the smallest isolation pad or pad of the layer;

各所述埋容层上制作的最小隔离盘或焊盘的图形,于水平方向上依次间隔错开一个设定的距离;The graphics of the minimum isolation pads or pads fabricated on each of the embedding layers are sequentially staggered by a set distance in the horizontal direction;

当所述各埋容层与内层芯板压合形成多层线路板后,按照所述设定的距离,进行钻孔,形成多个通孔,所述通孔分别贯穿所述各埋容层上和所述内层芯板上的最小隔离盘或焊盘;After the embedding layers are pressed together with the inner core board to form a multi-layer circuit board, holes are drilled according to the set distance to form a plurality of through holes, and the through holes respectively pass through the embedding capacitors. Minimum isolated pads or pads on layers and on said inner core board;

将完成钻孔后的所述线路板,在X光机器下检查各所述埋容层和所述内层芯板上的最小隔离盘或焊盘的图形,若所述最小隔离盘或焊盘的图形没有破盘,则该层没有破盘。With the circuit board after the drilling is completed, check the patterns of the minimum isolation pads or pads on each of the embedding layers and the inner core board under an X-ray machine, if the minimum isolation pads or pads If there is no broken market in the graph, then the layer has no broken market.

进一步地,所述最小隔离盘或焊盘的图形为一正方形,所述正方形的四角处倒圆角,并于所述正方形的中心设有一圆,所述圆的直径作为最小隔离盘或焊盘的直径。Further, the pattern of the minimum isolation pad or pad is a square, the four corners of the square are rounded, and a circle is set in the center of the square, and the diameter of the circle is used as the minimum isolation pad or pad diameter of.

进一步地,所述正方形的边长为5mm,所述正方形的四角处倒半径为1mm的圆角。Further, the side length of the square is 5 mm, and the four corners of the square are rounded with a radius of 1 mm.

进一步地,所述设定的距离大于2mm。Further, the set distance is greater than 2mm.

进一步地,于所述埋容层上,所述最小隔离盘或焊盘的图形中仅圆形部分未覆盖有铜金属;于所述内层芯板上,所述最小隔离盘或焊盘的图形中仅圆形部分覆盖有铜金属。Further, on the buried capacity layer, only the circular part of the pattern of the smallest isolation pad or pad is not covered with copper metal; on the inner core board, the smallest isolation pad or pad Only the circular portion of the graphic is covered with copper metal.

与现有技术相比,本发明中的在各所述埋容层的四角空白位置设置最小焊盘或隔离盘图形,所述各埋容层上的最小焊盘或隔离盘相互间隔错开一个设定的距离,如此,在所述各埋容层于所述内层芯板压合形成多层线路板后,按照预先设定的距离钻设多个贯穿所述各埋容层和所述内层芯板的通孔,再将钻设有通孔的多层线路板于X光机器下检查各所述埋容层和所述内层芯板上的最小隔离盘或焊盘的图形是否破盘,若是破盘,即表示所述破盘的图形所在的埋容层或内层芯板发生了偏移。整个过程中,可以很直观快捷的判定压合后的多层线路板是否破盘,以及具体是哪一层发生了破盘,而不需要将多层线路板签废板确认,避免了优质的多层线路板被检测报废,大大提高了检测效率。Compared with the prior art, in the present invention, minimum pads or isolation pad patterns are set at the four corners of each buried capacitance layer, and the minimum pads or isolation pads on each of the buried capacitance layers are staggered from each other by a design. In this way, after the embedding layers are laminated on the inner core board to form a multilayer circuit board, a plurality of embedding layers and the inner layer are drilled according to a preset distance. The through hole of the core board, and then drill the multilayer circuit board with the through hole under the X-ray machine to check whether the patterns of the minimum isolation pads or pads on each of the embedded layers and the inner core board are broken. If the disk is broken, it means that the embedding layer or inner core board where the pattern of the broken disk is located has shifted. During the whole process, it is possible to intuitively and quickly determine whether the laminated multilayer circuit board is broken, and which layer is broken, without the need to sign the waste board for confirmation, avoiding high-quality The multi-layer circuit board is scrapped by detection, which greatly improves the detection efficiency.

附图说明Description of drawings

图1是本发明实施例中埋容层上最小焊盘或隔离盘图形分布于四角空白位置的示意图;Figure 1 is a schematic diagram of the distribution of the smallest pads or isolation pads on the embedding layer in the blank positions of the four corners in the embodiment of the present invention;

图2是本发明实施例中埋容层上最小焊盘或隔离盘图形分布于四角空白位置的侧视示意图;Fig. 2 is a schematic side view of the distribution of the minimum pads or isolation pads on the embedding layer in the blank positions of the four corners in the embodiment of the present invention;

图3是本发明实施例中多个埋容层钻孔后的示意图;Fig. 3 is a schematic diagram after drilling a plurality of buried capacity layers in an embodiment of the present invention;

图4是本发明实施例中最小焊盘或隔离盘的图形示意图。FIG. 4 is a schematic diagram of the smallest pad or isolation pad in an embodiment of the present invention.

标记说明:Mark Description:

1第一埋容层的第一面11第一焊盘1 the first surface of the first buried capacity layer 11 the first pad

2第一埋容层的第二面21第二焊盘2 The second surface of the first buried capacity layer 21 The second pad

3第二埋容层的第一面31第三焊盘3 The first surface of the second buried capacity layer 31 The third pad

4第二埋容层的第二面41第四焊盘4 The second surface 41 of the second buried capacity layer The fourth pad

5内层芯板51第五焊盘5 Inner layer core board 51 fifth welding pad

6通孔71圆形6 through holes 71 round

8最小焊盘或隔离盘的分布区72正方形8 minimum pad or isolation pad distribution area 72 square

9有效图形区D1边长9 The side length of effective graphics area D1

10空白位置R圆角半径10 blank position R fillet radius

具体实施方式detailed description

为了使本发明的目的、技术方案及优点更加清楚明白,以下结合附图及实施例,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

以下结合具体附图对本发明的实现进行详细的描述。The implementation of the present invention will be described in detail below in conjunction with specific drawings.

如图1~4所示,为本发明提供的一较佳实施例。As shown in Figures 1-4, it is a preferred embodiment provided by the present invention.

本发明中的检验埋容板埋容层对位的方法,所述埋容层的中间部分为有效图形区9,其周边为空白位置10,包括以下步骤:In the method for checking the alignment of the embedding layer of the embedding plate in the present invention, the middle part of the embedding layer is an effective pattern area 9, and its periphery is a blank position 10, comprising the following steps:

找出每层埋容层的最小隔离盘或焊盘尺寸;Find the minimum isolation pad or pad size for each buried capacitance layer;

于每层埋容层四角落的空白位置10,分别制作该层的最小隔离盘或焊盘;如图1所示,所述最小隔离盘或焊盘的分布区8位于所述空白位置10的四个角落处。At the blank positions 10 at the four corners of each layer of buried capacity layer, make the minimum isolation pad or pad of the layer respectively; as shown in Figure 1, the distribution area 8 of the minimum isolation pad or pad is located at the blank position 10 at the four corners.

参见图2所示,各所述埋容层上制作的最小隔离盘或焊盘,于水平方向上依次错开一个设定的距离;Referring to Fig. 2, the minimum isolation pads or pads made on each of the embedding layers are sequentially staggered by a set distance in the horizontal direction;

参见图3所示,当所述各埋容层与内层芯板5压合形成多层线路板后,按照所述设定的距离,进行钻孔,形成多个通孔6,所述通孔6分别贯穿所述各埋容层上和所述内层芯板5上的最小隔离盘或焊盘;Referring to Fig. 3, after the embedding layers are pressed together with the inner core board 5 to form a multilayer circuit board, holes are drilled according to the set distance to form a plurality of through holes 6, and the through holes 6 are formed. The holes 6 respectively pass through the minimum isolation pads or pads on the buried capacitance layers and on the inner core board 5;

将完成钻孔后的所述线路板,在X光机器下检查各所述埋容层和所述内层芯板5上的最小隔离盘或焊盘的图形,若所述最小隔离盘或焊盘的图形没有破盘,则该层没有破盘。The printed circuit board after the drilling is completed, check each of the embedding layers and the pattern of the minimum isolation pads or pads on the inner core board 5 under the X-ray machine, if the minimum isolation pads or solder pads If the graph of the market is not broken, then the layer is not broken.

与现有技术相比,本发明中的在各所述埋容层的四角空白位置10设置最小隔离环或焊盘图形,所述各埋容层上的最小隔离环或焊盘相互间隔错开一个设定的距离,如此,在所述各埋容层与所述内层芯板5压合形成多层线路板后,按照预先设定的距离钻设多个贯穿所述各埋容层和所述内层芯板5的通孔6,再将钻设有通孔6的多层线路板于X光机器下检查各所述埋容层和所述内层芯板5上的最小隔离盘或焊盘的图形是否破盘,若是破盘,即表示所述破盘的图形所在的埋容层或内层芯板5发生了偏移。整个过程中,可以很直观快捷的判定压合后的多层线路板是否破盘,以及具体是哪一层发生了破盘,而不需要将多层线路板签废板确认,避免了优质的多层线路板被检测报废,大大提供了检测效率。Compared with the prior art, in the present invention, minimum isolation rings or pad patterns are set at the four corner blank positions 10 of each buried capacitance layer, and the minimum isolation rings or pads on each buried capacitance layer are staggered from each other by one set distance, so that after the embedding layers and the inner core board 5 are pressed together to form a multilayer circuit board, a plurality of embedding layers and the embedding layers are drilled according to a preset distance. The through hole 6 of the inner layer core board 5, and then the multi-layer circuit board drilled with the through hole 6 is checked under the X-ray machine for each of the buried capacity layers and the minimum isolation disk or disk on the inner layer core board 5 Whether the pattern of the pad is broken, if it is broken, it means that the buried layer or the inner core board 5 where the pattern of the broken disk is located has shifted. During the whole process, it is possible to intuitively and quickly determine whether the laminated multilayer circuit board is broken, and which layer is broken, without the need to sign the waste board for confirmation, avoiding high-quality The multi-layer circuit board is detected and scrapped, which greatly improves the detection efficiency.

具体地,本实施例中,设有两层埋容层,每层埋容层具有两面。如图2所示,由上往下,依次为第一埋容层的第一面1、第一埋容层的第二面2、第二埋容层的第一面3和第二埋容层的第二面4,以及内层芯板5。所述第一埋容层的第一面1、第一埋容层的第二面2、第二埋容层的第一面3和第二埋容层的第二面4以及内层芯板5上分别设有第一焊盘、第二焊盘、第三焊盘、第四焊盘和第五焊盘。Specifically, in this embodiment, two embedding layers are provided, and each embedding layer has two sides. As shown in Figure 2, from top to bottom, the first surface 1 of the first buried capacity layer, the second surface 2 of the first buried capacity layer, the first surface 3 of the second buried capacity layer, and the second buried capacity layer The second face 4 of the layer, and the inner core 5. The first surface 1 of the first buried volume layer, the second surface 2 of the first buried volume layer, the first surface 3 of the second buried volume layer, the second surface 4 of the second buried volume layer, and the inner core board 5 are respectively provided with a first pad, a second pad, a third pad, a fourth pad and a fifth pad.

进一步地,所述最小隔离盘或焊盘的图形为一正方形72,所述正方形的四角处倒圆角,并于所述正方形72的中心设有一圆,所述圆的直径作为最小焊盘或隔离盘的直径。通过这种结构的设置,在发生破盘时,利于观察,可直观的判定具体哪一层发生了破盘。Further, the pattern of the smallest isolating pad or pad is a square 72, the four corners of the square are rounded, and a circle is set at the center of the square 72, and the diameter of the circle serves as the smallest pad or pad. The diameter of the isolation disc. Through the setting of this structure, when a break occurs, it is convenient for observation, and it can be intuitively judged which layer has broken.

优选地,参见图4所示,所述正方形72的边长D1为5mm,所述正方形72的四角处倒半径R为1mm的圆角。如此,细小的设计,更便于生产加工。当然,根据具体的多层板的精度要求,可以合理设置该尺寸。当然,更加不同埋容层的需要,可合理设置所述圆的直径,即设置最小最小隔离盘或焊盘的尺寸。Preferably, as shown in FIG. 4 , the side length D1 of the square 72 is 5 mm, and the four corners of the square 72 are rounded with a radius R of 1 mm. In this way, the small design is more convenient for production and processing. Of course, this size can be reasonably set according to the specific precision requirements of the multilayer board. Of course, depending on the needs of the buried capacity layer, the diameter of the circle can be reasonably set, that is, the size of the smallest isolation pad or pad can be set.

进一步地,所述设定的距离大于2mm。如此,可避免各层之间的最小隔离环或焊盘间的检测干涉。使破盘检测变得更加直观,可靠。Further, the set distance is greater than 2mm. In this way, minimal spacer rings between layers or detection interference between pads can be avoided. Make broken disk detection more intuitive and reliable.

进一步地,于所述埋容层上,所述最小隔离盘或焊盘的图形中仅圆形71部分未覆盖有铜金属做负性;于所述内层芯板5上,所述最小隔离盘或焊盘的图形中仅圆形71部分覆盖有铜金属。如此,可快速区分所述埋容层和非埋容层,便于判定破盘于具体发生于哪一层。Further, on the buried capacity layer, only the circular 71 part of the pattern of the minimum isolation pad or pad is not covered with copper metal as a negative; on the inner core board 5, the minimum isolation Only the circular 71 portion of the pattern of pads or pads is covered with copper metal. In this way, the buried capacity layer and the non-buried capacity layer can be quickly distinguished, and it is convenient to determine which layer the breach occurred in.

以上所述仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本发明的保护范围之内。The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention should be included in the protection of the present invention. within range.

Claims (5)

1. inspection is buried and is held the method that plate buries the contraposition of appearance layer, it is characterized in that, comprises the following steps:
Find out every layer and bury the minimum trap-out tray or pad size that hold layer;
Bury in every layer the blank position holding layer four corner, make minimum trap-out tray or the pad of this layer respectively;
Bury the minimum trap-out tray or pad that hold and layer makes described in each, in horizontal direction, stagger a distance set in interval successively;
When described respectively burying is held after layer and core material pressing form multilayer circuit board, according to the distance of described setting, hole, form multiple through hole, described through hole run through respectively described respectively bury on appearance layer with the minimum trap-out tray on described core material or pad;
To the described wiring board after boring be completed, check under X-ray machine device each described in bury the figure holding minimum trap-out tray on layer and described core material or pad, if the broken dish of the figure of described minimum trap-out tray or pad, then the broken dish of this layer.
2. a kind of inspection according to claim 1 is buried and is held the method that plate buries the contraposition of appearance layer, it is characterized in that: the figure of described minimum trap-out tray or pad is a square, described foursquare corner place rounding, and a circle is provided with in described foursquare center, described diameter of a circle is as minimum trap-out tray or pad diameter.
3. a kind of inspection according to claim 2 is buried and is held the method that plate buries the contraposition of appearance layer, and it is characterized in that: the described foursquare length of side is 5mm, described foursquare corner place reciprocal radius is the fillet of 1mm.
4. a kind of inspection according to claim 3 is buried and is held the method that plate buries the contraposition of appearance layer, it is characterized in that: the distance of described setting is greater than 2mm.
5. a kind of inspection according to claim 3 is buried and is held the method that plate buries the contraposition of appearance layer, it is characterized in that: hold on layer in described burying, in the figure of described minimum trap-out tray or pad, only circular portion is not coated with copper metal; On other core material, in the figure of described minimum trap-out tray or pad, only circular portion is coated with copper metal.
CN201210593685.6A 2012-12-31 2012-12-31 The method held and plate buries and holds layer contraposition is buried in a kind of inspection Expired - Fee Related CN103913471B (en)

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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114614231B (en) * 2020-12-09 2024-03-22 深南电路股份有限公司 Coupler and electronic equipment
CN112654141B (en) * 2020-12-25 2022-10-11 天津普林电路股份有限公司 Method for checking alignment of mechanical hole and inner layer pattern

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1681632A (en) * 2002-09-25 2005-10-12 松下电工株式会社 Method for producing laminated board and misregistration-preventing system for laminated board production
CN101212859A (en) * 2006-12-31 2008-07-02 比亚迪股份有限公司 Method for detecting inter-layer displacement of multi-layer flexible printed circuit board
CN101709948A (en) * 2009-12-23 2010-05-19 深南电路有限公司 Alignment detecting method of multilayer printed wiring board
CN102072716A (en) * 2010-12-21 2011-05-25 胜宏科技(惠州)有限公司 Method for detecting interlayer offset and drilling offset of multi-layer circuit board
CN201867378U (en) * 2010-10-26 2011-06-15 广州宏镓电子材料科技有限公司 Layer deviation inspection machine capable of being automatically started
CN201947553U (en) * 2010-06-24 2011-08-24 胜宏科技(惠州)有限公司 Supplementary structure for detecting layer to layer registration of PCB (printed circuit board)
CN102445140A (en) * 2011-09-21 2012-05-09 东莞生益电子有限公司 Test device and test method for multilayer circuit board alignment
CN102607368A (en) * 2012-03-20 2012-07-25 昆山鼎鑫电子有限公司 Laser drilling deviation inspection method for HDI (High Density Interconnection) plate
CN102729583A (en) * 2011-04-13 2012-10-17 竞陆电子(昆山)有限公司 PCB multilayer board alignment structure
CN203259621U (en) * 2013-06-06 2013-10-30 胜宏科技(惠州)股份有限公司 Layer offset test device of multi-layer circuit board

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6709962B2 (en) * 2002-03-19 2004-03-23 N. Edward Berg Process for manufacturing printed circuit boards
US7928591B2 (en) * 2005-02-11 2011-04-19 Wintec Industries, Inc. Apparatus and method for predetermined component placement to a target platform
US8710858B2 (en) * 2010-09-23 2014-04-29 Intel Corporation Micro positioning test socket and methods for active precision alignment and co-planarity feedback

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1681632A (en) * 2002-09-25 2005-10-12 松下电工株式会社 Method for producing laminated board and misregistration-preventing system for laminated board production
CN101212859A (en) * 2006-12-31 2008-07-02 比亚迪股份有限公司 Method for detecting inter-layer displacement of multi-layer flexible printed circuit board
CN101709948A (en) * 2009-12-23 2010-05-19 深南电路有限公司 Alignment detecting method of multilayer printed wiring board
CN201947553U (en) * 2010-06-24 2011-08-24 胜宏科技(惠州)有限公司 Supplementary structure for detecting layer to layer registration of PCB (printed circuit board)
CN201867378U (en) * 2010-10-26 2011-06-15 广州宏镓电子材料科技有限公司 Layer deviation inspection machine capable of being automatically started
CN102072716A (en) * 2010-12-21 2011-05-25 胜宏科技(惠州)有限公司 Method for detecting interlayer offset and drilling offset of multi-layer circuit board
CN102729583A (en) * 2011-04-13 2012-10-17 竞陆电子(昆山)有限公司 PCB multilayer board alignment structure
CN102445140A (en) * 2011-09-21 2012-05-09 东莞生益电子有限公司 Test device and test method for multilayer circuit board alignment
CN102607368A (en) * 2012-03-20 2012-07-25 昆山鼎鑫电子有限公司 Laser drilling deviation inspection method for HDI (High Density Interconnection) plate
CN203259621U (en) * 2013-06-06 2013-10-30 胜宏科技(惠州)股份有限公司 Layer offset test device of multi-layer circuit board

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
多层板层间对位度的设定与控制;林金堵;《印制电路信息》;19940930(第09期);第35-51页 *
多层板涨缩性层偏改善方法及监控方式解析;龚俊,陈涛,张晃初,赵启祥,李加余;《印刷电路信息》;20120131(第1期);第28-33页 *

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