CN103905063B - Decoding method for LDPC coder - Google Patents

Abstract

The invention discloses a decoding method for an LDPC coder. When a layered decoding algorithm is adopted and decoding of each layer is completed, except whether a calibration equation is met, whether overturn of sign bit decodes of all posteriori information (please find the formula in the specification) participating in the decoding happens is further calculated, and correctness and completeness of the termination condition of an HiTx result calculated previously are ensured. According to the decoding method for the LDPC coder, when hardware is achieved, the fault iteration termination situation can be avoided by only adding a small quantity of hardware logics so that the decoding condition of the system can be more complete and a lower bit error rate can be obtained. The decoding method for the LDPC coder can enable a fall line transitional zone of the bit error rate of the LDPC coder to be narrower and enable an error code flat layer to be lower.

Description

Method for stopping decoding of LDPC decoder

Technical Field

The invention relates to a method for terminating decoding, in particular to a method for terminating decoding of an LDPC decoder.

Background

In the whole communication system, channel coding is a very important part, which guarantees the reliability of the communication system. Nowadays, mobile communication is more and more oriented to real-time high-speed transmission, in which case users pay more attention to data reliability, and therefore, it is important to research algorithms and hardware implementation of channel coding with excellent performance. A Low Density Parity Check (LDPC) code is one of the key technologies for mobile communication, and has excellent error correction performance and good application prospect in reliable channel transmission, and has become a most significant research hotspot in the field of current channel coding. The trend that LDPC codes will replace Turbo codes in many cases is already evident, and it will find wide application in deep space communications, optical fiber communications, satellite digital video and audio broadcasting, magnetic/optical/holographic storage, mobile and fixed wireless communications, cable modulators/demodulators and Digital Subscriber Lines (DSL). Communication standards such as 10 gigabit ethernet (10GBASE-T), european digital mobile broadcasting (DVB-S2), WiMax (802.16e), Wi-Fi (802.11n), national mobile multimedia broadcasting standard (CMMB), and 60GHz wireless personal area network WPAN (802.15.3c) all employ LDPC codes as channel coding schemes.

The LDPC code is a special linear block code, and is characterized in that the number of non-zero elements in a parity check matrix H is very small and is far less than that of the zero elements, so the LDPC code can be defined by the check matrix. The LDPC code may be divided into a regular LDPC code and an irregular LDPC code depending on whether the number of non-zero elements in each row and each column of the check matrix H is equal. Each column in the check matrix of the regular LDPC code comprises d_vA non-zero element, each row containing d_cA nonzero element, if the code length is N, then can be recorded as (N, d)_v,d_c). Formula (1) represents the regular LDPC code of (10,3,6), and the corresponding check equation is shown in formula (2).

According to statistics, the modern communication chip has about 1/2 area and 1/3 power consumption in the channel coding module, so that the performance of the channel coding module determines the cost and complexity of the communication chip, and determines the quality of the digital television transmitter and receiver, thereby determining the competitiveness of a company in the market. It is crucial for the whole system to design and implement a high-performance, low-area, and lower-power LDPC decoder.

LDPC decoding algorithms have a significant impact on decoder design. The decoding algorithms of the current LDPC are numerous, and the mainstream algorithms comprise: a sum-product algorithm, a minimum sum algorithm, a hierarchical algorithm, a residual information algorithm, and the like. The minimum sum algorithm and the hierarchical algorithm are algorithms mainly adopted in the design of the existing decoder, and the algorithms are based on the idea of iterative decoding and require certain iteration times to complete decoding. In the implementation process of the LDPC decoder, resources occupied by a memory are the most important, so how to design the LDPC decoder with less occupied memory resources is a design key. The realization of the LDPC decoder in the early period is generally realized by adopting a minimum sum algorithm, and the control is simple and is easy to realize. In recent years, the LDPC decoder is almost realized by hardware by using a layering algorithm, the layering algorithm does not need to store intermediate variable node information, the convergence rate is doubled compared with the minimum convergence rate and the algorithm, the storage resources are greatly saved, and the LDPC decoder has great attraction particularly for the LDPC decoder with strict power consumption requirement.

The hierarchical algorithm is a parallel iterative decoding algorithm, namely, all check nodes are updated firstly in iteration and then all variable nodes are updated, and the update of the check nodes can only utilize bit node information in the last iteration process. In order to utilize the updated information of the variable nodes as early as possible, the convergence iteration speed of the code words is accelerated.

Adopting Binary Phase Shift Keying (BPSK) modulation under Additive White Gaussian Noise (AWGN) channel, and decoding the hierarchical algorithm as follows:

(1) initialization:

setting a maximum number of iterations I_max

Initializing posterior information:(0≤j<N)。y_jreceiving soft information for the channel, σ²As a noise squareDifference, N is LDPC codeword length

Initializing inspection information:(0≤i<m). M is the number of rows of the check matrix

(2) Iteration steps, i is 0,1, …, M-1;

a) verification informationUpdating:

alpha is a correction coefficient, and k is the current iteration number

b) Posterior informationUpdating:

(3) codeword x decision and check equation calculation

If H is present^Tx is 0 or the maximum number of iterations I is reached_maxAnd (4) stopping decoding, otherwise, returning to the step (2) to continue iteration, and adding one to the iteration number.

When the LDPC decoder is implemented by hardware by using a layering algorithm, the decoding is stopped in advance, so that the LDPC decoder with high performance and lower power consumption is realized, and the whole system is very important. In the prior art, the method has the defects that,

generally by setting a fixed, comparatively large number of decoding iterations I_maxEach decoding iteration to a maximum number of times I_maxThe decoding is exited. There is also a scheme for terminating decoding, in which a layer is decoded while calculating whether the layer satisfies a check equation until all layers satisfy the check equation (H)^Tx ═ 0) then decoding is terminated. The greatest disadvantage of the first scheme is that it is power consuming, and it is hardly adopted in practical applications because it is not necessary to iterate to the maximum number in most cases, resulting in "no work" being done by the decoder most of the time. In the second scheme, as shown in FIG. 1, the check matrix H with code rate 3/4 in CMMB standard has nine layers, each layer is Hi (1 ≦ i)<10) The size is 256x 9216. When the decoder has finished decoding the first layer and has finished calculating the check equation H1 of the first layer^TIf x is 0, then decode the second layer and calculate the second layer check equation H2^TWhether x is 0, and so on until H9 is calculated^TIf x is 0, then one iteration is completed, when all H1^Tx,H2^Tx,…,H9^TWhen x is 0, the decoder outputs the decoding result. This scheme has the disadvantage of implementing an LDPC decoder, for example, when the first layer is decoded and H1^Tx is 0, the process of decoding the second layer may change the sign of a posteriori information from which the first layer participates in the calculation of the check equation, so that H1^Tx is not 0. When all check equations are thus calculated to be full (Hi)^Tx is 0), but the decoding is not necessarily completely correct, the decoding is terminated early, i.e. the completeness of the decoding termination condition is not enough. For systems with high Bit Error Rate (BER) performance requirements, such as digital satellite broadcasting of ABS, dvb-s2, etc., especially for systems with ABS having only one LDPC channel decoder, even a bit error at a critical location may result in a large mosaic appearing on the subsequent video display.

Disclosure of Invention

The invention aims to solve the technical problems that the decoding termination method of the LDPC decoder is provided aiming at the defects of the prior art, and the problems of high power consumption, incomplete decoding termination conditions and high bit error rate of the prior method are solved.

In order to solve the technical problems, the technical scheme adopted by the invention is as follows: a method for stopping decoding of an LDPC decoder comprises the following steps:

1) initialization: simulation determination of maximum iteration number I_maxPosterior informationAnd variable node informationInitial value0≤j<N，y_jFor soft information received by the channel, σ²Is the noise variance, and N is the LDPC codeword length; initializing the inspection information:i-0, 1, …, M-1; m is the number of rows of the check matrix;

2) let k equal to 1;

3) updating the verification information using the following equation

Wherein,c_iis the ith check node, v_jIs the jth variable node, M (c)_i) Bit symbol information set, M (c), representing a constraint on i phases of the check symbols_i)/v_jRepresents M (c)_i) Does not contain v_jα is a correction factor, 0<α<1; sgn () is a sign function;

4) updating posterior information using the following formula

5) Judgment ofWhether or not equal toIf it isIs equal toAnd isTerminating the decoding; or a maximum number of iterations I_maxIf yes, the decoding is stopped; otherwise, adding 1 to the value of k, and returning to 3); wherein H_iIs a check matrix of the i-th layer,

compared with the prior art, the invention has the beneficial effects that: the invention not only calculates whether the check equation is satisfied or not when each layer of decoding is completed, but also calculates all posterior information participating in the current decodingWhether the sign bit turns over before and after decoding ensures the calculationHi of^Tx correctness of results and completeness of termination conditions; when the method is realized by hardware, the condition of error termination iteration can be prevented by only adding a small amount of hardware logic, the system termination decoding condition can be more complete and lower bit error rate can be obtained, and particularly when the method is used in a communication receiver system of high-order modulation, the waterfall transition band of the bit error rate of the LDPC decoder realized by the hardware can be narrower.

Drawings

FIG. 1 is a schematic diagram of a check matrix according to an embodiment of the present invention;

FIG. 2 is a flow chart of a method according to an embodiment of the present invention;

FIG. 3 is a block diagram of an implementation of an embodiment of the invention.

Detailed Description

The hardware implementation logic block diagram of the present invention is shown in FIG. 3, and the specific implementation steps are S1, decoding the layer requiredThe information and the check information are respectively taken out from the posterior information storage module and the check information storage module, andthe sign bit is temporarily stored. S2, sending the data to the arithmetic unit to calculate the updated check information and the posterior informationS3, calculating a check equation Hi^TAnd x and judging whether the sign bit is inverted or not through exclusive OR. And S4, storing the new posterior information and the verification information back to the storage module. If S3 is satisfied, outputting a decoding result, otherwise, returning to S1 to start the next iteration until reaching the set maximum iteration number.

To solve the problem that all check equations satisfy H^TWhen decoding of each layer is finished, the invention calculates whether the check equation is satisfied and calculates all the posterior information participating in the decoding of the current timeWhether or not flipping occurred before or after sign bit decoding, i.e.Whether or not equal toAs shown in fig. 2. This ensures the Hi calculated previously^TCorrectness of x results and completeness of termination conditions. When Hi of each layer^Tx is all 0 and each layer participates in the decodingAnd outputting the decoding result when the symbols before and after decoding are not changed.

The method comprises the following steps:

(1) initialization:

setting a maximum number of iterations I_max，(0≤j<N)。y_jReceiving soft information for the channel, σ²For noise variance, N is the LDPC codeword length

Initializing inspection information:(0≤i<m). M is the number of rows of the check matrix

(2) Iteration steps, i is 0,1, …, M-1;

a) verification informationUpdating:

alpha is a correction coefficient, and k is the current iteration number;

b) posterior informationUpdating:

c) calculating whether the sign bit is turned overWhether or not equal to

c) Each layer of information participating in calculation is judgedAnd calculates Hi^TWhether x is 0;

(3) exit iteration decision

If all Hi^Tx is all 0 and the sign bit of each layer is not inverted or reaches the maximum iteration number I_maxAnd (4) stopping decoding, otherwise, returning to the step (2) to continue iteration, and adding one to the iteration number.

The hardware implementation logic block diagram of the present invention is shown in figure 3,the decoding and decoding terminating steps are S1, decoding the layer required by the decodingThe information and the check information are respectively taken out from the posterior information storage module and the check information storage module, andthe sign bit is temporarily stored. S2, sending the data to the arithmetic unit to calculate the updated check information and the posterior informationS3, calculating a check equation Hi^TAnd x and judging whether the sign bit is inverted or not through exclusive OR. And S4, storing the new posterior information and the verification information back to the storage module. If S3 is satisfied, outputting a decoding result, otherwise, returning to S1 to start the next iteration until reaching the set maximum iteration number.

Claims (1)

1. A method for terminating decoding in an LDPC decoder, the method comprising the steps of:

1) initialization: simulation determination of maximum iteration number I_maxPosterior informationAnd variable node informationInitial value0≤j<N，y_jFor soft information received by the channel, σ²Is the noise variance, and N is the LDPC codeword length; initializing the inspection information:i-0, 1, …, M-1; m is the number of rows of the check matrix;

2) let k equal to 1;

3) updating the verification information using the following equation

${m^k}_{c_i\&RightArrow;v_j}=\mathrm{\&alpha;}\&CenterDot;\underset{v_n\&Element;M\left(c_i\right)/v_j}{\&Pi;}\mathrm{sgn}\left({m^{k-1}}_{v_n\&RightArrow;c_i}\right)\&CenterDot;\underset{v_n\&Element;M\left(c_i\right)/v_j}{min}\left|{m^{k-1}}_{v_n\&RightArrow;c_i}\right|;$

Wherein,c_iis the ith check node, v_jIs the jth variable node, M (c)_i) Bit symbol information set, M (c), representing a constraint on i phases of the check symbols_i)/v_jRepresents M (c)_i) Does not contain v_jα is a correction factor, 0<α<1; sgn () is a sign function;

4) updating posterior information using the following formula

5) Judgment ofWhether or not equal toIf it isIs equal toAnd isTerminating the decoding; or a maximum number of iterations I_maxIf yes, the decoding is stopped; otherwise, adding 1 to the value of k, and returning to 3); wherein H_iIs a check matrix of the i-th layer,