CN103904045A - Wafer-level CSP structure with insulated side wall and packaging method thereof - Google Patents
Wafer-level CSP structure with insulated side wall and packaging method thereof Download PDFInfo
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- CN103904045A CN103904045A CN201410156161.XA CN201410156161A CN103904045A CN 103904045 A CN103904045 A CN 103904045A CN 201410156161 A CN201410156161 A CN 201410156161A CN 103904045 A CN103904045 A CN 103904045A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 title claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 28
- 229910052751 metal Inorganic materials 0.000 claims abstract description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 39
- 229910052710 silicon Inorganic materials 0.000 claims description 39
- 239000010703 silicon Substances 0.000 claims description 39
- 239000000758 substrate Substances 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 10
- 239000000377 silicon dioxide Substances 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 230000000694 effects Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 59
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 230000000149 penetrating effect Effects 0.000 description 3
- 239000011247 coating layer Substances 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 230000009194 climbing Effects 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007888 film coating Substances 0.000 description 1
- 238000009501 film coating Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a wafer-level CSP structure with an insulated side wall and a packaging method of the wafer-level CSP structure with the insulated side wall and belongs to the technical field of semiconductor package. The wafer-level CSP structure with the insulated side wall comprises a silica-based body (101) with a plurality of chip electrodes (110), and insulating layers (200), wherein the insulating layers (200) are arranged on the surface of the side, provided with the chip electrodes (110), of the silica-based body (101) and the side wall of the silica-based body (101), insulating layer openings (201) are formed in the insulating layers (200) and are located over the chip electrodes (110), and metal protrusions (400) are arranged in the insulating layer openings (201) and fixedly connected with the chip electrodes (110). According to the wafer-level CSP structure with the insulated side wall, the wicking effect of the side wall is effectively eliminated, electric leakage of chip scale package is avoided, the yield of devices is increased, the packaging method is easy, and manufacturing cost is reduced.
Description
Technical Field
The invention relates to a wafer-level CSP packaging structure and a packaging method thereof, in particular to a wafer-level CSP packaging structure with insulated side walls and a packaging method thereof, belonging to the technical field of semiconductor packaging.
Background
In the conventional wafer-level csp (chip Scale package) package structure, silicon around a chip is exposed in an assembly environment, and in a mounting reflow process, a solder ball or an electrode area is easy to cause part of solder to climb onto the exposed silicon on the side wall of the chip due to excessive printing amount of solder paste, thereby causing chip leakage. Meanwhile, for extremely small-sized packaged products, such as packaged products with sizes of 0402, 0210, 01005 and the like, the self weight of the packaged products is very light as shown in the left drawing of fig. 1, and if the printing quantities of solder pastes of two electrodes are different in the surface mounting process and the reflow heating temperature is not uniform, the two ends of the electrodes are unbalanced, so that one end of a device is easy to tilt up to form a tombstone phenomenon, and the device mounting is poor as shown in the right drawing of fig. 1.
Disclosure of Invention
The invention aims to overcome the defects of the wafer-level CSP packaging structure and provides the wafer-level CSP packaging structure with insulated side walls and a packaging method thereof, wherein the wafer-level CSP packaging structure is used for improving poor device mounting and is not easy to cause chip electric leakage.
The object of the invention is thus achieved：
The invention discloses a wafer-level CSP packaging structure with insulated side walls, which comprises a silicon substrate body with a plurality of chip electrodes and an insulating layer, wherein the insulating layer is arranged on the surface of the silicon substrate body at one side of the chip electrodes and the side walls of the silicon substrate body, an insulating layer opening is arranged on the insulating layer right above the chip electrodes, metal salient points are arranged in the insulating layer opening, and the metal salient points are fixedly connected with the chip electrodes.
The chip electrodes are distributed in an array shape.
The height h1 of the metal bump above the insulating layer is more than or equal to 10 mu m, h 1.
Furthermore, the height h1 of the metal bump above the insulating layer is not less than 15 mu m and not more than h1 and not more than 25 mu m.
The surface of the silicon-based body on the other side of the chip electrode is provided with a back surface protection layer.
Furthermore, the periphery of the silicon-based body positioned on one side of the chip electrode is step-shaped, and the chip electrode is positioned on the top of the step-shaped silicon-based body; the insulating layer is arranged on the surface of the silicon-based body on one side of the chip electrode and the side wall of the silicon-based body, an insulating layer opening is formed in the insulating layer right above the chip electrode, a metal salient point is arranged in the insulating layer opening, and the metal salient point is fixedly connected with the chip electrode.
Further, the step-shaped side wall of the silicon-based body has at least one step.
Further, the total depth h2 of the steps is more than or equal to 30 mu m.
Further, the total depth h2 of the steps is 100-150 μm.
The invention has the beneficial effects that:
1. according to the wafer-level CSP packaging structure with the insulated side wall, the step structure is arranged on the side wall of the silicon substrate body and the insulating layer is fully distributed on the side wall, so that the tin climbing phenomenon of the silicon substrate side wall is eliminated, the electric leakage problem of chip size packaging is solved, and the mounting yield of devices is improved;
2. the wafer-level CSP packaging method with insulated side walls has simple manufacturing process and reduces the production cost.
Drawings
FIG. 1 is a schematic diagram of a conventional wafer-level CSP structure showing a tin-climbing phenomenon;
FIG. 2 is a process flow diagram of a wafer level CSP packaging method with sidewall isolation;
FIG. 3 is a cross-sectional view of a first embodiment of a wafer level CSP package with sidewall insulation;
FIG. 4 is a schematic front view of the positional relationship between the chip electrodes and the silicon-based body of FIG. 3;
fig. 5 to fig. 20 are schematic process diagrams of a packaging method according to a first embodiment;
FIG. 21 is a cross-sectional view of a second embodiment of a side-wall insulated wafer-level CSP package structure of the present invention;
fig. 22 to 27 are schematic process diagrams of a packaging method according to a second embodiment;
FIGS. 28 and 29 are schematic cross-sectional views of a wafer level CSP package with sidewall insulation according to a third embodiment of the present invention;
fig. 30 is a schematic front view illustrating a positional relationship between a chip electrode and a silicon substrate in a fourth embodiment of a side-wall-insulated wafer-level CSP structure according to the present invention;
FIG. 31 is a cross-sectional view of a fifth embodiment of a side-wall insulated wafer-level CSP package structure of the present invention;
wherein,
Silicon-based body 101
Back surface protection layer 130
Insulating layer opening 201
Film layer I510
And a film II 520.
Detailed Description
The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown, so that this disclosure will fully convey the scope of the invention to those skilled in the art. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.
Example one
Referring to fig. 2, the invention relates to a wafer level CSP packaging method with insulated side walls, which comprises the following steps:
executing the step one: providing a wafer with a chip electrode array;
and (5) executing the step two: forming a wide groove which cannot cut through the wafer on the surface of the wafer along a scribing way of the wafer;
and step three is executed: depositing insulating layers on the surface of the wafer and the inner wall of the wide groove, and curing and forming;
and step four is executed: an insulating layer opening penetrating through the insulating layer is formed above the chip electrode;
and executing the step five: chemically plating metal bumps in the openings of the insulating layer;
and a sixth step is executed: coating a film layer I on the metal salient points and then turning over the die to enable the back of the wafer to be upward;
and a seventh step is executed: thinning the back of the wafer until the bottom of the wide groove is exposed;
and step eight is executed: coating a film layer II on the back of the wafer and turning over the mold;
the execution step nine: and sequentially removing the film layer I and the film layer II to form a single wafer-level CSP packaging structure with insulated side walls.
By adopting the above process method, the wafer-level CSP packaging structure with insulated side wall according to the present invention is formed, as shown in fig. 3 and 4, the silicon substrate 101 has two chip electrodes 110, the insulating layer 200 is disposed on the surface of the silicon substrate 101 at one side of the chip electrodes 110 and the side wall of the silicon substrate 101, the insulating layer 200 is made of insulating material with low thermal expansion coefficient, generally SiO2, so as to overcome the tin-climbing phenomenon. An insulating layer opening 201 is formed in the insulating layer 200 right above the chip electrode 110, a metal bump 400 formed by electroless plating using a metal such as nickel/gold is disposed in the insulating layer opening 201, and the metal bump 400 is fixedly connected to the chip electrode 110. The height h1 and h1 of the metal bump 400 above the insulating layer 200 are more than or equal to 10 microns, preferably more than or equal to 15 microns and less than or equal to h1 and less than or equal to 25 microns.
The packaging method of the first embodiment specifically comprises the following process steps:
as shown in fig. 5 and 6, a wafer 100 with an array of chip electrodes is provided;
as shown in fig. 7, wide grooves 120 which do not cut through the wafer are formed on the surface of the wafer 100 on the side of the chip electrode 110 along the scribe line 12 of the wafer, the transverse wide grooves 120 and the longitudinal wide grooves 120 are staggered with each other, and a thick blade is selected as a dicing blade, preferably a dicing blade with a width of 65 μm and a depth of 150 μm; the partial sawing may be performed by using other specific processes besides mechanical sawing, including but not limited to laser sawing, chemical etching, and the like, and the depth of the wide trench 120 is not less than 30 μm, preferably 100-150 μm.
As shown in fig. 8, an insulating layer 200 is deposited on the surface of the silicon-based body 101 on the chip electrode 110 side and the inner wall of the wide trench 120, and cured.
As shown in fig. 9 and 10, a photoresist layer 300 is covered on the surface of the insulating layer 200, and the photoresist material right above the chip electrode 110 is removed by a photolithography process to form a photoresist opening pattern 301 penetrating the photoresist layer 300 up and down;
as shown in fig. 11, the insulating material in the opening of the photolithography opening pattern 301 is removed by etching, so as to form an insulating layer opening 201, exposing the surface of the chip electrode 110;
as shown in fig. 12, the remaining photoresist material is removed;
as shown in fig. 13, a metal bump 400 is chemically plated on the surface of the chip electrode 110;
as shown in fig. 14 and 15, a coating layer i 510 is coated on one side of the metal bump 400, and the mold is turned over so that the back surface of the wafer 100 faces upward;
as shown in fig. 16, the back surface of the wafer 100 is thinned by mechanical horizontal grinding until the wide trenches 120 are exposed, and the insulating material at the bottom of the wide trenches 120 is also removed;
as shown in fig. 17 and 18, coating a coating layer ii 520 on the surface of the wafer, and performing mold turning again;
as shown in fig. 19 and 20, the film layer i 510 and the film layer ii 520 are removed in sequence to form a single wafer-level CSP package structure with insulating sidewalls.
Example two
Referring to fig. 2, the invention relates to a wafer level CSP packaging method with insulated side walls, which comprises the following steps:
executing the step one: providing a wafer with a chip electrode array;
and (5) executing the step two: forming a wide groove which cannot cut through the wafer on the surface of the wafer along a scribing way of the wafer;
and step three is executed: depositing insulating layers on the surface of the wafer and the inner wall of the wide groove, and curing and forming;
and step four is executed: an insulating layer opening penetrating through the insulating layer is formed above the chip electrode;
and executing the step five: chemically plating metal bumps in the openings of the insulating layer;
and a sixth step is executed: the wafer is inversely arranged on the film layer I, so that the back of the wafer faces upwards;
and a seventh step is executed: thinning the back of the wafer;
and step eight is executed: coating a film layer II on the back of the wafer and turning over the mold;
the execution step nine: and removing the film layer I, cutting the wafer along the scribing street of the wafer, removing the film layer II, and finally cracking to form a single wafer-level CSP packaging structure with insulated side walls.
With the above process, the wafer-level CSP structure with insulated sidewalls according to the present invention is formed, and referring to fig. 21, the silicon substrate 101 of the present invention has two chip electrodes 110, the periphery of the silicon substrate 101 located at one side of the chip electrodes 110 is step-shaped, and the chip electrodes 110 are located on the top of the step-shaped silicon substrate 101. The step 121 is at least one step, and the depth h2 of the step 121 is greater than or equal to 30 μm, preferably 100-150 μm.
The insulating layer 200 is disposed on the surface of the silicon substrate 101 on one side of the chip electrode 110, the surface of the step 121 on the periphery of the silicon substrate 101, and the sidewall of the step 121, and the insulating layer 200 is made of an insulating material with a low thermal expansion coefficient, generally SiO2, to overcome the tin-climbing phenomenon. An insulating layer opening 201 is formed in the insulating layer 200 right above the chip electrode 110, a metal bump 400 formed by electroless plating using a metal such as nickel/gold is disposed in the insulating layer opening 201, and the metal bump 400 is fixedly connected to the chip electrode 110. The height h1 and h1 of the metal bump 400 above the insulating layer 200 are more than or equal to 10 microns, preferably more than or equal to 15 microns and less than or equal to h1 and less than or equal to 25 microns.
The difference between the process of the packaging method of the second embodiment and the process of the first embodiment is as follows:
as shown in fig. 22, the wafer with the metal bumps 400 formed on the surface of the chip electrode 110 is inverted to a film material, and a film layer i 510 is formed after curing, with the back surface of the wafer 100 facing upward;
as shown in fig. 23, the back surface of the wafer 100 is thinned by mechanical horizontal grinding until the remaining thickness of silicon above the wide trenches 120 is h3, and the thickness of h3 is more than or equal to 5 μm;
as shown in fig. 24, a film material is coated on the surface of the wafer and cured to form a film layer ii 520;
turning over the mold, and removing the film layer I510 as shown in FIG. 25;
as shown in fig. 26 and 27, the wafer is cut in the wide trench 120 by a dicing blade or a laser to form a street having a width smaller than that of the wide trench 120, and then the street is diced to form a single side-wall-insulated wafer-level CSP package structure, in which the dicing blade is thinner than the dicing blade used for forming the wide trench 120, and functions to separate the wafer so that an insulating layer having a certain thickness is left on the periphery of the single side-wall-insulated wafer-level CSP package structure.
EXAMPLE III, see FIGS. 28 and 29
The difference between this embodiment and the first and second embodiments is: the surface of the silicon substrate 101 on the other side of the chip electrode 110 is provided with a backside protection layer 130 to enhance the strength of the wafer-level CSP structure.
The back surface protective layer is formed on the other surface of the wafer 100 by a method of film-coating or printing before the film layer ii 520 is applied to the surface of the wafer 100, and is divided by a dicing blade or a laser beam when forming the dividing lines.
The wafer-level CSP packaging structure with insulated side wall and the packaging method thereof of the present invention are not limited to the above preferred embodiments, for example, there may be a plurality of chip electrodes 110 distributed in an array on the silicon substrate 101, as shown in fig. 30, to meet the requirements of product application; the periphery of the silicon-based body 102 formed by the wafer level process may have a slope shape, as shown in fig. 31. Therefore, any modification, equivalent change and modification of the above embodiments according to the technical spirit of the present invention by those skilled in the art are within the scope of the present invention as defined in the claims.
Claims (9)
1. A wafer level CSP packaging structure with insulated side wall comprises a silicon substrate (101) with a plurality of chip electrodes (110),
the method is characterized in that: the silicon substrate is characterized by further comprising an insulating layer (200), wherein the insulating layer (200) is arranged on the surface of the silicon substrate (101) on one side of the chip electrode (110) and on the side wall of the silicon substrate (101), an insulating layer opening (201) is formed right above the chip electrode (110) in the insulating layer (200), a metal bump (400) is arranged in the insulating layer opening (201), and the metal bump (400) is fixedly connected with the chip electrode (110).
2. The wafer level CSP packaging structure of claim 1, wherein: the chip electrodes (110) are distributed in an array shape.
3. The wafer level CSP packaging structure of claim 1, wherein: the height h1 of the metal bump (400) above the insulating layer (200) is more than or equal to 10 mu m, h 1.
4. The wafer level CSP package structure of claim 3, wherein: the height h1 of the metal bump (400) above the insulating layer (200) is not less than 15 mu m and not more than 25 mu m of the h 1.
5. The wafer level CSP packaging structure of claim 1, wherein: and a back surface protection layer (130) is arranged on the surface of the silicon-based body (101) positioned on the other side of the chip electrode (110).
6. The wafer level CSP package structure of any one of claims 1 to 5, wherein: the periphery of the silicon-based body (101) on one side of the chip electrode (110) is stepped, and the chip electrode (110) is positioned on the top of the stepped silicon-based body (101); the insulating layer (200) is arranged on the surface of the silicon-based body (101) on one side of the chip electrode (110) and on the side wall of the silicon-based body (101), an insulating layer opening (201) is formed right above the chip electrode (110) on the insulating layer (200), a metal bump (400) is arranged in the insulating layer opening (201), and the metal bump (400) is fixedly connected with the chip electrode (110).
7. The wafer level CSP package structure of claim 6, wherein: the step-shaped side wall of the silicon-based body (101) is provided with at least one step.
8. The wafer level CSP packaging structure of claim 7, wherein: the total depth h2 of the step is more than or equal to 30 mu m.
9. The wafer level CSP packaging structure of claim 8, wherein: the total depth h2 of the step is 100-150 μm.
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| CN201410156161.XA CN103904045A (en) | 2014-04-18 | 2014-04-18 | Wafer-level CSP structure with insulated side wall and packaging method thereof |
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| CN201410156161.XA CN103904045A (en) | 2014-04-18 | 2014-04-18 | Wafer-level CSP structure with insulated side wall and packaging method thereof |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104201114A (en) * | 2014-08-26 | 2014-12-10 | 江阴长电先进封装有限公司 | Packaging method and packaging structure of chip with sidewall in insulating protection |
| CN106024646A (en) * | 2016-06-01 | 2016-10-12 | 南通富士通微电子股份有限公司 | Full-coating wafer-level packaging method for semiconductor device |
| CN106024648A (en) * | 2016-06-15 | 2016-10-12 | 中航（重庆）微电子有限公司 | Passivating method for front side and side walls of discrete device chip |
| CN107887259A (en) * | 2017-09-26 | 2018-04-06 | 宁波芯健半导体有限公司 | A kind of small-size chips method for packing |
| CN110176447A (en) * | 2019-05-08 | 2019-08-27 | 上海地肇电子科技有限公司 | Surface-assembled component and its packaging method |
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| US20040113283A1 (en) * | 2002-03-06 | 2004-06-17 | Farnworth Warren M. | Method for fabricating encapsulated semiconductor components by etching |
| US20050082651A1 (en) * | 2003-10-20 | 2005-04-21 | Farnworth Warren M. | Methods of coating and singulating wafers and chip-scale packages formed therefrom |
| CN101339910A (en) * | 2007-07-03 | 2009-01-07 | 台湾积体电路制造股份有限公司 | Method for manufacturing wafer-level chip scale package |
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| US6338980B1 (en) * | 1999-08-13 | 2002-01-15 | Citizen Watch Co., Ltd. | Method for manufacturing chip-scale package and manufacturing IC chip |
| US20040113283A1 (en) * | 2002-03-06 | 2004-06-17 | Farnworth Warren M. | Method for fabricating encapsulated semiconductor components by etching |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104201114A (en) * | 2014-08-26 | 2014-12-10 | 江阴长电先进封装有限公司 | Packaging method and packaging structure of chip with sidewall in insulating protection |
| CN106024646A (en) * | 2016-06-01 | 2016-10-12 | 南通富士通微电子股份有限公司 | Full-coating wafer-level packaging method for semiconductor device |
| CN106024648A (en) * | 2016-06-15 | 2016-10-12 | 中航（重庆）微电子有限公司 | Passivating method for front side and side walls of discrete device chip |
| CN107887259A (en) * | 2017-09-26 | 2018-04-06 | 宁波芯健半导体有限公司 | A kind of small-size chips method for packing |
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| CN110176447A (en) * | 2019-05-08 | 2019-08-27 | 上海地肇电子科技有限公司 | Surface-assembled component and its packaging method |
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Application publication date: 20140702 |