CN103902470B - Read processing method, equipment and the system during missing - Google Patents

Abstract

The invention provides a processing method, device and system for reading loss. The method comprises that the first processor generates address information, and the address information includes a Cache Tag; when the first processor determines that the first Cache Line exists, obtains the second processor recorded in the first Cache Line information, the Tag of the first Cache Line is the same as the value of the Cache Tag, and the status bit indicates an invalid state; the first processor sends the information to the second processor according to the information of the second processor and unicast sending the bus read transaction, so that the second processor provides the data of the first Cache Line when storing a valid copy of the data of the first Cache Line. The embodiment of the present invention can reduce the power consumption overhead during read misses.

Description

Processing method, device and system for reading loss

technical field

The present invention relates to storage technology, in particular to a processing method, device and system for reading loss.

Background technique

Cache memory (Cache) is a high-speed small-capacity memory between the processor and the memory in the hierarchical structure of the computer storage system. Cache generally consists of many cache memory lines (Cache Line), and each Cache Line is an independent entry in Cache.

During the read operation, the Cache will receive the address information and compare the cache register tag (Cache Tag) in the address information with the tag (Tag) in the Cache Line. When there is no CacheLine corresponding to the Cache Tag, or there is but the When the Cache Line is invalid, a read miss occurs.

After a read miss occurs, the Cache will broadcast the bus read transaction to all the Cache on the bus through the bus. The bus read transaction contains the missing address information. When there is valid data corresponding to the address information, respond to the bus read transaction and provide the valid data to the missing Cache.

It can be seen from the above description that when the above-mentioned read miss occurs, the prior art adopts a broadcast method, and all caches on the bus that receive the bus read transaction need to perform Tag comparison, which consumes a lot of power consumption.

Contents of the invention

In view of this, embodiments of the present invention provide a processing method, device, and system for read misses, so as to solve the problem of high power consumption of read misses in the prior art.

In the first aspect, a processing method for reading loss is provided, including:

The first processor generates address information, where the address information includes a Cache Tag;

When the first processor determines that there is a first Cache Line, it obtains the information of the second processor recorded in the first Cache Line, the Tag of the first Cache Line is the same as the value of the CacheTag, and the status bit indicates an invalid state;

The first processor unicasts the bus read transaction to the second processor according to the information of the second processor, so that the second processor is storing a valid data copy of the first Cache Line , provide the data of the first Cache Line.

In combination with the first aspect, the first possible implementation of the first aspect further includes:

After the status bit of the first Cache Line is invalid, the first processor records the information of the second processor in the first Cache Line, and the second processor stores the information of the first Cache Line last time. Processor for a CacheLine of data copies.

With reference to the first aspect or the first possible implementation of the first aspect, in the second possible implementation of the first aspect, the information of the second processor is recorded in the data area of the first Cache Line .

In combination with the first aspect or the first possible implementation of the first aspect, the third possible implementation of the first aspect further includes:

The first processor receives the bus read transaction response sent by the second processor, wherein when the second processor stores a valid data copy of the first Cache Line, the bus read transaction response includes The data of the first Cache Line, or, when the first processor does not store a valid copy of the data of the first Cache Line, the bus read transaction response is used to indicate that the first processor is on the bus broadcast send bus read transaction; or,

If the first processor does not receive the bus read transaction response sent by the second processor within the set time, it broadcasts and sends the bus read transaction on the bus, and the read transaction response is not received by the second processor. It is not sent when storing the valid data copy of the first Cache Line.

In the second aspect, a processing method for reading loss is provided, including:

The second processor receives the bus read transaction sent by the first processor unicast, the bus read transaction is sent by the first processor according to the information of the second processor recorded in the first Cache Line, and the first processor The Tag of the Cache Line is the same as the Cache Tag value in the address information generated by the first processor, and the status bit indicates an invalid status;

The second processor provides the data of the first Cache Line to the first processor when storing a valid copy of the data of the first Cache Line.

In combination with the second aspect, the first possible implementation manner of the second aspect further includes:

When the second processor does not store a valid data copy of the first Cache Line, it sends a bus read transaction for instructing the first processor to broadcast a bus read transaction on the bus to the first processor response; or,

When the second processor does not store a valid data copy of the first Cache Line, it does not send a bus read transaction response, so that the first processor does not receive the second processor within a set time The sent bus read transaction response broadcasts the sent bus read transaction on the bus.

In the third aspect, a processing device for reading loss is provided, including:

A generating module, configured to generate address information, where the address information includes a Cache Tag;

An acquisition module, configured to acquire the information of the second processor recorded in the first CacheLine when it is determined that there is the first Cache Line, the Tag of the first Cache Line is the same as the CacheTag value, and the status bit indicates is invalid;

A sending module, configured to unicast send a bus read transaction to the second processor according to the information of the second processor, so that when the second processor stores a valid data copy of the first Cache Line , providing the data of the first Cache Line.

In combination with the third aspect, the first possible implementation of the third aspect further includes:

A recording module, configured to record the information of the second processor in the first CacheLine after the state bit of the first Cache Line is in an invalid state, and the second processor stores the information of the first Cache for the last time Handler for Line's data copy.

With reference to the third aspect or the first possible implementation of the third aspect, in a second possible implementation of the third aspect, the information of the second processor is recorded in the data area of the first Cache Line .

In combination with the third aspect or the first possible implementation manner of the third aspect, the third possible implementation manner of the third aspect further includes:

A receiving module, configured to receive the bus read transaction response sent by the second processor, wherein when the second processor stores a valid copy of the data of the first Cache Line, the bus read transaction response includes the The data of the first Cache Line, or, when the first processor does not store a valid copy of the data of the first Cache Line, the bus read transaction response is used to instruct the first processor to broadcast on the bus send a bus read transaction; or,

The broadcast module is used to broadcast and send the bus read transaction on the bus if the bus read transaction response sent by the second processor is not received within the set time, and the read transaction response is not stored in the second processor A valid data copy of the first Cache Line is not sent.

In the fourth aspect, a processing device for reading loss is provided, including:

The receiving module is configured to receive the bus read transaction sent by the first processor in unicast, the bus read transaction is sent by the first processor according to the information of the second processor recorded in the first Cache Line, the second processor The Tag of a Cache Line is the same as the CacheTag value in the address information generated by the first processor, and the status bit indicates an invalid state;

A sending module, configured to provide the first processor with the data of the first Cache Line when storing a valid copy of the data of the first Cache Line.

With reference to the fourth aspect, in a first possible implementation manner of the fourth aspect, the sending module is further configured to:

When there is no valid data copy of the first Cache Line stored, sending a bus read transaction response for instructing the first processor to broadcast a bus read transaction on the bus to the first processor; or,

When there is no effective data copy of the first Cache Line stored, the bus read transaction response is not sent, so that the first processor does not receive the bus read transaction response sent by the second processor within the set time , broadcast a bus read transaction on the bus.

In the fifth aspect, a system for processing missing reads is provided, including:

any device of the third aspect; and,

Any device of the fourth aspect.

Through the above technical solution, the information of the processor that stored its copy last time is recorded in the Cache Line, and when the read is missing, the bus broadcast transaction is sent to the corresponding processor by unicast according to the information of the processor, which can avoid the problems caused by the broadcast transmission method , reducing power overhead.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings that need to be used in the description of the embodiments. Obviously, the drawings in the following description are some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained based on these drawings without any creative effort.

Fig. 1 is the basic structural representation of the Cache in the embodiment of the present invention;

Fig. 2 is a schematic flow chart of an embodiment of a processing method when reading a deletion in the present invention;

Fig. 3 is a schematic flow chart of another embodiment of the processing method for reading deletions in the present invention;

Fig. 4 is a schematic flow chart of another embodiment of the processing method for reading deletions in the present invention;

FIG. 5 is a schematic flow diagram of another embodiment of the processing method for reading deletions in the present invention;

Fig. 6 is the MSI state change diagram of Cache Line caused by local processor memory read and write operation in the embodiment of the present invention;

Fig. 7 is the MSI state change diagram of the CacheLine caused by the processor memory read and write operation on the bus in the embodiment of the present invention;

FIG. 8 is a schematic structural diagram of an embodiment of a processing device for read misses in the present invention;

FIG. 9 is a schematic structural diagram of another embodiment of the processing device for read misses in the present invention;

FIG. 10 is a schematic structural diagram of another embodiment of a processing device for read misses in the present invention;

FIG. 11 is a schematic structural diagram of another embodiment of the processing device for read misses in the present invention;

FIG. 12 is a schematic structural diagram of an embodiment of a processing system for read-misses in the present invention.

detailed description

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

As shown in Figure 1, it is a schematic diagram of the basic structure of the Cache. The address information of the Cache includes three parts: a cache tag (Cache Tag), a cache index (Cache index) and an offset (offset). Among them, the Cache index is used to index the position of a certain Cache Line in the Cache. A Cache Line includes three parts: status bit (Valid bit), tag (Tag) and data (Data). Assuming that the Cache has w ways (way), then a Cache index can obtain w Cache Lines at the same time, and these w Cache Lines form a group (Cache set). At this time, it is necessary to compare the Cache Tag with the Tag in the Cache Line. If the values are equal, the Cache hits, and the data of the hit Cache Line is output through a multiplexer (MUX). Among them, since the number of bits in the Tag in the Cache Tag and the Cache Line may be different, the Cache Tag can be converted to be consistent with the number of bits in the Tag in the Cache Line through a bypass translation buffer (Translation LookasideBuffer, TLB) during comparison. whether the values are the same.

Cache can greatly reduce the memory bandwidth requirement of a single processor. If the memory bandwidth requirement of a single processor is reduced, multiple processors can share the same memory. Shared memory systems support caching of both shared and private data, with private data being used by a single processor and shared data being used by multiple processors. Because the memory views stored by two different processors are obtained through their own Cache, if there are no other precautions, when one of the processors changes the value of the shared data in its Cache, the other processor still retains it. When the original data is shared, the two processors get two different values respectively, which is the Cache consistency problem.

The key to implementing the write invalidation protocol in a multiprocessor system is to use the bus or other broadcast medium to complete the invalidation operation. To realize the invalid operation, the processor only needs to obtain the control right of the bus and then broadcast the address of invalid data on the bus (bus write invalid transaction). All processors constantly snoop the bus to monitor addresses. The processors check whether there is an address broadcast on the bus in their respective Cache. If there is, the corresponding data in the Cache shall be invalidated.

When a processor misses a read, it broadcasts the address of the missing data on the bus (a bus read transaction). All processors constantly snoop the bus to monitor addresses. The processors check whether there is an address broadcast on the bus in their respective Cache. If so, respond to the bus read transaction and provide this Cache Line.

When a processor misses a write, it broadcasts the address of the missing data on the bus (bus exclusive read transaction). All processors constantly snoop the bus to monitor addresses. The processors check whether there is an address broadcast on the bus in their respective Cache. If so, respond to the bus exclusive read transaction, provide this Cache Line, and invalidate the local copy.

Not only the above-mentioned invalidation protocol, but also the existing coherence protocol also needs to broadcast the bus read transaction when a Cache read miss occurs. In order to solve the problem of high power consumption caused by broadcasting, the present invention provides the following embodiments.

Fig. 2 is a schematic flow chart of an embodiment of a processing method for reading deletions in the present invention, including:

21: The first processor generates address information, where the address information includes a cache memory tag (CacheTag);

22: When the first processor determines that there is a first cache memory line (Cache Line), obtain the information of the second processor in the first cache line, and the tag (Tag ) is the same as the value of the Cache Tag, and the status bit indicates an invalid status;

23: The first processor unicasts the bus read transaction to the second processor according to the information of the second processor, so that the second processor stores the valid first Cache Line When copying data, provide the data of the first Cache Line to the first processor.

The aforementioned first processor may refer to any processor that initiates a bus read transaction.

Optionally, as shown in FIG. 3, before reading the information of the processor recorded in the first Cache Line, taking before 21 as an example, the method may also include:

31: After the status bit of the first Cache Line is invalid, the first processor records the information of the second processor in the first Cache Line, and the second processor stores the information of the first Cache Line last time. The processor of the data copy of the Cache Line.

Optionally, the information of the second processor may be recorded in a data area (data) of the first Cache Line.

Correspondingly, referring to FIG. 4, the process executed by the second processor may be as follows:

41: The second processor receives the bus read transaction sent by the first processor in unicast, the bus read transaction is sent by the first processor according to the information of the second processor recorded in the first Cache Line, and the The Tag of the first Cache Line has the same value as the CacheTag in the address information generated by the first processor, and the status bit indicates an invalid status;

42: The second processor provides the data of the first Cache Line to the first processor when storing a valid copy of the data of the first Cache Line.

In this embodiment, by recording the information of the processor that stored its copy last time in the Cache Line, and sending the bus broadcast transaction to the corresponding processor by unicast according to the information of the processor when the read is missing, the problems caused by the broadcast transmission mode can be avoided. Reduce power overhead.

Fig. 5 is a schematic flow chart of another embodiment of the processing method of the present invention when reading a deletion, including:

51: The first processor generates a read address.

The structure of the read address can be seen in Figure 1, including Cache Tag, Cache index and offset.

52: The first processor finds the corresponding Cache Set according to the index (Cache index) of the read address.

For example, referring to FIG. 1, a Cache index can find w Cache Lines, and the w Cache Lines form a Cache Set.

53: The first processor judges whether there is a matching Tag, and if yes, executes 54; otherwise, executes 59.

The Cache Tag in the read address can be compared with the Tag of each Cache Line in the Cache Set. If there is a Cache Set and Tag with the same value, it indicates that the matching Tag is stored, otherwise it does not exist.

54: The first processor judges whether the Cache line status bit matched by the Tag is valid, and if so, executes 55; otherwise, executes 56.

Wherein, when the Tag of a Cache Line is the same as the Cache Tag, the Cache Line is the Cache Line that the Tag matches.

As shown in Figure 1, the Cache Line includes a status bit (Valid bit), which is used to indicate whether it is in a valid state. For example, if the Valid bit=1, it indicates that it is valid, and when the Valid bit=0, it indicates that it is invalid.

55: A read hit, and then the first processor can read out the data.

56: Read the number of the processor from the data area of the Cache line that the Tag matches. This processor can be called the second processor, which is the processor that stored the data copy of the Cache Line last time, and sends the data to the second processor. The device unicasts the bus read transaction.

Among them, for a Cache Line, when its status bit indicates that it is invalid, for example, after Valid bit=0, in addition to recording the written data in the data area of the Cache Line, it is also necessary to record the processor that modifies the Cache Line data information and is updated every time the processor modifies it. When a processor modifies the data of the Cache Line, it may first store the data of the Cache Line in the processor, that is, a copy of the data of the Cache Line will be stored in the processor.

Since the information of the corresponding processor is recorded in each modification of the Cache Line, the data area of the CacheLine can record the information of the processor that modified its data last time, that is, the information of the processor that stored its data copy last time, for example The number of the processor.

57: After receiving the bus read transaction, the second processor judges whether there is a valid copy, the copy is a data copy corresponding to the Cache Line, if yes, go to 58, otherwise go to 59.

Wherein, the processor that receives the bus read transaction can also compare the Cache Tag first, and after finding a matching CacheLine, if the status bit of the Cache Line is valid, it indicates that there is a valid copy of the corresponding Cache Line, otherwise there is no valid copy.

58: The second processor provides the Cache Line data to the first processor.

The second processor may send a bus read transaction response to the first processor, where the response carries a valid data copy corresponding to the Cache Line, that is, provides Cache Line data.

59: The first processor broadcasts the send bus read transaction. That is, the existing Cache read-miss process is executed.

Wherein, the broadcasted bus read transaction may be directly broadcasted when the first processor determines that there is no matching Tag; or,

It may also be that, when there is no valid Cache Line data copy in the second processor, the second processor sends a bus read transaction response to the first processor, which indicates that there is no valid Cache Line in the second processor copy of the data or other indication information to trigger the first processor to broadcast the bus read transaction. or,

It can also be that when there is no valid data copy of the Cache Line in the second processor, the second processor does not respond, and when the first processor does not receive a response within the set time, it broadcasts the sending bus read transaction.

After the above processing, the following uses the Modified Shared Invalid (MSI) protocol as an example to illustrate the state changes of the Cache.

The write invalidation protocol is to ensure that the processor has exclusive access to the data item before the processor writes the data, and it invalidates other copies when performing the write operation. The MSI protocol is a write invalidation protocol, which uses three states to distinguish the state of the CacheLine, which are:

M: Modified status. This state indicates that the Cache Line has been modified by the processor, the data in it is the only correct data in the system, the corresponding data in the main memory is outdated, and the copies of the Cache Line in other Cache are also invalid.

S: shared state. This state indicates that there may be valid copies of the Cache Line in other Caches.

I: Invalid state. This status indicates: the data in this Cache Line is invalid.

Among them, when the Cache Line is in the M or S state, the value of the corresponding status bit (valid bit) is 1, indicating that it is in a valid state; when the Cache Line is in the I state, the value of the corresponding status bit (valid bit) is 0, Indicates an invalid state.

The MSI state of the Cache Line is not only affected by the read and write operations of the memory of the local processor, but also by the read and write operations of the memory of other processors on the shared bus.

Referring to FIG. 6 , it shows the influence of the local processor memory read and write operations on the MSI state of the Cache Line. Among them, when a read is hit, the state of the Cache Line can only be in the M or S state. At this time, there is no need to send a bus transaction, and the data is provided by the Cache, and the state of the Cache Line remains unchanged.

When the read is missing, it may be because the data to be accessed is not in the Cache, that is, when the Tag does not match, or the read miss may also be because the data to be accessed is in the Cache but is in an invalid state. At this time, a bus read transaction needs to be sent. Get data and set the state of Cache Line to S state.

When a write hits, if the hit is a Cache Line in the M state, the CacheLine is directly updated, and the state of the CacheLine remains unchanged; if the write hits a Cache Line in the S state, it is necessary to send a bus write invalid transaction broadcast to make other caches The copy of the data block is invalid, and then the CacheLine is updated, and the state of the Cache Line changes to the M state.

When writing is missing, it may be because the data to be accessed is not in the Cache, or it may be because the data to be accessed is in the Cache but is in an invalid state. At this time, it is necessary to send a bus exclusive read transaction broadcast to obtain and update the data, and set the CacheLine Set to M state.

Different from the prior art, the prior art will broadcast the bus read transaction regardless of which of the above two read misses, but in the embodiment of the present invention, when the data to be accessed is in the Cache but is in an invalid state, the read miss , the bus read transaction will be unicast. The destination processor of the unicast is the processor recorded in the data area of the CacheLine mentioned above.

Referring to FIG. 7 , it shows the influence of the processor memory read and write operations on the bus on the MSI state of the Cache Line.

When the local Cache does not contain the Cache Line specified by the bus read transaction or the bus write transaction, or although it is included but the Cache Line is in the I state, the local Cache does not respond or respond to trigger the broadcast of the processor that sends the bus read transaction Bus read transaction.

When the local Cache contains the Cache Line specified by the bus read transaction and the Cache Line is in the S state, the local Cache will respond to the bus read transaction and provide data.

When the local Cache contains the Cache Line specified by the bus read transaction and the Cache Line is in the M state, the local Cache will provide data in response to the bus read transaction, and then set the local Cache Line to the S state.

When the local Cache contains the Cache Line specified by the bus write invalid transaction, the state of the Cache Line is set to be invalid.

When the local Cache contains the Cache Line specified by the bus mutually exclusive read transaction and the CacheLine is in the M state, the local Cache will provide data in response to the bus mutually exclusive read transaction, and then set the local Cache Line to the I state.

Different from the prior art, the above-mentioned bus read transaction is sent by unicast instead of the broadcast sending method in the prior art.

Taking the MSI protocol above as an example, the existing technologies such as the Modified Exclusive Shared Invalid (MESI) protocol and the Modified Owned Exclusive Shared Invalid (MOESI) protocol are also applicable to the above-mentioned tag matching but data In the case of read misses caused by invalidity, unicast transmission is adopted.

FIG. 8 is a schematic structural diagram of an embodiment of a processing device when reading is missing in the present invention. The device can be the above-mentioned first processor. The device 80 includes a generation module 81, an acquisition module 82 and a unicast module 83; the generation module 81 uses When generating address information, the address information includes Cache Tag; the obtaining module 82 is configured to obtain the information of the second processor recorded in the first Cache Line when it is determined that the first Cache Line exists, and the first The Tag of the Cache Line is identical to the value of the Cache Tag, and the status bit indicates an invalid state; the unicast module 83 is used to unicast and send the bus read transaction to the second processor according to the information of the second processor, The second processor is configured to provide the data of the first Cache Line when storing a valid copy of the data of the first Cache Line.

Optionally, the device can also include:

A recording module, configured to record the information of the second processor in the first CacheLine after the state bit of the first Cache Line is in an invalid state, and the second processor stores the information of the first Cache for the last time Handler for Line's data copy.

Optionally, the information of the second processor is recorded in the data area of the first Cache Line.

Optionally, the device can also include:

A receiving module, configured to receive the bus read transaction response sent by the second processor, wherein when the second processor stores a valid copy of the data of the first Cache Line, the bus read transaction response includes the The data of the first Cache Line, or, when the first processor does not store a valid copy of the data of the first Cache Line, the bus read transaction response is used to instruct the first processor to broadcast on the bus send a bus read transaction; or,

The broadcast module is used to broadcast and send the bus read transaction on the bus if the bus read transaction response sent by the second processor is not received within the set time, and the read transaction response is not stored in the second processor A valid data copy of the first Cache Line is not sent.

Referring to FIG. 9 , it is a schematic structural diagram of another device provided by an embodiment of the present invention. The device may be the above-mentioned first processor, and the first processor 90 includes a transceiver 91, a CPU 92, and a cache memory (Cache) 93, and a bus 94 connected to the above-mentioned modules, the bus 94 may include a data bus, an address bus, a status bus, and the like. The CPU is used to generate address information according to user input received through the transceiver and the bus, where the address information includes a Cache Tag; For the information of the processor, the Tag of the first Cache Line is the same as the value of the Cache Tag, and the status bit indicates an invalid status. The CPU may also unicast the bus read transaction to the second processor through the transceiver and the bus according to the information of the second processor, so that the second processor stores the valid first Cache Line When copying data, provide the data of the first Cache Line. Among them, CacheLine is located in the Cache. It can be understood that the processor may also include other modules, such as an arithmetic logic unit, a clock generator, a comparator, a timer, a reset circuit, a modulator, and the like.

It should be noted that the devices shown in FIG. 8 and FIG. 9 can be used to implement any method related to the first processor provided by the above method embodiments, and the description of related terms and related implementation methods are the same as the above method embodiments, I won't repeat them here.

In this embodiment, by recording the information of the processor that stored its copy last time in the Cache Line, and sending the bus broadcast transaction to the corresponding processor by unicast according to the information of the processor when the read is missing, the problems caused by the broadcast transmission mode can be avoided. Reduce power overhead.

FIG. 10 is a schematic structural diagram of another embodiment of the processing device for read misses in the present invention. The device may be the above-mentioned second processor. The device 100 includes a receiving module 101 and a sending module 102; the receiving module 101 is used to receive the first A bus read transaction sent by a processor unicast, the bus read transaction is sent by the first processor according to the information of the second processor recorded in the first Cache Line, the Tag of the first Cache Line is the same as the The Cache Tag values in the address information generated by the first processor are the same, and the status bit indicates an invalid state; the sending module 102 is configured to send to the first processor when storing a valid copy of the data of the first Cache Line Provide the data of the first Cache Line.

Optionally, the sending module is also used for:

When there is no valid data copy of the first Cache Line stored, sending a bus read transaction response for instructing the first processor to broadcast a bus read transaction on the bus to the first processor; or,

When there is no effective data copy of the first Cache Line stored, the bus read transaction response is not sent, so that the first processor does not receive the bus read transaction response sent by the second processor within the set time , broadcast a bus read transaction on the bus.

Referring to FIG. 11 , it is a schematic structural diagram of another device provided by an embodiment of the present invention. The device may be the above-mentioned second processor, and the second processor 110 includes a transceiver 111 , a CPU 112 , and a cache memory (Cache) 113, and a bus 114 connected to the above-mentioned modules, the bus 114 may include a data bus, an address bus, a status bus, and the like. The transceiver is used to receive the bus read transaction sent by the first processor in unicast, the bus read transaction is sent by the first processor according to the information of the second processor recorded in the first Cache Line, and the first Cache Line The Tag of Line is the same as the Cache Tag value in the address information generated by the first processor, and the status bit indicates an invalid state; When copying data, provide the data of the first Cache Line to the first processor. It can be understood that the processor may also include other modules, such as an arithmetic logic unit, a clock generator, a comparator, a timer, a reset circuit, a modulator, and the like.

It should be noted that the devices shown in FIG. 10 and FIG. 11 can be used to implement any method related to the second processor provided in the above method embodiments, and the description of related terms and related implementation methods are the same as the above method embodiments, I won't repeat them here.

In this embodiment, by recording the information of the processor that stored its copy last time in the Cache Line, and sending the bus broadcast transaction to the corresponding processor by unicast according to the information of the processor when the read is missing, the problems caused by the broadcast transmission mode can be avoided. Reduce power overhead.

FIG. 12 is a schematic structural diagram of an embodiment of a system for processing read misses according to the present invention. The system 120 includes a first processor 121 and a second processor 122 ; refer to FIG. 8 or FIG. 9 for the first processor 121 . Refer to FIG. 10 or FIG. 11 for the second processor 122 .

In this embodiment, by recording the information of the processor that stored its copy last time in the Cache Line, and sending the bus broadcast transaction to the corresponding processor by unicast according to the information of the processor when the read is missing, the problems caused by the broadcast transmission mode can be avoided. Reduce power overhead.

Those skilled in the art can clearly understand that for the convenience and brevity of description, only the division of the above-mentioned functional modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional modules according to needs. The internal structure of the device is divided into different functional modules to complete all or part of the functions described above. For the specific working process of the above-described system, device, and unit, reference may be made to the corresponding process in the foregoing method embodiments, and details are not repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be Incorporation may either be integrated into another system, or some features may be omitted, or not implemented. In another point, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

If the integrated unit is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or part of the contribution to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , including several instructions for enabling a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk, and other media that can store program codes. .

As mentioned above, the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still understand the foregoing The technical solutions described in each embodiment are modified, or some of the technical features are equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the application.

Claims (13)

1. A processing method when a read is missing, it is characterized in that, comprising: The first processor generates address information, and the address information includes a cache tag Cache Tag; When the first processor determines that the first cache memory line Cache Line exists, it obtains the information of the second processor recorded in the first Cache Line, and the tag Tag of the first Cache Line is related to the Cache Line Tag values are the same, and the state bit indicates an invalid state, and the second processor is the processor that stored the data copy of the first CacheLine last time; The first processor unicasts the bus read transaction to the second processor according to the information of the second processor, so that the second processor is storing a valid data copy of the first Cache Line , provide the data of the first Cache Line. 2. The method according to claim 1, further comprising: After the status bit of the first Cache Line is invalid, the first processor records the information of the second processor in the first Cache Line. 3. The method according to claim 1 or 2, wherein the information of the second processor is recorded in the data area of the first Cache Line. 4. The method according to claim 1 or 2, further comprising: The first processor receives the bus read transaction response sent by the second processor, wherein when the second processor stores a valid data copy of the first Cache Line, the bus read transaction response includes The data of the first Cache Line, or, when the second processor does not store a valid copy of the data of the first Cache Line, the bus read transaction response is used to indicate that the first processor is on the bus broadcast a bus read transaction; or, If the first processor does not receive the bus read transaction response sent by the second processor within the set time, it broadcasts and sends the bus read transaction on the bus, and the read transaction response is not received by the second processor. It is not sent when storing the valid data copy of the first Cache Line. 5. A processing method for reading deletions, comprising: The second processor receives the bus read transaction sent by the first processor unicast, the bus read transaction is sent by the first processor according to the information of the second processor recorded in the first cache memory line Cache Line, The tag Tag of the first Cache Line is the same as the cache memory tag CacheTag value in the address information generated by the first processor, and the status bit indicates an invalid state, and the second processor stores the The processor of the data copy of the first CacheLine; The second processor provides the data of the first Cache Line to the first processor when storing a valid copy of the data of the first Cache Line. 6. The method according to claim 5, further comprising: When the second processor does not store a valid data copy of the first Cache Line, it sends a bus read transaction for instructing the first processor to broadcast a bus read transaction on the bus to the first processor response; or, When the second processor does not store a valid data copy of the first Cache Line, it does not send a bus read transaction response, so that the first processor does not receive the second processor within a set time The sent bus read transaction response broadcasts the sent bus read transaction on the bus. 7. A processing device for missing reads, comprising: A generating module, configured to generate address information, which includes a cache tag Cache Tag; An acquisition module, configured to acquire the information of the second processor recorded in the first Cache Line when it is determined that there is a first cache memory line Cache Line, the tag Tag of the first Cache Line and the Cache Tag The values are the same, and the state bit indicates an invalid state, and the second processor is the processor that stored the data copy of the first CacheLine last time; A unicast module, configured to unicast and send a bus read transaction to the second processor according to the information of the second processor, so that the second processor is storing a valid data copy of the first Cache Line , provide the data of the first Cache Line. 8. The device according to claim 7, further comprising: The recording module is configured to record the information of the second processor in the first Cache Line after the status bit of the first Cache Line is invalid. 9. The device according to claim 7 or 8, wherein the information of the second processor is recorded in the data area of the first Cache Line. 10. The device according to claim 7 or 8, further comprising: A receiving module, configured to receive the bus read transaction response sent by the second processor, wherein when the second processor stores a valid copy of the data of the first Cache Line, the bus read transaction response includes the The data of the first CacheLine, or, when the second processor does not store a valid copy of the data of the first Cache Line, the bus read transaction response is used to instruct the processing device to broadcast the send bus on the bus read transaction; or, The broadcast module is used to broadcast and send the bus read transaction on the bus if the bus read transaction response sent by the second processor is not received within the set time, and the read transaction response is not stored in the second processor A valid data copy of the first Cache Line is not sent. 11. A processing device for reading loss, characterized in that it comprises: The receiving module is configured to receive the bus read transaction sent by the first processor in unicast, and the bus read transaction is sent by the first processor according to the information of the second processor recorded in the first cache memory line Cache Line , the tag Tag of the first Cache Line is the same as the cache memory tag Cache Tag value in the address information generated by the first processor, and the status bit indicates an invalid state, and the second processor stores A processor of the data copy of the first Cache Line; A sending module, configured to provide the first processor with the data of the first Cache Line when storing a valid copy of the data of the first Cache Line. 12. The device according to claim 11, wherein the sending module is also used for: When there is no valid data copy of the first Cache Line stored, sending a bus read transaction response for instructing the first processor to broadcast a bus read transaction on the bus to the first processor; or, When there is no effective data copy of the first Cache Line stored, the bus read transaction response is not sent, so that the first processor does not receive the bus read transaction response sent by the second processor within the set time , broadcast a bus read transaction on the bus. 13. A processing system for reading deletions, comprising: An apparatus as claimed in any one of claims 7-10; and, Apparatus according to any one of claims 11-12.