CN103888147B - A kind of transformation from serial to parallel change-over circuit and converter and converting system - Google Patents
A kind of transformation from serial to parallel change-over circuit and converter and converting system Download PDFInfo
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- CN103888147B CN103888147B CN201410140970.1A CN201410140970A CN103888147B CN 103888147 B CN103888147 B CN 103888147B CN 201410140970 A CN201410140970 A CN 201410140970A CN 103888147 B CN103888147 B CN 103888147B
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Abstract
This application discloses a kind of transformation from serial to parallel change-over circuit, converter and converting system, wherein change-over circuit includes：1st toShift register group, selector group and parallel output register group, wherein n are odd number, and shift register group includes：First register and the second register, and the clock signal input terminal of the second register is provided with NOT gate.Foregoing circuit is got after serial input signals serial_data, and the positive edge of the first clock signal and anti-edge are synchronous respectively（n+1）/ 2 times, produce n+1 synchronizing signal, selector group is combined into n signal by selecting clock signal data_sel by n+1 synchronizing signal, it is last by output signal register by readout clock read_clk by n signal synchronism output after combination, n bit parallel datas are obtained, wherein the type of the first clock signal can also be able to be full-speed clock signal for half-speed clocks signal.
Description
Technical field
The application is related to Digital Signals technical field, and parallel output is turned more specifically to a kind of serial input
Logic circuit.
Background technology
In serial data communication, in order to save the bus used in data transmission procedure, data-signal is in transmitting procedure
In typically use serial mode, i.e.,：When data are sent, internal parallel data signal is converted to external series number by transmission circuit
It is believed that number, in transmitting terminal, using high-frequency clock sampling principle, the position data in parallel data are sent to transmission medium one by one
On, realize parallel-to-serial conversion.But it is due to the limitation of process speed, must be using parallel side when handling signal
Formula, so in receiving terminal, because the clock signal that transmitting terminal and receiving terminal are not shared carries out the synchronous of data, receiving terminal needs
Clock signal is recovered from the serial data stream received to realize simultaneously operating, and clock recovery circuitry is just responsible for going here and there
Recovered clock and recovery data in row data are extracted.The transformation from serial to parallel change-over circuit of rear class will recover data conversion again
Exported for parallel data.
Fig. 1 is the design drawing of transformation from serial to parallel change-over circuit in the prior art, when the fclk signals are full speed in Fig. 1
Clock signal, Seriai_data are serial input signals, the X bits represent that X register, the read_clk represent reading
Clock signal, the data<0>To data<x-1>Represent that parallel output signal, X bits represent X parallel output signal, can
See that transformation from serial to parallel change-over circuit of the prior art is generally based on what full-speed clock fclk was designed, wherein no matter odd number
Position or even bit data-signal, all only need to the shift register of the several numbers of corresponding positions, using finally with same reading when
Clock signal read_clk synchronously goes out the data-signal, wherein the cycle of the read clock signal read_clk is complete
X times of fast clock fclk, X is the positive integer not less than 1.
But if there is no full-speed clock fclk in circuit design process, then will be unable to realize that serial data signal is serial
With parallel conversion, this is directed to, how to realize that one kind does not need full-speed clock fclk to realize yet and turns serial data signal
The circuit of parallel data signal is changed to, as those skilled in the art's urgent problem to be solved.
The content of the invention
In view of this, the application provides a kind of change-over circuit for not needing full-speed clock also to realize transformation from serial to parallel, turned
Parallel operation and converting system.
To achieve these goals, it is proposed that scheme it is as follows：
A kind of transformation from serial to parallel change-over circuit, including：
1st toShift register group, the n is odd number, and the shift register group includes：First register and
Second register, the clock signal input terminal of second register is provided with NOT gate, the described 1st toShift register
Group is sequentially connected in series, wherein the output end of upper first register is connected with the input of latter the first register, upper one
The output end of second register is connected with latter the second register input；
Selector group, the selector group includes n selector, and the selector includes first input end, the second input
End and selection signal input, the selection signal input are used to obtain selection clock signal；
Parallel output register group, the parallel output register group includes n output register；
Described 1st toFirst register output end of shift register group and the selector in the selector group
First input end be connected, the second register output end is connected with the second input of the selector；
Wherein described second toFirst register output end of shift register group also with the selector
Two inputs are connected, first input end of second output end also with the selector is connected；And each selector and one
Individual shift register group is connected, and an input of the selector is connected with the first register output end, another input
End is connected with the second register output end.
It is preferred that, in above-mentioned transformation from serial to parallel change-over circuit, the clock signal of the output register is believed for readout clock
Number, the clock signal of the shift register group is the first clock signal, and the cycle of the readout clock signal is described first
Clock signal periodTimes.
It is preferred that, in above-mentioned transformation from serial to parallel change-over circuit, the shift register group specifically for：
The output signal of first register output end and the rising edge synch of the first clock signal, the second register output end
The signal of output is synchronous with the trailing edge of the first clock signal.
It is preferred that, in above-mentioned transformation from serial to parallel change-over circuit, the selector specifically for：
When the selection clock signal is high level, by rising edge synch, output state is changed into output by the selection
The signal that device first input end is obtained, it is synchronous by trailing edge when selection clock signal is low level, output state be changed into output by
The signal that the input of selector second is obtained.
It is preferred that, in above-mentioned transformation from serial to parallel change-over circuit, first and second register is additionally provided with shift LD
Device group controlling switch, the shift register group controlling switch is used for control data digit.
It is preferred that, in above-mentioned transformation from serial to parallel change-over circuit, the cycle of the selection clock signal is the first clock signal
N times.
It is preferred that, in above-mentioned transformation from serial to parallel change-over circuit, the cycle of the selection clock signal is readout clock signal
2 times of cycle.
A kind of transformation from serial to parallel converter, the change-over circuit of the converter can be changed for above-mentioned any one is disclosed
Circuit.
The change-over circuit of converter can be public for above-mentioned any one in a kind of transformation from serial to parallel converting system, the system
The change-over circuit opened.
It can be seen from above-mentioned technical scheme that, change-over circuit disclosed in the present application gets the serial input signals
After Seriai_data, the positive edge of first clock signal and anti-synchronous (n+1)/2 time of edge difference produce n+1 and synchronously believed
Number, the selector group is combined into n signal by selecting clock signal data_sel by the n+1 synchronizing signal, finally
N signal synchronism output after the combination is obtained by the readout clock read_clk by the output signal register
To n bit parallel datas, wherein the type of first clock signal can also be able to be full-speed clock letter for half-speed clocks signal
Number.
Brief description of the drawings
, below will be to embodiment or existing in order to illustrate more clearly of the embodiment of the present application or technical scheme of the prior art
There is the accompanying drawing used required in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of application, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other accompanying drawings are obtained according to these accompanying drawings.
The design drawing of Fig. 1 transformation from serial to parallel change-over circuits in the prior art；
Fig. 2 is the structure chart of transformation from serial to parallel change-over circuit disclosed in the embodiment of the present application；
Fig. 3 is the structure chart of the shift register group；
Fig. 4 is that n disclosed in the embodiment of the present application is equal to each clock signal in change-over circuit when 3, clk is half-speed clocks
Between graph of a relation；
Fig. 5 is the simulation result figure of the circuit of the 9 Half Speed transformation from serial to parallel designed using the present invention.
Embodiment
Electricity is changed in order to provide a kind of transformation from serial to parallel that can be also applied under the conditions of without full-speed clock fclk
Road, this application discloses a kind of transformation from serial to parallel change-over circuit and converter and converting system, is now specifically described as follows：
Below in conjunction with the accompanying drawing in the embodiment of the present application, the technical scheme in the embodiment of the present application is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only some embodiments of the present application, rather than whole embodiments.It is based on
Embodiment in the application, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of the application protection.
Fig. 2 is the structure chart of transformation from serial to parallel change-over circuit disclosed in the embodiment of the present application, and Fig. 3 is the shift register
The structure chart of group, referring to Fig. 2 and Fig. 3, wherein when Seriai_data is that serial input signals, the clk are first in the figure
Clock signal, the Data_sel represent that selection clock signal, the read_clk represent readout clock signal.
Referring to Fig. 2, the change-over circuit includes input module 1, selector group 2, parallel output register group 3, specifically connects
Binding structure is as follows：
The input module includes the 1st to theShift register group, wherein n are odd number, shown in Figure 3, described to move
Bit register group includes：First register 101 and the second register 102, the clock signal input terminal of second register 102
It is provided with NOT gate, the described 1st toShift register group is sequentially connected in series, wherein the output end of upper first register 101
It is connected with the input of latter the first register 101, the output end of upper second register 102 is deposited with latter second
The input of device 102 is connected；
Selector group 2, the selector group 2 includes n selector, and the selector includes first input end da, second
Input db and selection signal input, the selection signal input are described for acquisition selection clock signal data_sel
Selector be used to obtaining by the first clock signal synchronization to data, and according in selection clock signal data_sel selections
Rise synchronous along synchronous or trailing edge；
Parallel output register group 3, the parallel output register group 3 includes n output register；
Described 1st toThe output end of first register 101 of shift register group and the choosing in the selector group
The first input end da for selecting device is connected, the output end of the second register 102 is connected with the second input db of the selector；
Wherein described second toThe output end of first register 101 of shift register group also with the selector
The second input db be connected, the second output end is also connected with the first input end da of the selector；And each is selected
Device is only connected with a shift register group, and an input of the selector is connected with the first register output end, separately
One input is connected with the second register output end.
Referring to technical scheme disclosed in the above embodiments of the present application, the serial input signals are got in such scheme
After Seriai_dataa, the positive edge of first clock signal and anti-synchronous (n+1)/2 time of edge difference produce n+1 and synchronously believed
Number, the selector group is combined into n signal by selecting clock signal data_sel by the n+1 synchronizing signal, finally
N signal synchronism output after the combination is obtained by the readout clock read_clk by the output signal register
To n bit parallel datas, wherein the type of first clock signal can also be able to be full-speed clock letter for half-speed clocks signal
Number, and when first clock signal is full-speed clock signal, the technical scheme that the application is provided is compared to traditional skill
For art scheme, power consumption is lower, and when first clock signal is half-speed clocks signal, is capable of the frequency of normal work
It is higher, it is twice when clock signal is full-speed clock signal, it is seen that the application is using Half Speed processing mode to described serial defeated
Enter signal to be handled, wherein Half Speed processing substantial data rate bit rate and clock speed identical processing mode.
The relation of the readout clock signal read_sel and the first clock signal clk wherein in above-described embodiment
It can be defined as：The cycle of the readout clock signal read_sel is the first clock signal clk cyclesTimes, for example
Optionally, the n is 3, then the cycle of the readout clock signal read_sel is the first clock signal clk cycles
1.5 again.
The selection clock signal data_sel and readout clock signal read_sel relation can be defined as：Institute
Once inside out occurs for each trailing edge for stating selection clock signal read_sel in the readout clock signal data_sel, its
Essential Action is to produce data by readout clock to select signal.
In the change-over circuit disclosed in the embodiment of the present application, the shift register group can be for single first
Register and the second register, of course for layout, it is easy to connect, the shift register group can also be to be encapsulated in one piece
First register and the second register.
In order to better improve the change-over circuit it is new can, the working method of register described in above-described embodiment can be with
Including：When the selection clock signal data_sel is high level, output state is changed into output and obtained by first input end da
Signal, when selection clock signal data_sel is low level, output state is changed into the letter that output is obtained by the second input db
Number.
The negligible amounts for the shift register group that may be needed in some cases, might not use all shiftings
Bit register group, so user uses for convenience, first register and the second register disclosed in above-described embodiment are also
Shift register group controlling switch can be provided with, when the shift register groups of whole need not be used, corresponding the is controlled
The shift register group controlling switch of one register and the second register disconnects.
The break-make of wherein described shift register group controlling switch can be controlled by controller, and the controller passes through
Shift register group controlling switch to different shift register groups exports different control signals, to reach the selection conversion
The problem of quantity of shift register group described in circuit.
Fig. 4 is that the n is equal to the graph of a relation between each clock signal in change-over circuit when 3, clk is half-speed clocks.
Wherein described ddrclk represents half-speed clocks signal, and the ddrclk synch_ronism represent that the displacement is posted
Storage group by according to the clock signal to the serial input signals processing after export to the signal waveforms of selector,
merge(d<0>、d<1>、d<2>) represent the selector according to input signal of the selection clock signal to the selector
Output after being handled is to the signal waveforms of the parallel output shift register group, the output (data<0>、
data<1>、data<2>) represent the parallel output shift register group according to signal of the readout clock signal to input
The waveform signal figure of parallel output after being handled.
Fig. 5 is the simulation result figure of the circuit of the 9 Half Speed transformation from serial to parallel designed using the present invention.
S_dout is din<0>Turning string by a parallel-by-bit of ideal 9 after the design is converted into 9 bit parallel datas
The result arrived after row.
Accurate conversion can be reached referring to the circuit of the visible 9 Half Speed transformation from serial to parallel disclosed in the present application of Fig. 5
Effect.
Changed corresponding to above-mentioned change-over circuit disclosed herein as well is a kind of transformation from serial to parallel for applying above-mentioned change-over circuit
Device, the change-over circuit of the specific converter can include any one above-mentioned disclosed change-over circuit of the application.
Equally on the basis of the converter, disclosed herein as well is a kind of transformation from serial to parallel converting system, described turn
The system of changing can include a kind of above-mentioned any disclosed change-over circuit.
Finally, in addition it is also necessary to explanation, herein, such as first and second or the like relational terms be used merely to by
One entity or operation make a distinction with another entity or operation, and not necessarily require or imply these entities or operation
Between there is any this actual relation or order.Moreover, term " comprising ", "comprising" or its any other variant meaning
Covering including for nonexcludability, so that process, method, article or equipment including a series of key elements not only include that
A little key elements, but also other key elements including being not expressly set out, or also include be this process, method, article or
The intrinsic key element of equipment.In the absence of more restrictions, the key element limited by sentence "including a ...", is not arranged
Except also there is other identical element in the process including the key element, method, article or equipment.
The embodiment of each in this specification is described by the way of progressive, and what each embodiment was stressed is and other
Between the difference of embodiment, each embodiment identical similar portion mutually referring to.
The foregoing description of the disclosed embodiments, enables professional and technical personnel in the field to realize or use the application.
A variety of modifications to these embodiments will be apparent for those skilled in the art, as defined herein
General Principle can in other embodiments be realized in the case where not departing from spirit herein or scope.Therefore, the application
The embodiments shown herein is not intended to be limited to, and is to fit to and principles disclosed herein and features of novelty phase one
The most wide scope caused.
Claims (6)
1. a kind of transformation from serial to parallel change-over circuit, it is characterised in that including：
1st toShift register group, the n is odd number, and the shift register group includes：First register and second
Register, the clock signal input terminal of second register is provided with NOT gate, the described 1st toShift register group according to
Secondary series connection, wherein the output end of upper first register is connected with the input of latter the first register, upper one second
The output end of register is connected with latter the second register input；
Selector group, the selector group includes n selector, the selector including first input end, the second input and
Selection signal input, the selection signal input is used to obtain selection clock signal；
Parallel output register group, the parallel output register group includes n output register；
Described 1st toThe of first register output end of shift register group and the selector in the selector group
One input is connected, the second register output end is connected with the second input of the selector；
Wherein described second toSecond input of the first register output end of shift register group also with the selector
End is connected, first input end of the second register output end also with the selector is connected；And each selector and one
Individual shift register group is connected, and an input of the selector is connected with the first register output end, another input
End is connected with the second register output end；
The clock signal of the output register is readout clock signal, when the clock signal of the shift register group is first
Clock signal, the cycle of the readout clock signal is first clock signal periodTimes, the selection clock signal
Cycle is n times of the first clock signal, and the cycle of the selection clock signal is 2 times of the cycle of readout clock signal.
2. according to the transformation from serial to parallel change-over circuit in claim 1, it is characterised in that the shift register group is specific
For：
The output signal of first register output end and the rising edge synch of the first clock signal, the output of the second register output end
Signal it is synchronous with the trailing edge of the first clock signal.
3. according to the transformation from serial to parallel change-over circuit in claim 1, it is characterised in that the selector specifically for：
When the selection clock signal is high level, by rising edge synch, output state is changed into output by the selector the
The signal that one input is obtained, synchronous by trailing edge when selection clock signal is low level, output state is changed into output by described
The signal that the input of selector second is obtained.
4. according to the transformation from serial to parallel change-over circuit in claim 1, it is characterised in that first and second register
Shift register group controlling switch is additionally provided with, the shift register group controlling switch is used for control data digit.
5. a kind of transformation from serial to parallel converter, it is characterised in that it is any that the change-over circuit of the converter includes claim 1-4
Change-over circuit in one.
6. a kind of transformation from serial to parallel converting system, it is characterised in that the change-over circuit of converter includes being right in the system
It is required that change-over circuit disclosed in 1-5 any one.
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| CN112865805B (en) * | 2019-11-27 | 2024-04-05 | 京东方科技集团股份有限公司 | Data transmission circuit, display device and data transmission method |
| CN111064912B (en) * | 2019-12-20 | 2022-03-22 | 江苏芯盛智能科技有限公司 | Frame format conversion circuit and method |
| CN111130560B (en) * | 2019-12-30 | 2024-11-29 | 西安智多晶微电子有限公司 | High-speed serial-parallel conversion interface word synchronization method and circuit for FPGA chip |
| CN113517894B (en) * | 2021-07-14 | 2022-07-08 | 上海安路信息科技股份有限公司 | Serial-parallel conversion circuit |
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