CN103887277A - Packaging Structure And Method Of Assembling A Packaging Structure - Google Patents

Abstract

The invention relates to a packaging structure and an assembly method thereof. A method of assembling a package structure is provided, the method comprising directly electrically interconnecting respective active surfaces of first and second chips in a face-to-face arrangement, electrically connecting at least one of the respective sidewalls of the first and second chips to interconnecting to the common chip; and laterally orienting the respective active surfaces of the first and second chips relative to the common chip.

Description

Package structure and assembly method thereof

technical field

The present invention relates to packaging structures. More specifically, the present invention relates to packaging structures having direct electrical connections between the respective active surfaces of first and second chips and between at least one of the first and second chips and a common chip.

Background technique

As the size of complementary metal-oxide-semiconductor (CMOS) devices shrinks, chip packaging methods are investigated to improve system performance. In some cases, the stack of chips includes a plurality of chips arranged in parallel to form a module with a common chip disposed on one side of the module. The block is then connected to the circuit board along the side of the block opposite the common chip.

In chip stacks that include a common chip and multiple chips arranged in side-by-side configurations, large amounts of silicon are packaged and interconnected. However, interconnections across a common (ie, top) chip are limited by corner crossing density. Additionally, power delivery to a common chip is also challenging because the direction of power transfer is oriented vertically along the vertical length of each of the multiple chips.

Contents of the invention

According to one embodiment of the present invention, a package structure is provided, and the package structure includes first and second chips, at least one surface of each of the first and second chips is an active surface; and a common chip, At least one of the first and second chips is electrically interconnected to the common chip. The respective active surfaces of the first and second chips are directly electrically interconnected to each other in a face-to-face arrangement and are oriented laterally relative to the common chip.

According to another embodiment, there is provided a package structure, and the package includes first and second chips, each of the first and second chips has two opposing surfaces and extends between the two opposing surfaces. A body of four sidewalls, at least one of the two opposing surfaces of each of the first and second chips is an active surface; and a common chip, at least one of the respective sidewalls of the first and second chips One is electrically interconnected to the common chip. The respective active surfaces of the first and second chips are directly electrically interconnected to each other in a face-to-face arrangement and are laterally oriented relative to the common chip.

According to another embodiment, a package structure is provided, and the package structure includes first and second chip groups, each chip group includes at least first and second chips, and the first and second chips of each chip group At least one surface of each of which is an active surface, the respective active surfaces of the first and second chips of each chip set are directly electrically interconnected to each other in a face-to-face arrangement; and the bonding layer, the first and second chip sets are attached to each other by a tie layer.

According to another embodiment, a package structure is provided, and the package structure includes first and second chip groups, each chip group includes at least first and second chips, and the first and second chips of each chip group At least one surface of each of which is an active surface, the respective active surfaces of the first and second chips of each chip set are directly electrically interconnected to each other in a face-to-face arrangement; and the bonding layer, the first and second chip sets are attached to each other by a tie layer.

According to another embodiment, there is provided a method of assembling a package structure comprising directly electrically interconnecting respective active surfaces of first and second chips in a face-to-face arrangement, placing at least one of the first and second chips The respective sidewalls are electrically interconnected to the common chip, and the respective active surfaces of the first and second chips are laterally oriented relative to the common chip.

Additional features and advantages will be realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with advantages and characteristics, refer to the description and to the drawings.

Description of drawings

The claims at the conclusion of the specification point out and claim what is regarded as the invention. The foregoing and other advantages of the invention will become apparent from the ensuing detailed description in conjunction with the accompanying drawings.

FIG. 1 shows a perspective view of a packaging structure according to an embodiment;

Fig. 2 shows a side view of the packaging structure of Fig. 1 with the power conversion chip facing upward;

Figure 3 shows a perspective view of a chipset according to an embodiment;

Figure 4 shows a perspective view of the chipset of Figure 3 with an additional filler;

Fig. 5 shows a top view of a packaging structure according to another embodiment;

Figure 6 shows a perspective view of a packaging structure according to another embodiment;

Figure 7 shows a top view of a chipset with first and second chips and additional chips;

Figure 8 shows a perspective view of a first processing operation for assembling the package structure;

Figure 9 shows a perspective view of a second processing operation for assembling the package structure;

Figure 10 shows a perspective view of a third processing operation for assembling the package structure; and

Figure 11 shows a perspective view of a fourth processing operation for assembling the package structure.

Detailed ways

In a chip stack like a 4Di chip stack, a large amount of silicon in the form of multiple chips arranged in parallel with a normal (top) chip is packaged and interconnected to provide an area multiplication of about 8.5X or more, with 57.6k connections for both power and communication between chip stacks and common chips. However, interconnection through the common chip is limited by corner crossing density and power delivery to the common chip presents challenges because power delivery is vertically oriented along the vertical length of each of the multiple chips.

According to embodiments described herein, there is provided a chip stack and embodied as a 4Di chip stack comprising groups arranged in at least active surface to active surface (i.e., face-to-face) with conductive elements disposed therebetween (such as small pitch microbumps or microconnections) of multiple chips. This provides a relatively high-bandwidth connection between pairs of chips (or, more specifically, groups of two or more chips) and can be used, for example, to convert power conversion or memory chips or contain components such as decoupling capacitors or inductors The integrated passive components of the chip are attached to the processor chip. This also effectively doubles the active area of the chip that can be tightly electrically interconnected with other modules. In addition, the chip stack provides at least 28.8k connections between chips per chip pair or 30 or more chip pairs, for a total of at least 864k connections for the chip stack. In addition, the use of facing chip pairs is advantageous because of the symmetrical arrangement so that any stress-induced bowing is compensated.

Referring now to FIGS. 1 and 2 , a package structure 10 is provided as an exemplary die stack. The package structure 10 includes at least one or more pairs of the first chip 11, the second chip 12, and in some cases, the common chip 12, which is connected with each of the first and second chips 11 and 12 of one or more chip pairs. At least one of the is connectable. At least one of the first and second chips 11 and 12 includes at least one of a voltage conversion device 14 , a control device 15 and a memory device 16 . At least one of the first and second chips 11 and 12 further includes a power conversion chip 17 configured to convert the input voltage into a first voltage range to supply power to the other of the first and second chips 11 and 12 and The input voltage is converted to a second voltage range to supply power to the common chip 13 when the common chip 13 is used.

The first chip 11 includes a first chip body 110 having two opposing surfaces 111 at least one of which is an active surface 112 and four sidewalls 113 . Four side walls 113 extend between the two opposite surfaces 111 . The second chip 12 similarly includes a second chip body 120 having two opposite surfaces 121 at least one of which is an active surface 122 and four sidewalls 123 . Likewise, four side walls 123 extend between the two opposing surfaces 121 . While the first and second chips 11 and 12 are shown as rectangular, it should be understood that this is exemplary only and that other configurations are possible. For the exemplary rectangular case, the first and second chips 11 and 12 are oriented such that one of the sidewalls 113 and 123 is the “top” sidewall 113 , 123 and the opposite one is the “bottom” sidewall 113 , 123 .

For each pair of chips, at least one of the respective sidewalls 113 and 123 of the first and second chips 11 and 12 (i.e., the "top" sidewalls 113, 123) passes through, for example, a 25 micrometer (μm) pitch corner intersection electrical are interconnected (or at least configured to be electrically interconnected) to the active surface 130 of the common chip 13 . That is, in one particular configuration, corner crossings are only provided between the first chip 11 or the second chip 12 and the common chip 13 via 25 micron pitch corner crossings, so only one chip is directly connected to the common chip 13 and the other chips are indirectly connected. Connect to common chip 13.

In addition, the respective active surfaces 112 and 122 of the first and second chips 11 and 12 are directly electrically interconnected to each other in an active surface to active surface arrangement (hereinafter referred to as a "face-to-face" arrangement). The respective active surfaces 112 and 122 of the first and second chips 11 and 12 are oriented laterally with respect to the plane of the active surface 130 of the common chip 13 . can be between, for example, the first level packaging substrate (see reference number 201 of FIG. An array 20 of controllable collapse chip connections (C4) is provided between them. Wider pitch corner crossings, eg about 100 micron pitch, are provided to electrically interconnect the active surfaces 112 and 122 of the first and second chips 11 and 12 to the corresponding bottom sidewalls 113 and 123 and the C4 array 20 .

A warp in one of the first and second chips 11 and 12 can be compensated for by a warp in the other of the first and second chips 11 and 12 . Alternatively, the curvature may be corrected or strained by the other of the first and second chips 11 and 12 .

Between the first and second chips 11 and 12 at least one microbump 18 or microconnection may be distributed. For purposes of clarity and brevity, non-limiting microprotrusion 18 embodiments will be described herein, but this is not meant to be limiting or exclusive. The microbumps 18 may be provided with eg a 50 μm pitch and may serve as electrical conductors by which the respective active surfaces 112 and 122 of the first and second chips 11 and 12 are electrically interconnected directly to each other. According to an embodiment, the micro-bumps 18 may also be inserted between the first and second chips 11 and 12 and the common chip 13 at a pitch of 75 μm.

For an embodiment, wherein at least one of the first and second chips 12 and 13 includes a power conversion chip 17 configured to convert the input voltage to the first and second or more voltage ranges to the first and second, respectively, The other of the second chips 11 and 12 and the common chip 13 supply power, and the first and second or more voltage ranges can be independent. Additionally, it should be understood that with this arrangement there will be very little resistive voltage (I x R) loss in the microbump 18 between the electrically interconnected first and second chips 11 and 12. For the common chip 13, the voltage or power conversion region 131 is provided along the "top" edge of the respective active chip surface 112 or 122 and below the region 131 on the respective active chip surface 112 or 122 of the power conversion chip 17 The power conversion region 132 of the facing chip in the pair for bonding (see FIG. 2 ). Therefore, the current transmitted to the common chip 13 can be transmitted through the corresponding corner intersections and micro-bumps 18 . The voltage conversion device 14 and the control device 15 can be used as, for example, a switched capacitor power supply or a buck converter power supply.

According to an embodiment, the first and second chips 11 and 12 may be provided in a chip pair. Chip pairs may be formed by bonding wafers together or by bonding individual wafers together. The wafer bonding method is suitable for high chip yields, since a defective chip on any wafer results in a defective chip pair. Using individual chip processes, known good wafers can be selected from each initial wafer and subsequently assembled. Depending on the assembly yield, it is desirable to test the chip pairs before they are assembled into chip stacks (ie, 4Di modules). This can be achieved in a separate chip process by making one chip slightly smaller than the other in at least one dimension, which results in a testable probe liner. The probe pads are then subsequently filled with additional silicon "filler" segments. By dicing the edge off one chip and using TCA (temporary chip attach; at small size pads) type bond pads to expose the test pads by removing the diced chip segments and then backfilling the silicon "filler" segments, Variations of this process can be used in wafer bonding situations. The filler edge should be slightly inward than the bottom chip edge to allow precision assembly of the 4Di chip stack.

3 and 4 illustrate an embodiment of the process described above. In particular, Figures 3 and 4 show that chip pair 30 may be provided as an exemplary chipset. As shown in FIG. 3 , one of the first and second chips 11 and 12 may be smaller than the other of the first and second chips 11 and 12 in at least one dimension. That is, the first chip 11 may be shorter than the second chip 12 in the longitudinal dimension, either as a result of the first chip 11 being manufactured differently than the second chip 12 so that the first chip 11 is shorter than the second chip 12 or as a result of the first chip 11 being shorter than the second chip 12. A result that the end portion of the chip 11 is cut off. In either case, the exposed portions 21 of the second chip 12 may be used as probes or test pads. Once probing or testing is complete, a filler 22 may be added to the first chip 11 to cover the exposed portion 21 of the second chip 12 as shown in FIG. 4 .

According to an alternative embodiment, the filler 22 of FIG. 4 may not be added. Conversely, referring to FIG. 5 , the exposed portion 21 of the second chip 12 may be electrically coupled to the complementary exposed portion 21 of another second chip 12 of another adjacent chip pair 30 . As shown in FIG. 5 , two chip pairs 30 cooperate to form lap joints 35 at complementary exposed portions 21 of respective second chips 12 . In a given package, this arrangement can be repeated for each chip pair 30 to form multiple bridges 35 and so that the given package's width, active area, and total connections increase accordingly.

Referring to FIG. 6 , the package structure 10 may further include a carrier chip 40 . The carrier chip 40 can be electrically interconnected to the respective "bottom" sidewalls 113 and 123 of the first and second chips 11 and 12 by conductive elements such as microbumps 18 having a pitch of, for example, 75 μm so that they can be placed on the respective "top" sidewalls 113 and 123. ” and “bottom” sidewalls 113 and 123 using a 25 μm pitch corner intersection thereby multiplying the number of possible connections provided by package structure 10 . The carrier chip 40 may be formed from silicon and may define through-silicon vias (TSVs) and further include conductive elements electrically connected to the first and second chips through the TSVs. The C4 array 20 may be provided on the “bottom” surface of the carrier chip 40 between the packaging structure 10 and the first level packaging substrate 201 . The use of TSVs in the carrier chip 40 allows the use of lower cost materials and simplification of the first level packaging substrate.

Still referring to FIG. 6 , and according to yet another embodiment, the package structure 10 may include a “T” connector 50 . These "T" connectors 50 may be disposed along respective "top" and/or "bottom" (ie, long) sidewalls 113 and 123 of adjacent ones of the first and/or second chips 11 and 12 and be Configured to provide vertical and horizontal connections. The "T" connector 50 may be formed from a multilayer ceramic, two or more bonded glass/silicon inserts with wiring on one or more surfaces. In this embodiment, the "T" connector 50 may be used to replace the "corner intersection" between the active chip surfaces 112 and 122 and the "top" sidewalls 113 and 123 of the active surface 130 facing the common chip 13 and the corners between the active chip surfaces 112 and 122 and the “bottom” sidewalls 113 and 123 facing the carrier chip 40 . "T" connector 50 may provide an electrical connection (i.e., a horizontal connection) between adjoining chip pairs 30 and/or a package liner between chip pair 30 and common top chip 13 or carrier chip 40 or if carrier chip 40 is not present. Electrical connections (ie, a combination of horizontal and vertical connections) are provided between the bases 201 . The "T" connector 50 can be connected to the respective active surface of the chip pair 30 (112 or 122), which are adjacent to the active surface 130 of the common chip 13 and connected to the The active surface 130 of the common chip 13 . Similar connections can be made to the carrier chip 40 or the package substrate 201 .

Although the chip set described above and shown in FIGS. Other setups in which two or more chips are present in a chipset are possible. That is, referring to FIG. 7 , a given chipset may include first and second chips 11 and 12 and one or more additional chips 60 . This additional chip 60 may be disposed between the first and second chips 11 and 12 and formed to define a TSV 61 so that communication between the first and second chips 11 and 12 is possible. In any case, it should also be understood that package 10 generally includes multiple chip groups arranged along the length of common chip 13 and that individual chip groups in package 10 may include different numbers of chips.

Referring to FIGS. 8-11 , an optional packaging structure 1000 (see FIG. 11 ) may be formed of chipsets, where each chipset includes two first chips 1100 and two second chips 1200 . The process of assembling such an arrangement will be described below.

Initially, as shown in FIG. 8, a first chip 1100 and a second chip 1200 are electrically interconnected by microbumps 18 to form a first pair 70, as described above. The first chip 1100 and the second chip 1200 are rotated 90 degrees relative to each other and are substantially rectangular in shape (although this is not required). This defines the exposed portion 21 at the opposite distal end of the second chip 1200 which extends beyond the sidewall of the first chip 1100 . As shown in FIG. 9 , a through block 71 is then attached to the exposed portion 21 of the second chip 1200 . For pitches up to 100-200 [mu]m, a through block 71 containing solder bumps 72 or other electrical connectors with similar pitch characteristics as described above can be provided. The through block 71 may be formed of glass with conductive vias, silicon with conductive vias, ceramics with conductive vias, PCB/organic build-up/flex, and the like.

Referring to FIG. 10 , a second pair 80 of first and second chips 1100 and 1200 electrically interconnected by microbumps 18 may be attached to first pair 70 . The exposed portions 21 of the second chips 1200 of the second pair 80 are connected to the through-block 71 through solder bumps 72 or other electrical connectors. A thermal bonding layer 81 is formed between the two first chips 1100 of the first and second pairs 70 and 80 . The thermal bonding layer may be a solder layer, a filled thermal adhesive such as silver epoxy, or an epoxy filled with thermally conductive particles such as a low melting point metal or alloy. Optionally, fluid channels may be formed on the non-active major surfaces of the first and second pair 70 and 80 and a dielectric fluid may flow through for cooling purposes. As shown in Figure 11, the process can continue for additional pairs.

The package structure 1000 shown in FIGS. 8-11 allows the formation of a stack of chips with electrical connections between all chips in the stack without the use of through-silicon vias. The downward facing surface of the "bottom" chip or the downward facing exposed portion 21 of the "top" chip in a "bottom" chip pair can be mounted to the package substrate 2010 using the C42000 to provide power and communications to the chip stack. Through-block 71 may include flexible connections 710 that can be attached to package substrate 2010 or elsewhere in the system to provide power and communication directly to chip pairs in the stack without passing through lower chips and through-blocks in the stack .

For example, as shown in FIG. 11 , one or more upper through-blocks 71 may include flex connections 710 attached to package substrate 2010 . Additionally, one or more feedthrough blocks 71 may include flexible connections 710 for attachment to other feedthrough blocks 71 or system components. System components may include, but are not limited to, circuit boards, memory devices, power supplies, input/output (I/O) devices, and/or electrical/optical converters.

This is the terminology used for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms unless the content clearly dictates otherwise. It should also be understood that the terms "comprising" and/or "comprising", when used in this specification, specifically refer to the presence of state features, integers, steps, operations, elements and/or parts, but do not exclude the presence of one or more features , an integer, a step, an operation, an element and/or the presence or addition of a group thereof.

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, and act for performing the function in combination with other claimed elements as specifically claimed . The description of the present invention has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and changes will be apparent to those skilled in the art without departing from the scope and spirit of the invention as described. The embodiment was chosen and described in order to best explain the principles of the invention as well as the practical application, and to enable others skilled in the art to employ the invention with various modifications as are suited to the particular use contemplated.

While the embodiments of the present invention have been described, it will be apparent to those skilled in the art that various improvements and enhancements can be made, now and in the future, within the scope of the invention which follows in the appended claims. These claims should be construed to maintain the proper protection for the invention first described.

Claims (33)

1. an encapsulating structure, comprising:

The first and second chips;

At least one surface of each in described the first and second chips is active surface; And

Common chip, at least one in described the first and second chips arrived described common chip by electrical interconnection;

The active surface separately of described the first and second chips is to arrange face-to-face each other directly electrical interconnection and with respect to described common chip horizontal orientation.

2. according to the encapsulating structure of claim 1, wherein the bending in described the first and second chips is compensated for by the bending in another in described the first and second chips.

3. according to the encapsulating structure of claim 1, at least one in wherein said the first and second chips comprises at least one in voltage or power conversion apparatus, control device and storage component part.

4. according to the encapsulating structure of claim 1, be also included at least one in microprotrusion or the micro-connection arranging between described the first and second chips, described active surface is separately by described microprotrusion or the direct electrical interconnection of micro-connection.

5. according to the encapsulating structure of claim 1, in wherein said the first and second chips one is less than another in described the first and second chips at least one yardstick.

6. according to the encapsulating structure of claim 1, wherein said the first and second chips are rotation relative to each other at least one yardstick.

7. according to the encapsulating structure of claim 1, also comprise carrier chip, described the first and second chip electrical interconnections are to described carrier chip.

8. according to the encapsulating structure of claim 1, wherein said the first and second chips each be quantitatively plural number and provided by the form of the chipset of the length setting with along described common chip.

9. encapsulating structure according to Claim 8, one or more in wherein said chipset comprise additional chip.

10. according to the encapsulating structure of claim 7, wherein adjacent chips group is by overlap joint electrical interconnection.

11. 1 kinds of encapsulating structures, comprising:

The first and second chips, each in described the first and second chips comprises the body of four sidewalls that have two apparent surfaces and extend between described two apparent surfaces;

At least one in described two apparent surfaces of each in described the first and second chips is active surface; And

Common chip, at least one in the sidewall separately of described the first and second chips arrived described common chip by electrical interconnection;

The described active surface separately of described the first and second chips is to arrange face-to-face each other directly electrical interconnection and with respect to described common chip horizontal orientation.

12. according to the encapsulating structure of claim 11, and wherein the bending in described the first and second chips is compensated for by the bending in another in described the first and second chips.

13. according to the encapsulating structure of claim 11, and at least one in wherein said the first and second chips comprises at least one in voltage or power conversion apparatus, control device and storage component part.

14. according to the encapsulating structure of claim 11, is also included at least one in microprotrusion or the micro-connection arranging between described the first and second chips, and described active surface is separately by described microprotrusion or the direct electrical interconnection of micro-connection.

15. according to the encapsulating structure of claim 11, and in wherein said the first and second chips one is less than another in described the first and second chips at least one yardstick.

16. according to the encapsulating structure of claim 11, and wherein said the first and second chips are rotation relative to each other at least one yardstick.

17. according to the encapsulating structure of claim 11, also comprises carrier chip, and described the first and second chip electrical interconnections are to described carrier chip.

18. according to the encapsulating structure of claim 11, and wherein said the first and second chips each be quantitatively plural number and provided by the form of the chipset of the length setting with along described common chip.

19. according to the encapsulating structure of claim 18, and one or more in wherein said chipset comprise additional chip.

20. according to the encapsulating structure of claim 18, and wherein adjacent chips group is by overlap joint electrical interconnection.

21. 1 kinds of encapsulating structures, comprising:

The chipset of at least the first and second chips;

At least one surface of each of described first and second chips of each chipset is active surface; And

Common chip, at least one in described first and second chips of each of described chipset arrived described common chip by electrical interconnection;

The active surface separately of described first and second chips of each of described chipset is to arrange face-to-face each other directly electrical interconnection and with respect to described common chip horizontal orientation.

22. 1 kinds of encapsulating structures, comprising:

The first and second chipsets, each chipset at least comprises the first and second chips;

At least one surface of each of described first and second chips of each chipset is active surface;

The active surface separately of described first and second chips of each of described chipset is to arrange face-to-face each other directly electrical interconnection; And

Knitting layer, described the first and second chipsets are attached to each other by described knitting layer.

23. according to the encapsulating structure of claim 22, also comprises perforation piece, and the active surface of separately at least one of each of described first and second chips of each chipset interconnects by described perforation piece.

24. according to the encapsulating structure of claim 22, also comprises package substrate, and end chipset is interconnected to described package substrate.

The method of 25. 1 kinds of assembled package structures, comprising:

So that the active surface separately of direct electrical interconnection the first and second chips to be set face-to-face;

By at least one electrical interconnection in the sidewall separately of described the first and second chips to common chip; And

With respect to the described active surface separately of the first and second chips described in described common chip horizontal orientation.

26. according to the method for claim 25, also comprises by the bending in described the first and second chips and compensates for the bending in another in described the first and second chips.

27. according to the method for claim 25, also comprises forming having voltage or power conversion apparatus, control device, comprising at least one at least one described the first and second chips in passive device or the storage component part of capacitor or inductor.

28. according to the method for claim 25, is also included at least one in microprotrusion or micro-connection is set between described the first and second chips.

29. according to the method for claim 25, also comprises compared with in described the first and second chips one, reduces the size on another at least one yardstick in described the first and second chips.

30. according to the method for claim 25, also comprises described first is electrically connected to carrier chip with the second chip.

31. according to the method for claim 25, also comprises with the form of the chipset of the length setting along described common chip multiple described the first and second chips are provided.

32. according to the method for claim 31, and one or more in wherein said chipset comprise additional chip.

33. according to the method for claim 31, also comprises by overlap joint and is electrically connected contiguous chipset.

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