CN103885890A - Replacement processing method and device for cache blocks in caches - Google Patents
Replacement processing method and device for cache blocks in caches Download PDFInfo
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Abstract
本发明实施例提供的高速缓冲存储器cache中cache块的替换处理方法和装置，通过为除了L1 cache之外的cache中各cacheline增加一个标志位来指示其内的数据是否存在于上级cache中，尽可能减少上级cache中含有的cache line在本级cache被替换出去的情况，进而减少了上级cache的cache line被替换造成的开销；而且还能够提高cache的命中率，减少存储器访问时延。
In the cache block replacement processing method and device in the cache provided by the embodiments of the present invention, a flag bit is added to each cacheline in the cache except the L1 cache to indicate whether the data therein exists in the upper-level cache. It may reduce the situation that the cache line contained in the upper-level cache is replaced in the current-level cache, thereby reducing the overhead caused by the replacement of the cache line of the upper-level cache; and it can also improve the hit rate of the cache and reduce the memory access delay.
Description
Technical field
The embodiment of the present invention relates to data storage technology, relates in particular to replacing processing method and the device of cache piece in a kind of cache memory cache.
Background technology
Cache memory (cache) the earliest by Wilkes in nineteen fifty-one for the speed difference making up between processor and storer proposes, be most important part in storage system.In prior art, cache generally adopts hierarchical structure, Fig. 1 is cache hierarchical structure schematic diagram in prior art, the cache structure that has adopted as shown in Figure 1 L1 cache, L2 cache and tri-levels of L3 cache, its access speed is successively decreased successively, and capacity increases progressively successively.L1 cache is higher level cache for L2 cache, and L2 cache is higher level cache for L3 cache.If all data in higher level cache all exist in cache at the corresponding levels, the organizational form of so this cache is for comprising formula (inclusive).If data at most can two cache one of them, cannot be present in two cache simultaneously, this cache organizational form is exclusive formula (exclusive).The processor of prior art adopts the cache organizational form of inclusive mostly.
Cache is according to principle of locality, and the data that a storage area often uses are for processor calculating.So inevitable some data are not stored in cache, in the time of this part data of access, miss (cache miss) can occur, and hit (cache hit) otherwise be called cache.The performance of cache is closely connected with cache hit rate, and cache hit rate is higher, and the time that memory access needs is fewer, and the performance of cache is higher; Otherwise cache performance is just lower.If the data of current accessed are not cache miss in cache, may cause existing cache according to cache piece (cache line, refer generally to the least unit of cache read-write) size replace, the data that are about in cache line are up till now cancelled in this cache, and insert new data.
In the cache that adopts inclusive mode to organize, because cache at different levels only add up according to the accessed situation of cache at the corresponding levels, may cause the service condition of rudimentary cache also untrue, and then cause the replacement policy of poor efficiency, affect the access performance of storer.For example L2 cache, in the time carrying out cache line replacement, may replace a cache line who frequently hits in L1 cache; Due to the organizational form of inclusive, cache line corresponding in L1 cache also can be replaced away, will affect the access performance of storer like this.
Summary of the invention
The embodiment of the present invention provides replacing processing method and the device of cache piece in a kind of cache memory cache, to improve the hit rate of cache.
The embodiment of the present invention provides the replacing processing method of cache piece in a kind of cache memory cache on the one hand, comprising:
The data access request receiving in basis is carried out cache at the corresponding levels in the process of data access, if miss and to have zone bit in multiple cache pieces to be replaced in described cache at the corresponding levels be the cache piece of reset mode, in the cache piece that is reset mode at described zone bit, select a target cache piece to replace; Described zone bit comprises reset mode and SM set mode, and described zone bit is for representing whether the data of described cache piece are present in the higher level cache that described cache at the corresponding levels is corresponding, and described SM set mode represents to exist, and described reset mode represents not exist.
Also comprise in the above-described embodiments: if multiple cache pieces to be replaced comprise the cache piece of not storing data in described cache at the corresponding levels, the cache piece that data are not stored in preferential selection is replaced as target cache piece.
Also comprise in the above-described embodiments: in the time carrying out cache initialization, the zone bit of each cache piece is set to reset mode;
Or,
After data in cache piece are deleted, the zone bit of described cache piece is set to reset mode;
Or,
After data in described higher level cache in a cache piece are replaced, if only there is a higher level cache in described cache at the corresponding levels, or exist in multiple higher level cache and other higher level cache and do not comprise the data that are replaced, the zone bit of the cache piece being replaced corresponding cache piece in described cache at the corresponding levels is set to reset mode;
Or,
After data in described higher level cache in a cache piece are replaced, comprise if described cache at the corresponding levels exists in multiple higher level cache and other higher level cache the data that are replaced, the zone bit that maintains the cache piece of correspondence in described cache at the corresponding levels is SM set mode;
Or
After data in described higher level cache in a cache piece are replaced, the zone bit of the described cache piece corresponding cache piece in described cache at the corresponding levels after replacing is set to SM set mode.
Also comprise in the above-described embodiments: if the zone bit of multiple cache pieces to be replaced is SM set mode in cache at the corresponding levels, select a target cache piece to replace according to preset algorithm, and carrying out after replacement, the zone bit of described target cache piece is set to reset mode; And carried out at higher level cache after the replacement processing of cache piece, then the zone bit of described target cache piece is set to SM set mode;
Or
If the zone bit of multiple cache pieces to be replaced is SM set mode in cache at the corresponding levels, select a target cache piece to replace according to preset algorithm, and carrying out after replacement, directly the zone bit of described target cache piece is set to SM set mode; Carry out again the replacement processing of the cache piece of higher level cache;
Or
After selecting a target cache piece to replace in the cache piece that is reset mode at described zone bit, the zone bit of described target cache piece is set to reset mode; And carried out at higher level cache after the replacement processing of cache piece, then the zone bit of described target cache piece is set to SM set mode;
Or,
After selecting a target cache piece to replace in the cache piece that is reset mode at described zone bit, directly the zone bit of described target cache piece is set to SM set mode; Carry out again the replacement processing of the cache piece of higher level cache.
In the above-described embodiments, the each cache piece in described cache at the corresponding levels is all provided with a zone bit separately, or has the shared zone bit of multiple cache pieces of different index.
In the above-described embodiments, each described cache piece is stored in same an array with corresponding zone bit, or stores in different arrays.
The another aspect of the embodiment of the present invention provides the replacement treating apparatus of cache piece in a kind of cache memory cache, and this device comprises:
Receiver module, for receiving data access request;
Processing module, for the process cache at the corresponding levels being carried out according to the data access request receiving data access, if miss and to have zone bit in multiple cache pieces to be replaced in described cache at the corresponding levels be the cache piece of reset mode, in the cache piece that is reset mode at described zone bit, select a target cache piece to replace; Described zone bit comprises reset mode and SM set mode, and described zone bit is for representing whether the data of described cache piece are present in the higher level cache that described cache at the corresponding levels is corresponding, and described SM set mode represents to exist, and described reset mode represents not exist.
Replacing processing method and the device of cache piece in the cache memory cache that the embodiment of the present invention provides, whether increase a zone bit by each cache line in the cache for except L1 cache indicates the data in it to be present in higher level cache, reduce as far as possible the situation that the cacheline that contains in higher level cache is replaced away at cache at the corresponding levels, and then the cache line that has reduced higher level cache is replaced the expense causing; But also can improve the hit rate of cache, reduce access time delay of memory.
Accompanying drawing explanation
Fig. 1 is cache hierarchical structure schematic diagram in prior art;
Fig. 2 is cache inner structure schematic diagram in the embodiment of the present invention;
Fig. 3 is the replacing processing method process flow diagram of embodiment of the present invention cache piece;
Fig. 4 is the structural representation of the corresponding cache at the corresponding levels of the single higher level cache of the embodiment of the present invention;
Fig. 5 is the structural representation of the corresponding cache at the corresponding levels of the multiple higher level cache of the embodiment of the present invention;
Fig. 6 is the replacement treating apparatus structural representation of cache piece in embodiment of the present invention cache.
Embodiment
In cache hierarchical structure as shown in Figure 1, both can adopt exclusive mode, also can adopt inclusive mode, following embodiment is that the storage mode that all data in higher level cache all exist in cache at the corresponding levels is introduced technical scheme of the present invention for inclusive mode.
In order more clearly to understand technical scheme of the present invention, paper is cache inner structure once, and Fig. 2 is cache inner structure schematic diagram in the embodiment of the present invention, and as shown in Figure 2, cache generally adopts the organizational form of set associative.General cache is divided into some groups, and every group comprises that several cache line(are cache piece), if every group has n cache line, be referred to as n road set associative.Specific data in internal memory (memory) can correspondingly be put in any one the cache line in the designated groups in cache.Fig. 2 is the cache structure of two-way set associative.First address (address) is divided into cache tag(label), cache index(index) and offset(side-play amount) three field: offset represent an address in cache line, the cache line of for example 16Byte, can represent with the offset of 4-bit; Cache index is used for the group (because in set associative, the address of an appointment can only be mapped to a group) in Data Array and the Tag Array of index cache; Cache tag is generally the high part of address, is used for judging in the multiple cache line(Fig. 2 in group as way0 and way1) whether hit or do not hit (hit/miss).1 road set associative is called direct mapping.Cache only has one group, is called full associative mapping.Directly, in the situation of mapping, when cache replaces, owing to must also can only the cache line of one of them appointment being replaced, there is no alternative cache line and select.Therefore various embodiments of the present invention are adapted in the situation of non-direct mapping, in cache index one group of cache pointed, at least have two cacheline to be replaced.
The embodiment of the present invention is in the cache of inclusive organizational form, and the defect of likely the cache line frequently using being replaced away, is optimized replace Algorithm, to improve memory access efficiency.Particularly, in the embodiment of the present invention, be that cache line as each for example, in other cache except L1 cache in Fig. 1 (L2 cache and L3 cache) increases a such as upper of zone bit, upper is for representing whether the data of this cache line are present in the higher level cache that cache at the corresponding levels is corresponding.Zone bit at least comprises that two states are reset mode and SM set mode, wherein, SM set mode represents that the data in this cache line are to be present in the higher level cache that cache at the corresponding levels is corresponding, and reset mode represents that the data in this cache line are not to be present in the higher level cache that cache at the corresponding levels is corresponding.For example, in a cache line in L2 cache, store data M, if zone bit corresponding to this cache line is that for example upper position of SM set mode is " 1 ", illustrates and in L1 cache, also store data M; If the zone bit that this cache line is corresponding is reset mode, for example upper position is " 0 ", illustrates and in L1 cache, does not store data M.The embodiment of the present invention can be selected suitable cache line in multiple cache line to be replaced according to the state of zone bit in L2 cache, to avoid the frequent cache line using in L1 cache to be replaced away.
Fig. 3 is the replacing processing method process flow diagram of embodiment of the present invention cache piece, and as shown in Figure 3, the method comprises:
Receiving after data access request, progressively inquiring about according to the hierarchical structure of cache.First search L1 cache, search one group of cache line corresponding with cacheindex in L1 cache according to the cache index in request address particularly, check that the cache the tag whether tag corresponding to data of storage in each cache line in this group cache line comprise with address is consistent, if consistent, hit, if inconsistent, miss.If L1 cache hits, data access success; If L1 cache is miss, continue sequentially to search L2 cache and L3 cache, the mode of searching of L2 cache and L3 cache is consistent with L1cache, repeats no more herein.If all miss, search memory until hit.As requested, if the cache of certain one-level is miss, to trigger replacement flow process, in this grade of cache, in the cache line corresponding with cacheindex group, multiple cache line of to be replaced middle selection to be replaced replace, and will apply the data that the data replacement that will search was stored originally.
In the embodiment of the present invention, miss at L1 cache, continue for example L2 cache to carry out in the process of data access, if still miss, need L2 cache to replace processing.First check the state of the zone bit of each cache line in the cache line group that cacheindex is corresponding, if having zone bit is the cache line of reset mode, illustrate that the data in this cache line are not present in L1 cache, even if the data in this cache line are replaced away, in L1 cache, all data of storage are still all stored in L2 cache, select so its as an alternative target can not cause the replacement of L1 cache, therefore in the cache line that the embodiment of the present invention is reset mode at zone bit, select a target cache line to replace.Be understandable that, if the zone bit of the cache line of selected replacement in L2 cache is SM set mode, illustrate that the data in this cache line are also present in L1 cache, after the data replacement in this cache line is gone out, according to the requirement of inclusive organizational form, cacheline corresponding in L1cache also will replace, and the data of its storage inside are by deleted, if these data are frequently hit at L1 cache, so replace the efficiency that is unfavorable for data search.
In the replacing processing method of the cache piece that the embodiment of the present invention provides, whether increase a zone bit by each cache line in the cache for except L1 cache indicates the data in it to be present in higher level cache, reduce as far as possible the situation that the cache line that contains in higher level cache is replaced away at cache at the corresponding levels, and then the cache line that has reduced higher level cache is replaced the expense causing; But also can improve the hit rate of cache, reduce access time delay of memory.
In said method embodiment, if L1 cache and L2 cache are all miss, in L2 cache, select according to the method described above in process that a target cache line replaces, if find, in L2 cache, multiple cache line to be replaced comprise the cache line that does not store data, preferentially select this cache line that does not store data to replace as target cache line.In a cache line, current reason of not storing data has a lot, for example, after initialization, in all cache line, all do not store data.Be in the present embodiment when select target cache line, the cache line of any data is not stored in preferential selection, if all store data, the system of selection that embodiment provides is according to the method described above selected.
In said method embodiment, if L1 cache and L2 cache are all miss, in L2 cache, select according to the method described above in process that a target cache line replaces, if find, the zone bit of multiple cache line to be replaced in L2 cache is SM set mode, and the algorithm that can generally adopt according to for example prior art of preset algorithm selects a target cache line to replace.Because the data after replacing do not exist in L1 cache, zone bit that therefore can this target cache line after replacement is set to reset mode.
Fig. 4 is the structural representation of the corresponding cache at the corresponding levels of the single higher level cache of the embodiment of the present invention, and Fig. 5 is the structural representation of the corresponding cache at the corresponding levels of the multiple higher level cache of the embodiment of the present invention.Fig. 4 comprises the higher level cache of a cache at the corresponding levels and single correspondence, adopts the organizational form of inclusive, for example, only have the corresponding L2 cache of a L1 cache.Fig. 5 comprises a cache at the corresponding levels and corresponding multiple higher level cache, adopts the organizational form of inclusive, for example the corresponding L3 cache of the multiple L2 cache in multiple nucleus system.For each cache line of cache at the corresponding levels increases a zone bit upper, represent whether corresponding cache line has data to be present in higher level cache.Initialization, reset and the set operation of upper position are as follows:
Initialization: in the time carrying out cache initialization, all cache line in cache are all invalid, and the zone bit of cache line is set to reset mode.
Upper set (effectively): when there being data to be written to any one higher level cache from cache at the corresponding levels, by the upper set of corresponding cache line in cache at the corresponding levels.For Fig. 5, if be written to the data in one of them higher level cache, this is just present in other higher level cache, and upper is originally exactly that effectively now set does not affect so.If between multiple higher level cache, be the organizational form of exclusive (for example, most L1 data cache and L1 instruction cache), be written to so the data in one of them higher level cache, inevitable not being present in other higher level cache, upper becomes effectively from invalid so.
In addition, after the data in higher level cache in a cache piece are replaced, by the upper set of the cache piece corresponding cache line in cache at the corresponding levels after replacing.
Upper reset (invalid):
For Fig. 4, according to causing that reason that upper resets is divided into two kinds of the replacements of the invalid of cache line and cache line: as the non-L1cache of cache() the invalid operation of carrying out cache line while deleting the data in cacheline, and the upper of corresponding cache line needs to reset.When there being data to replace out from higher level cache, the cache line being replaced is resetted at the upper of the corresponding cache line of the corresponding levels.Data are replaced from higher level cache out two kinds of situations: a kind of is to be caused by the cache miss of higher level cache; A kind of is because upper all in cache at the corresponding levels all replaces effectively time and causes.
For Fig. 5, according to causing that reason that upper resets is divided into two kinds of the replacements of the invalid of cache line and cache line: as the non-L1 cache of cache() the invalid operation of carrying out cache line while deleting the data in cacheline, and the upper of corresponding cache line needs to reset.The replacement of cache line is divided into two kinds of situations: the first is the replacement being caused by the cache miss of higher level cache, and the second is because upper all in cache at the corresponding levels all replaces effectively time and causes.The second situation can reset upper immediately.The first situation needs further to analyze:
If what adopt between multiple higher level cache is the organizational form of exclusive, so in the time that higher level cache replaces, in other higher level cache, do not comprise the data that are replaced, now can immediately the cache line being replaced be resetted at the upper of cache line corresponding to cache at the corresponding levels.
If what adopt between multiple higher level cache is the organizational form of inclusive, when a higher level cache replaces, whether the higher level cache that first inquires about other contains these data that are replaced, and (catalogue consistance can be checked catalogue, bus consistency protocol can complete judgement by sending bus request to other higher level cache), as long as if having one to contain this data in other higher level cache, upper position does not reset so, still keep SM set mode (effective), otherwise the cache line being replaced is resetted at the upper of cache line corresponding to cache at the corresponding levels.
In said method embodiment, cache line and corresponding zone bit upper can be stored in same an array, can certainly be stored in different arrays.Each cache line in cache can all be provided with a upper position separately.Or multiple cache line with different index share a upper position, that is to say in order to save the shared storage resources of upper, can adopt a upper to represent multiple cache line corresponding different index of cache at the corresponding levels, as long as wherein there is a cache line to meet the as above condition of upper set, this upper position is with regard to set; Otherwise upper position is invalid.
In addition, communicating by letter between cache at the corresponding levels and higher level cache can, by many-to-one draw bail, also can be passed through bus, also can be by structures such as crossbar, and the embodiment of the present invention is also not construed as limiting.
Below in conjunction with an actual example, the method for the embodiment of the present invention is introduced.In the time that the cache shown in Fig. 1 is carried out to A data access, in request address, cache index points to one group of cache line in L1 cache, comprising two cache line(cache line1 and cache line2) (the present embodiment describes take two as example, be not limited to this), cache line1 stores data B, and cache line2 stores data C.Because the data A of access is miss at L1 cache, continue access L2 cache.Cache index points to one group of cache line in L2 cache, comprising three cache line(cacheline3, cache line4 and cache line5) (the present embodiment describes take three as example, be not limited to this), suppose that cache line3 stores data C, corresponding upper position is 1; Cache line4 stores data D, and corresponding upper position is 0; Cache line5 stores data E, and corresponding upper position is 0.The method providing according to the embodiment of the present invention, now selects cache line5 to replace (supposing that L3 cache hits herein) as target cacheline and uses data A replacement data E, and the upper position that now cacheline5 is corresponding is 0.
While carrying out the replacement of L1 cache again, use data A replacement data C if select cache line2 to replace, the cache line2(being replaced in L1 cache stores data C) in L2 cache, the upper position of corresponding cache line3 is set to 0.Meanwhile, in L1 cache, the cacheline2(after replacement stores data A) in L2 cache, the upper position of corresponding cache line5 is set to 1.
While carrying out the replacement of L1 cache again, use data A replacement data B if select cache line1 to replace, the cache line1(being replaced in L1 cache is stored to data B) cache line(corresponding in L2 cache stores data B, in another cache line group) upper position be set to 0.Meanwhile, in L1 cache, the cache line1(after replacement stores data A) in L2 cache, the upper position of corresponding cache line5 is set to 1.Or can also simplify processing, while being the cache line5 of correspondence in application data A replacement L2 cache, because L2 cache is miss, L1 cache is inevitable also miss, therefore can be first directly in L2 cache the upper position of corresponding cache line5 be set to 1, and then to replace the data B of cache line1 in L1 cache with data A.This simplifies treatment scheme and is equally applicable to upper position that the miss and cache index of L2 cache points to the each cache line in L2 cache and is all set to other situations such as 1.
In the above-described embodiments, suppose that cache line1 stores data B; Cache line2 stores data C; Cache line3 stores data A, and corresponding upper position is 0; Ache line4 stores data B, and corresponding upper position is 1; Cache line5 stores data C, and corresponding upper position is 1.In the process of request access data A, L1 cache is miss, but L2 cache hits, now to carry out the replacement of L1cache, if select cache line1 to replace, needing the upper position of cache line4 is 0, and is 1 by the upper position of cache line3.In the replacing processing method of the cache piece that the embodiment of the present invention provides, whether increase a zone bit by each cache line in the cache for except L1 cache indicates the data in it to be present in higher level cache, and carrying out in cache line replacement process, selection marker position is in the cache of reset mode line as far as possible, situation about being replaced away at cache at the corresponding levels to reduce the cache line that contains in higher level cache, and then the cache line that has reduced higher level cache is replaced the expense causing; But also can improve the hit rate of cache, reduce access time delay of memory.
Fig. 6 is the replacement treating apparatus structural representation of cache piece in embodiment of the present invention cache, and as shown in Figure 6, this device comprises receiver module 61 and processing module 62, and wherein, receiver module 61 is for receiving data access request.Processing module 62 is for the process cache at the corresponding levels being carried out according to the data access request receiving data access, if miss and to have zone bit in multiple cache pieces to be replaced in described cache at the corresponding levels be the cache piece of reset mode, in the cache piece that is reset mode at described zone bit, select a target cache piece to replace; Described zone bit comprises reset mode and SM set mode, and described zone bit is for representing whether the data of described cache piece are present in the higher level cache that described cache at the corresponding levels is corresponding, and described SM set mode represents to exist, and described reset mode represents not exist.
The treating apparatus that the embodiment of the present invention provides, whether increase a zone bit by each cache line in the cache for except L1 cache indicates the data in it to be present in higher level cache, and carrying out in cache line replacement process, selection marker position is in the cache of reset mode line as far as possible, situation about being replaced away at cache at the corresponding levels to reduce the cache line that contains in higher level cache, and then the cache line that has reduced higher level cache is replaced the expense causing; But also can improve the hit rate of cache, reduce access time delay of memory.
In said apparatus embodiment, processing module 62 also for, if multiple cache pieces to be replaced comprise the cache piece of not storing data in described cache at the corresponding levels, the cache piece that data are not stored in preferential selection is replaced as target cache piece.
Processing module 62 also for: in the time carrying out cache initialization, the zone bit of each cache piece is set to reset mode; Or after data in cache piece are deleted, the zone bit of described cache piece is set to reset mode; Or, after data in described higher level cache in a cache piece are replaced, if only there is a higher level cache in described cache at the corresponding levels, or exist in multiple higher level cache and other higher level cache and do not comprise the data that are replaced, the zone bit of the cache piece being replaced corresponding cache piece in described cache at the corresponding levels is set to reset mode; Or, after data in described higher level cache in a cache piece are replaced, comprise if described cache at the corresponding levels exists in multiple higher level cache and other higher level cache the data that are replaced, the zone bit that maintains the cache piece of correspondence in described cache at the corresponding levels is SM set mode; Or after the data in described higher level cache in a cache piece are replaced, the zone bit of the described cache piece corresponding cache piece in described cache at the corresponding levels after replacing is set to SM set mode.
Processing module 62 also for, if the zone bit of multiple cache pieces to be replaced is SM set mode in cache at the corresponding levels, select a target cache piece to replace according to preset algorithm, and carrying out after replacement, the zone bit of described target cache piece is set to reset mode; And carried out at higher level cache after the replacement processing of cache piece, then the zone bit of described target cache piece is set to SM set mode; If or the zone bit of multiple cache pieces to be replaced is SM set mode in cache at the corresponding levels, select a target cache piece to replace according to preset algorithm, and carrying out after replacement, directly the zone bit of described target cache piece is set to SM set mode; Carry out again the replacement processing of the cache piece of higher level cache; Or after selecting a target cache piece to replace in the cache piece that is reset mode at described zone bit, the zone bit of described target cache piece is set to reset mode; And carried out at higher level cache after the replacement processing of cache piece, then the zone bit of described target cache piece is set to SM set mode; Or after selecting a target cache piece to replace in the cache piece that is reset mode at described zone bit, directly the zone bit of described target cache piece is set to SM set mode; Carry out again the replacement processing of the cache piece of higher level cache.
The embodiment of the present invention also provides the replacement treating apparatus of cache piece in a kind of cache, comprise a processor, this processor has been used for following functions: in the process of according to the data access request receiving, cache at the corresponding levels being carried out data access, if miss and to have zone bit in multiple cache pieces to be replaced in described cache at the corresponding levels be the cache piece of reset mode, in the cache piece that is reset mode at described zone bit, select a target cache piece to replace.Wherein, described zone bit comprises reset mode and SM set mode, described zone bit is for representing whether the data of described cache piece are present in the higher level cache that described cache at the corresponding levels is corresponding, and described SM set mode represents to exist, and described reset mode represents not exist.
If the function that processor completes can also comprise that in described cache at the corresponding levels, multiple cache pieces to be replaced comprise the cache piece of not storing data, the cache piece that data are not stored in preferential selection is replaced as target cache piece.
Further, in the time carrying out cache initialization, the zone bit of each cache piece is set to reset mode; Or after data in cache piece are deleted, the zone bit of described cache piece is set to reset mode; Or, after data in described higher level cache in a cache piece are replaced, if only there is a higher level cache in described cache at the corresponding levels, or exist in multiple higher level cache and other higher level cache and do not comprise the data that are replaced, the zone bit of the cache piece being replaced corresponding cache piece in described cache at the corresponding levels is set to reset mode; Or, after data in described higher level cache in a cache piece are replaced, comprise if described cache at the corresponding levels exists in multiple higher level cache and other higher level cache the data that are replaced, the zone bit that maintains the cache piece of correspondence in described cache at the corresponding levels is SM set mode; Or after the data in described higher level cache in a cache piece are replaced, the zone bit of the described cache piece corresponding cache piece in described cache at the corresponding levels after replacing is set to SM set mode.
Also have, if the zone bit of multiple cache pieces to be replaced is SM set mode in cache at the corresponding levels, select a target cache piece to replace according to preset algorithm, and carrying out after replacement, the zone bit of described target cache piece is set to reset mode.
The treating apparatus that the embodiment of the present invention provides, whether increase a zone bit by each cache line in the cache for except L1 cache indicates the data in it to be present in higher level cache, and carrying out in cache line replacement process, selection marker position is in the cache of reset mode line as far as possible, situation about being replaced away at cache at the corresponding levels to reduce the cache line that contains in higher level cache, and then the cache line that has reduced higher level cache is replaced the expense causing; But also can improve the hit rate of cache, reduce access time delay of memory.
In several embodiment provided by the present invention, should be understood that disclosed apparatus and method can realize by another way.For example, device embodiment described above is only schematic, for example, the division of described unit, be only that a kind of logic function is divided, when actual realization, can have other dividing mode, for example multiple unit or assembly can in conjunction with or can be integrated into another system, or some features can ignore, or do not carry out.Another point, shown or discussed coupling each other or direct-coupling or communication connection can be by some interfaces, indirect coupling or the communication connection of device or unit can be electrically, machinery or other form.
The described unit as separating component explanation can or can not be also physically to separate, and the parts that show as unit can be or can not be also physical locations, can be positioned at a place, or also can be distributed in multiple network element.Can select according to the actual needs some or all of unit wherein to realize the object of the present embodiment scheme.
In addition, the each functional unit in each embodiment of the present invention can be integrated in a processing unit, can be also that the independent physics of unit exists, and also can be integrated in a unit two or more unit.Above-mentioned integrated unit both can adopt the form of hardware to realize, and the form that also can adopt hardware to add SFU software functional unit realizes.
The integrated unit that the above-mentioned form with SFU software functional unit realizes, can be stored in a computer read/write memory medium.Above-mentioned SFU software functional unit is stored in a storage medium, comprise that some instructions (can be personal computers in order to make a computer equipment, server, or the network equipment etc.) or processor (processor) carry out the part steps of method described in each embodiment of the present invention.And aforesaid storage medium comprises: various media that can be program code stored such as USB flash disk, portable hard drive, ROM (read-only memory) (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disc or CDs.
Those skilled in the art can be well understood to, for convenience and simplicity of description, only be illustrated with the division of above-mentioned each functional module, in practical application, can above-mentioned functions be distributed and completed by different functional modules as required, be divided into different functional modules by the inner structure of device, to complete all or part of function described above.The specific works process of the device of foregoing description, can, with reference to the corresponding process in preceding method embodiment, not repeat them here.
Finally it should be noted that: above each embodiment, only in order to technical scheme of the present invention to be described, is not intended to limit; Although the present invention is had been described in detail with reference to aforementioned each embodiment, those of ordinary skill in the art is to be understood that: its technical scheme that still can record aforementioned each embodiment is modified, or some or all of technical characterictic is wherein equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (10)
1. a replacing processing method for cache piece in cache memory cache, is characterized in that, comprising:
The data access request receiving in basis is carried out cache at the corresponding levels in the process of data access, if miss and to have zone bit in multiple cache pieces to be replaced in described cache at the corresponding levels be the cache piece of reset mode, in the cache piece that is reset mode at described zone bit, select a target cache piece to replace; Described zone bit comprises reset mode and SM set mode, and described zone bit is for representing whether the data of described cache piece are present in the higher level cache that described cache at the corresponding levels is corresponding, and described SM set mode represents to exist, and described reset mode represents not exist.
2. method according to claim 1, is characterized in that, described method also comprises:
If multiple cache pieces to be replaced comprise the cache piece of not storing data in described cache at the corresponding levels, the cache piece that data are not stored in preferential selection is replaced as target cache piece.
3. method according to claim 1, is characterized in that, described method also comprises:
In the time carrying out cache initialization, the zone bit of each cache piece is set to reset mode;
Or,
After data in cache piece are deleted, the zone bit of described cache piece is set to reset mode;
Or,
After data in described higher level cache in a cache piece are replaced, if only there is a higher level cache in described cache at the corresponding levels, or exist in multiple higher level cache and other higher level cache and do not comprise the data that are replaced, the zone bit of the cache piece being replaced corresponding cache piece in described cache at the corresponding levels is set to reset mode;
Or,
After data in described higher level cache in a cache piece are replaced, comprise if described cache at the corresponding levels exists in multiple higher level cache and other higher level cache the data that are replaced, the zone bit that maintains the cache piece of correspondence in described cache at the corresponding levels is SM set mode;
Or
After data in described higher level cache in a cache piece are replaced, the zone bit of the described cache piece corresponding cache piece in described cache at the corresponding levels after replacing is set to SM set mode.
4. method according to claim 1, is characterized in that, described method also comprises:
If the zone bit of multiple cache pieces to be replaced is SM set mode in cache at the corresponding levels, to select a target cache piece to replace according to preset algorithm, and carrying out after replacement, the zone bit of described target cache piece is set to reset mode; And carried out at higher level cache after the replacement processing of cache piece, then the zone bit of described target cache piece is set to SM set mode;
Or
If the zone bit of multiple cache pieces to be replaced is SM set mode in cache at the corresponding levels, select a target cache piece to replace according to preset algorithm, and carrying out after replacement, directly the zone bit of described target cache piece is set to SM set mode; Carry out again the replacement processing of the cache piece of higher level cache;
Or
After selecting a target cache piece to replace in the cache piece that is reset mode at described zone bit, the zone bit of described target cache piece is set to reset mode; And carried out at higher level cache after the replacement processing of cache piece, then the zone bit of described target cache piece is set to SM set mode;
Or,
After selecting a target cache piece to replace in the cache piece that is reset mode at described zone bit, directly the zone bit of described target cache piece is set to SM set mode; Carry out again the replacement processing of the cache piece of higher level cache.
5. according to the arbitrary described method of claim 1 to 4, it is characterized in that, the each cache piece in described cache at the corresponding levels is all provided with a zone bit separately, or has the shared zone bit of multiple cache pieces of different index.
6. according to the arbitrary described method of claim 1 to 4, it is characterized in that, each described cache piece is stored in same an array with corresponding zone bit, or stores in different arrays.
7. a replacement treating apparatus for cache piece in cache memory cache, is characterized in that, comprising:
Receiver module, for receiving data access request;
Processing module, for the process cache at the corresponding levels being carried out according to the data access request receiving data access, if miss and to have zone bit in multiple cache pieces to be replaced in described cache at the corresponding levels be the cache piece of reset mode, in the cache piece that is reset mode at described zone bit, select a target cache piece to replace; Described zone bit comprises reset mode and SM set mode, and described zone bit is for representing whether the data of described cache piece are present in the higher level cache that described cache at the corresponding levels is corresponding, and described SM set mode represents to exist, and described reset mode represents not exist.
8. device according to claim 7, is characterized in that, described processing module also for:
If multiple cache pieces to be replaced comprise the cache piece of not storing data in described cache at the corresponding levels, the cache piece that data are not stored in preferential selection is replaced as target cache piece.
9. device according to claim 7, is characterized in that, described processing module also for:
In the time carrying out cache initialization, the zone bit of each cache piece is set to reset mode; Or,
After data in cache piece are deleted, the zone bit of described cache piece is set to reset mode; Or,
After data in described higher level cache in a cache piece are replaced, if only there is a higher level cache in described cache at the corresponding levels, or exist in multiple higher level cache and other higher level cache and do not comprise the data that are replaced, the zone bit of the cache piece being replaced corresponding cache piece in described cache at the corresponding levels is set to reset mode; Or,
After data in described higher level cache in a cache piece are replaced, comprise if described cache at the corresponding levels exists in multiple higher level cache and other higher level cache the data that are replaced, the zone bit that maintains the cache piece of correspondence in described cache at the corresponding levels is SM set mode; Or
After data in described higher level cache in a cache piece are replaced, the zone bit of the described cache piece corresponding cache piece in described cache at the corresponding levels after replacing is set to SM set mode.
10. device according to claim 7, is characterized in that, described processing module also for:
If the zone bit of multiple cache pieces to be replaced is SM set mode in cache at the corresponding levels, to select a target cache piece to replace according to preset algorithm, and carrying out after replacement, the zone bit of described target cache piece is set to reset mode; And carried out at higher level cache after the replacement processing of cache piece, then the zone bit of described target cache piece is set to SM set mode;
Or
If the zone bit of multiple cache pieces to be replaced is SM set mode in cache at the corresponding levels, select a target cache piece to replace according to preset algorithm, and carrying out after replacement, directly the zone bit of described target cache piece is set to SM set mode; Carry out again the replacement processing of the cache piece of higher level cache;
Or
After selecting a target cache piece to replace in the cache piece that is reset mode at described zone bit, the zone bit of described target cache piece is set to reset mode; And carried out at higher level cache after the replacement processing of cache piece, then the zone bit of described target cache piece is set to SM set mode;
Or,
After selecting a target cache piece to replace in the cache piece that is reset mode at described zone bit, directly the zone bit of described target cache piece is set to SM set mode; Carry out again the replacement processing of the cache piece of higher level cache.
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