CN103873047A - Two-divided-frequency device and high-speed multiplexer - Google Patents

Abstract

An embodiment of the present invention provides a frequency divider by two and a high-speed multiplexer, which are used to solve the problem of sampling errors caused by the uncertainty of the initial phase of the frequency divider by two in the existing high-speed multiplexer. The first setting circuit in the two frequency divider loads the first level signal to the input terminal of the first inverter when the setting signal is valid, so that the first output terminal is at the second level; and The input end of the second inverter loads the second level signal, so that the second output end is the first level; and after the setting signal is changed from valid to invalid, the frequency divider receives After the first active edge of the clock signal is output and before the second active edge, its first output terminal outputs the first level, and its second output terminal outputs the second level, thereby outputting the frequency-divided frequency of the determined phase clock signal.

Description

A divide-by-two and high-speed multiplexer

technical field

The invention relates to the technical field of integrated circuits, in particular to a frequency divider by two and a high-speed multiplexer.

Background technique

In the current ultra-high-speed signal processing, one ultra-high-speed signal is usually decomposed into multiple low-speed signals for digital signal processing. After the processing is completed, the multiple low-speed signals are restored to one ultra-high-speed signal through a high-speed multiplexer. The high-speed multiplexer needs to synthesize N groups of low-speed signals with M channels in each group and each frequency of F into N groups of ultra-high-speed signals with 1 channel in each group and each frequency of M*F. That is to say, Synthesize M channels of low-speed signals with a frequency of F in each group into 1 channel of ultra-high-speed signals with a frequency of M*F. High-speed multiplexers are so named because they can include multiple relatively lower-speed multiplexers and achieve higher speeds.

However, due to the device delay of the D flip-flop (DFF, D Flip-Flop) and the multiplexer in the high-speed multiplexer, the initial phases of the two frequency dividers in the high-speed multiplexer are different, It may cause errors in the high-speed multiplexer to restore multiple low-speed signals to one high-speed signal.

A current high-speed multiplexer adopts a binary tree structure composed of multiple 2:1 multiplexers, where each 2:1 multiplexer can synthesize two low-speed signals into one high-speed signal , the structure of each 2:1 multiplexer is shown in Figure 1, including two D flip-flops D1 and D2, a latch L, a frequency divider by two, a multiplexer MUX, flip-flops The input terminal D of D1 receives the data signal D _Ain of channel A, the input terminal D of the trigger D2 receives the data signal D _Bin of channel B, and the clock signal terminal of the trigger D1 and the clock signal terminal of the trigger D2 both receive the output of the frequency divider The first clock signal CLK1 of the latch L, the input terminal D of the latch L receives the signal output by the flip-flop D2, the clock signal terminal of the latch L receives the second clock signal CLK2 output by the two frequency divider, and the multiplexer MUX The input terminal S1 receives the signal output by the flip-flop D1, the input terminal S2 of the multiplexer MUX receives the signal output by the latch L, and the control terminal C of the multiplexer MUX receives the first clock signal CLK1 output by the frequency divider , the multiplexer MUX combines the received two signals into one under the control of the first clock signal CLK1. Wherein, the frequency of the first clock signal CLK1 is equal to the frequency of the second clock signal CLK2, and the first clock signal CLK1 and the second clock signal CLK2 are complementary, that is, when the first clock signal CLK1 is at a high level, the second clock signal CLK2 is at a low level level, when the first clock signal CLK1 is at low level, the second clock signal CLK2 is at high level. The frequency of the first clock signal CLK1 and the frequency of the second clock signal CLK2 output by the frequency divider by two are both equal to half of the frequency of the clock signal CLK _in received by the frequency divider by two.

Since the flip-flop needs to meet the requirements of data setup time (setup time) and data hold time (hold time) during the working process, that is, the input signal is not allowed to change before and after the active edge of the clock signal. For a flip-flop triggered by a rising edge, the rising edge of the clock signal is the active edge, and the falling edge of the clock signal is the inactive edge; for a flip-flop triggered by the falling edge, the falling edge of the clock signal is the active edge, The rising edge of the clock signal is the inactive edge. The setup time is the minimum time interval during which the input signal received by the flip-flop must remain stable before the active edge of the clock signal arrives; and the hold time is the input signal received by the flip-flop should remain stable after the active edge of the clock signal arrives. Change the minimum time interval.

Although the multiplexer does not have the concept of setup time and hold time, within a period of time before and after the transition edge (either a rising edge or a falling edge) of the clock signal received by the multiplexer , if the input signal received by the multiplexer changes, the signal output by the multiplexer may be wrong. Therefore, near the transition edge of the clock signal received by the multiplexer, the multiplexer receives The received signal cannot be changed. Therefore, before the jump edge of the clock signal received by the multiplexer, the minimum time interval during which the input signal received by the multiplexer remains unchanged can be considered as the setup time of the multiplexer; After the transition edge of the received clock signal, the minimum time interval during which the input signal received by the multiplexer remains unchanged can be considered as the hold time of the multiplexer.

The above-mentioned high-speed multiplexer can convert the delay of the previous device into the setup time or hold time of the next device (the input signal received by the latter device is the output signal of the previous device), thus solving the problem of device delay problem.

But the initial phase of the two-frequency divider in the above-mentioned high-speed multiplexer is uncertain, when the initial phase of the two-frequency divider in the multiple 2:1 multiplexers in the above-mentioned high-speed multiplexer When different, it may lead to sampling error.

Contents of the invention

An embodiment of the present invention provides a frequency divider by two and a high-speed multiplexer, which are used to solve the problem of sampling errors caused by the uncertainty of the initial phase of the frequency divider by two in the existing high-speed multiplexer.

In the first aspect, a two-frequency divider provided by an embodiment of the present invention includes a first controllable switch, a second controllable switch, a third controllable switch, a fourth controllable switch, a first inverter, a second an inverter, a third inverter, a fourth inverter, a first latch, a second latch and a first setting circuit;

One end of the first controllable switch is respectively connected to the input end of the first inverter and one end of the first latch, and the other end of the first controllable switch is connected to the fourth inverter the output terminal of the first controllable switch, the control terminal of the first controllable switch receives the first control signal;

One end of the second controllable switch is respectively connected to the input end of the second inverter and the other end of the first latch, and the other end of the second controllable switch is connected to the third inverter the output terminal of the switch, and the control terminal of the second controllable switch receives the first control signal;

One end of the third controllable switch is respectively connected to the output end of the first inverter and the first output end of the frequency division by two, and the other end of the third controllable switch is respectively connected to the second lock One end of the register and the input end of the third inverter, and the control end of the third controllable switch receives the second control signal;

One end of the fourth controllable switch is respectively connected to the output end of the second inverter and the second output end of the frequency division by two, and the other end of the fourth controllable switch is respectively connected to the second lock The other end of the register and the input end of the fourth inverter, the control end of the fourth controllable switch receives the second control signal;

The first setting circuit is used to load the first level signal to the input terminal of the first inverter when the setting signal is valid, so that the first output terminal is at the second level; The input end of the inverter is loaded with a second level signal, so that the second output end is at the first level; and when the set signal is invalid, stop supplying the input end of the first inverter and the first level The input terminals of the two inverters are loaded with signals;

The first control signal is complementary to the second control signal, and after the setting signal changes from valid to invalid, the first control signal is a clock signal, and the second control signal is a clock blocking signal;

Both the first controllable switch and the second controllable switch are used to close when the first control signal is a first level signal, and to close when the first control signal is a second level signal open; the third controllable switch and the fourth controllable switch are both used to close when the second control signal is a first level signal, and to close when the second control signal is a second level signal Disconnect when the signal is flat;

The first latch is configured to latch the signal at the input end of the first inverter, and latch the signal at the input end of the second inverter;

The second latch is configured to latch the signal at the input terminal of the third inverter and latch the signal at the input terminal of the fourth inverter after the setting signal changes from valid to invalid.

With reference to the first aspect, in a first possible implementation manner, the frequency divider by two further includes a second setting circuit;

The second setting circuit is configured to load the first level signal to the input terminal of the third inverter when the setting signal is valid, and load the second level signal to the input terminal of the fourth inverter. level signal; and when the set signal is invalid, stop loading signals to the input terminal of the third inverter and the input terminal of the fourth inverter;

Wherein, the driving capability of the part of the second setting circuit that loads the signal to the input terminal of the third inverter is greater than the driving capability of the first inverter, and the driving capability of the part of the second setting circuit that loads the signal to the input terminal of the third inverter The drive capability of the portion of the input terminal of the fourth inverter loaded with a signal is greater than the drive capability of the second inverter.

With reference to the first aspect, in a second possible implementation manner, when the setting signal is valid, the first control signal is set to a second level signal, and the second control signal is set to a first level signal. level signal.

所述一路高速信号的传输速度为所述2ⁿ路低速信号之和；In the second aspect, a high-speed multiplexer provided by an embodiment of the present invention includes at least one synthesis circuit, wherein one synthesis circuit includes k 2:1 multiplexers and the binary divider provided by the embodiment of the present invention A frequency converter, the one synthesizing circuit is used for synthesizing a group of 2 ⁿ -way low-speed signals into a group of one-way high-speed signal circuits, k and n are both positive integers,

The transmission speed of the one high-speed signal is the sum of the 2 ⁿ low-speed signals;

In a synthesis circuit, the same stage 2:1 multiplexer receives the same frequency clock signal, the first stage 2:1 multiplexer receives said low speed signal, and the last stage 2:1 multiplexes The signal output by the device is the high-speed signal, and the signal received by each stage of 2:1 multiplexer except the first stage of 2:1 multiplexer is the signal received by the previous stage of 2:1 multiplexer The signal output by the multiplexer; the clock signal received by the 2:1 multiplexers at all levels except the last stage 2:1 multiplexer is received by the latter stage of the 2:1 multiplexer The clock signal is output after the clock signal is divided by a frequency divider by two;

Each 2:1 multiplexer is used to synthesize two received signals with a frequency of f into one with a frequency of 2 under the control of a clock signal with a frequency f output by a frequency divider. *f signal.

With reference to the second aspect, in a first possible implementation manner, a 2:1 multiplexer includes a first flip-flop, a second flip-flop, a third flip-flop, and a 2:1 selector;

The input end of the first flip-flop receives the first data signal with frequency f, the clock signal end of the first flip-flop receives the clock signal with frequency f, and the output end of the first flip-flop is connected to the 2 : 1 first input terminal of the selector;

The input end of the second flip-flop receives the second data signal with frequency f, the clock signal end of the second flip-flop receives the clock signal with frequency f, and the output end of the second flip-flop is connected to the first The input terminals of three flip-flops; the clock signal end of the third flip-flop receives a clock signal complementary to the clock signal with frequency f, and the output end of the third flip-flop is connected to the second of the 2:1 selector input terminal; the control terminal of the 2:1 selector receives a clock signal complementary to the clock signal with frequency f;

The first flip-flop is used to synchronize the first data signal with frequency f with the clock signal with frequency f;

The second flip-flop is used to synchronize the second data signal with frequency f with the clock signal with frequency f;

The third flip-flop is used to shift the phase of the second data signal synchronized with the clock signal of frequency f by π;

The 2:1 selector is configured to connect the first input terminal to the output terminal of the 2:1 selector when the clock signal complementary to the clock signal with frequency f is a first level signal ; and when the clock signal complementary to the clock signal with frequency f is a second level signal, connecting the second input end to the output end of the 2:1 selector.

With reference to the second aspect or the first possible implementation manner of the second aspect, in the second possible implementation manner, the first flip-flop, the second flip-flop, and the third flip-flop are all D flip-flops.

With reference to the first possible implementation of the second aspect, in the third possible implementation, when the difference between half the period of the clock signal received by the 2:1 multiplexer and the total delay is less than The setup time of the flip-flop in the 2:1 multiplexer receiving the signal output from the 2:1 multiplexer when receiving the 2:1 multiplexer The multiplexer also includes a delayer;

The delayer is used to delay the clock signal received by the 2 frequency divider that provides the clock signal to the 2:1 multiplexer for a preset period of time, and send the clock signal delayed by the preset period of time to the receiver The 2:1 multiplexer outputs the signal to the 2:1 multiplexer.

In combination with any one of the second aspect, the first possible implementation of the second aspect, and the second possible implementation of the second aspect, in a fourth possible implementation, when the two-frequency divider When the second setting circuit is included, the setting signal received by the two-frequency divider is received by the high-speed multiplexer through a synthesis circuit where the two-frequency divider is located. obtained after synchronization of the clock signal.

In combination with the second aspect, any one of the first possible implementation manner of the second aspect to the fourth possible implementation manner of the second aspect, in a fifth possible implementation manner, the high-speed multiplexer It includes at least one buffer, and the at least one buffer is distributed in a clock tree, and is used to receive the clock signal sent to the high-speed multiplexer, and provide each synthesis circuit in the high-speed multiplexer clock signal;

Wherein, the output terminals of the buffers that output the clock signals for the respective synthesizing circuits in the high-speed multiplexer are directly connected; the clock signals provided for each synthesizing circuit are input to the first one of the synthesizing circuits A frequency divider by two, the output of the first frequency divider by two provides a clock signal for the last stage of the 2:1 multiplexer in the synthesis circuit.

With reference to the fifth possible implementation of the second aspect, in a sixth possible implementation, the clock signals received by the synthesis circuits in the high-speed multiplexer are all sent to the The clock signal of the high-speed multiplexer is obtained after being buffered by the same number of buffers in the at least one buffer.

With reference to the sixth possible implementation manner of the second aspect, in a seventh possible implementation manner, a transmission path of a clock signal output from a buffer that outputs a clock signal to multiple synthesizing circuits adopts a clock tree distribution.

The beneficial effects of the embodiments of the present invention include:

In the frequency divider by two and the high-speed multiplexer provided by the embodiment of the present invention, since the first output terminal of the frequency divider by two is at the second level when the setting signal is valid, the second frequency divider by two The output terminal is the first level, and after the setting signal changes from valid to invalid, after the first active edge, and before the nearest non-active edge after the active edge, the first output terminal of the frequency division by two is the second One level, the second output terminal of the two-frequency divider is the second level; wherein, the first active edge is the first time of the clock signal received by the two-frequency divider after the set signal changes from valid to invalid. along the function. That is to say, after the setting signal of the frequency divider provided by the embodiment of the present invention changes from valid to invalid, at the first active edge of the clock signal received by the frequency divider by two, the frequency divider by two The first output terminal outputs the first level, and the second output terminal of the two-frequency divider outputs the second level. Therefore, the initial phase of the two-frequency divider provided by the embodiment of the present invention is constant, which avoids the use of the two-frequency divider. The high-speed multiplexer sampling error of the frequency converter.

Description of drawings

FIG. 1 is a schematic structural diagram of a 2:1 multiplexer in the prior art;

FIG. 2 is one of the structural schematic diagrams of a two-frequency divider provided by an embodiment of the present invention;

Fig. 3 is a timing diagram of the frequency divider shown in Fig. 2;

FIG. 4 is the second structural schematic diagram of a two-frequency divider provided by an embodiment of the present invention;

FIG. 5 is a timing diagram of the two frequency divider shown in FIG. 4;

FIG. 6 is a schematic structural diagram of a synthesis circuit in a high-speed multiplexer provided by an embodiment of the present invention;

FIG. 7 is a schematic structural diagram of a 2:1 multiplexer in the high-speed multiplexer provided by the embodiment of the present invention;

FIG. 8 is a working sequence diagram of the 2:1 multiplexer shown in FIG. 7;

Fig. 9 is one of the circuit structure diagrams when signals are transmitted between connected two-stage 2:1 multiplexers;

The working sequence diagram of the circuit shown in Fig. 10 Fig. 9;

The second circuit structure diagram of Fig. 11 when signals are transmitted between connected two-stage 2:1 multiplexers;

Fig. 12 is a working sequence diagram of the circuit shown in Fig. 11;

FIG. 13 is a schematic diagram of the connection structure of each two frequency divider when the two frequency divider in a synthesis circuit in the high-speed multiplexer provided by the embodiment of the present invention adopts the structure shown in FIG. 2 ;

FIG. 14 is a schematic diagram of the connection structure of each two-frequency divider when the two-frequency divider in a synthesis circuit in the high-speed multiplexer provided by the embodiment of the present invention adopts the structure shown in FIG. 4 ;

FIG. 15 is one of the structural schematic diagrams of the clock tree in the high-speed multiplexer provided by the embodiment of the present invention;

FIG. 16 is the second structural schematic diagram of the clock tree in the high-speed multiplexer provided by the embodiment of the present invention.

Detailed ways

The frequency divider by two and the high-speed multiplexer provided by the embodiment of the present invention control the frequency divider by a set signal. When the set signal is valid, the first output terminal of the frequency divider by two is at the second level. The second output terminal of the two-frequency divider is the first level; and after the setting signal is changed from valid to invalid, the two-frequency divider is controlled on the first active edge of the clock signal received by the two-frequency divider, The first output terminal of the two-frequency divider outputs the first level, and the second output terminal of the two-frequency divider outputs the second level, so that the initial phase of the two-frequency divider is constant, and then the two-frequency divider is used The high-speed multiplexer of the device is correctly sampled.

The specific implementation manners of a frequency divider by two and a high-speed multiplexer provided in the embodiments of the present invention will be described below with reference to the drawings in the description.

A two-frequency divider provided by an embodiment of the present invention, as shown in FIG. 2 , includes a first controllable switch SW1, a second controllable switch SW2, a third controllable switch SW3, a fourth controllable switch SW4, a first an inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a first latch 22, a second latch 23 and a first setting circuit 21;

One end of the first controllable switch SW1 is respectively connected to the input end of the first inverter INV1 and one end of the first latch 22, and the other end of the first controllable switch SW1 is connected to the output end of the fourth inverter INV4. The control terminal of a controllable switch SW1 receives the first control signal Ctr1;

One end of the second controllable switch SW2 is respectively connected to the input end of the second inverter INV2 and the other end of the first latch 22, and the other end of the second controllable switch SW2 is connected to the output end of the third inverter INV3, The control terminal of the second controllable switch SW2 receives the first control signal Ctr1;

One end of the third controllable switch SW3 is respectively connected to the output end of the first inverter INV1 and the first output end OUT1 of the frequency division by two, and the other end of the third controllable switch SW3 is respectively connected to one end of the second latch 23 and the input terminal of the third inverter INV3, the control terminal of the third controllable switch SW3 receives the second control signal Ctr2;

One end of the fourth controllable switch SW4 is respectively connected to the output end of the second inverter INV2 and the second output end OUT2 of the frequency division by two, and the other end of the fourth controllable switch SW4 is respectively connected to the other end of the second latch 23. One terminal and the input terminal of the fourth inverter INV4, and the control terminal of the fourth controllable switch SW4 receives the second control signal Ctr2;

The first setting circuit 21 is used to load the first level signal to the input terminal of the first inverter INV1 when the setting signal SET is effective, so that the first output terminal OUT1 of the frequency divider by two is the second level signal. level; and load the second level signal to the input terminal of the second inverter INV2, so that the second output terminal OUT2 of the two frequency divider is the first level; and when the setting signal SET is invalid, stop supplying the second level signal The input terminal of an inverter INV1 and the input terminal of a second inverter INV2 are loaded with signals;

The first control signal Ctr1 is complementary to the second control signal Ctr2, that is, when the first control signal Ctr1 is at a high level, the second control signal Ctr2 is at a low level, and when the first control signal Ctr1 is at a low level, the second control signal Ctr2 is High level; after the setting signal SET changes from valid to invalid, the first control signal Ctr1 is a clock signal, and the second control signal Ctr2 is a clock blocking signal;

Both the first controllable switch SW1 and the second controllable switch SW2 are used to close when the first control signal Ctr1 is a first level signal, and to turn off when the first control signal Ctr1 is a second level signal;

Both the third controllable switch SW3 and the fourth controllable switch SW4 are used to close when the second control signal Ctr2 is a signal of the first level, and to open when the second control signal Ctr2 is a signal of the second level;

The first latch 22 is used to latch the signal at the input end of the first inverter INV1, and latch the signal at the input end of the second inverter INV2;

The second latch 23 is configured to latch the signal at the input terminal of the third inverter INV3 and latch the signal at the input terminal of the fourth inverter INV4 after the set signal SET changes from valid to invalid.

When the first level signal is a high level signal, the second level signal is a low level signal; when the first level signal is a low level signal, the second level signal is a high level signal.

Since the first setting circuit will load the first level signal to the input terminal of the first inverter when the setting signal is valid, so that the first inverter outputs the second level signal, and then the frequency division by two The first output terminal of the inverter is at the second level; and the first setting circuit will load the second level signal to the input terminal of the second inverter when the setting signal is valid, so that the second inverter outputs The signal of the first level further makes the second output end of the two frequency divider be at the first level.

That is to say, when the setting signal is valid, the first output terminal of the frequency divider by two is always at the second level, and the second output terminal of the frequency divider by two is always at the first level.

The first setting circuit 21 in the two frequency divider shown in Fig. 2 will not load the signal to the input terminal of the first inverter INV1 again when the setting signal SET is changed from valid to invalid; therefore, in the clock signal After an active edge of , before the nearest non-active edge after the active edge, that is, both the first controllable switch SW1 and the second controllable switch SW2 are closed, and the third controllable switch SW3 and the fourth controllable switch SW4 are both open , the input terminal of the first inverter INV1 receives the signal of the output terminal of the fourth inverter INV4, and at this time, the signal of the output terminal of the fourth inverter INV4 is the nearest inactive edge before the active edge and before the active edge After the edge (that is, when the first controllable switch SW1 and the second controllable switch SW2 are both off, and the third controllable switch SW3 and the fourth controllable switch SW4 are both closed), the input terminal of the fourth inverter INV4 An inverted signal of the received signal, that is, an inverted signal of the output terminal of the second inverter INV2.

When the first level is high level and the second level is low level, the active edge of the clock signal is the rising edge of the clock signal, and the non-active edge of the clock signal is the falling edge of the clock signal; when the first level is low level, the second level is high level, the active edge of the clock signal is the falling edge of the clock signal, and the inactive edge of the clock signal is the rising edge of the clock signal.

When the active edge is the first active edge of the clock signal received by the frequency divider after the set signal is changed from valid to invalid, before the active edge and after the nearest non-active edge before the active edge, The signal at the output terminal of the second inverter is the signal output by the second inverter when the set signal is valid, that is, the first level signal. Therefore, after the first active edge, the nearest active edge after the active edge Before the non-active edge, the signal received by the input terminal of the first inverter is the second level signal, and at this time, the first inverter outputs the first level signal, that is, the first output terminal of the two frequency divider is the first level; and after the nearest non-active edge after the first active edge and before the second active edge of the clock signal, the signal at the input terminal of the first inverter latched in the first latch After the first active edge and before the nearest non-active edge after the active edge, the signal at the input terminal of the first inverter, that is, the second level signal, therefore, the first inverter After the flat signal is reversed, the first level is still output, that is to say, after the first active edge of the clock signal received by the frequency divider after the set signal changes from valid to invalid, the set signal changes from valid to invalid. Before the second active edge of the clock signal received by the frequency divider after becoming invalid, the first output terminal of the frequency divider by two is at the first level.

When the active edge is the nth (n is greater than 1) active edge of the clock signal received by the frequency divider after the set signal changes from valid to invalid, the nearest active edge before the active edge After the non-active edge, the signal at the output of the second inverter is the n-1th function of the clock signal received by the two frequency divider after the second inverter changes from valid to invalid. After the edge, the signal output before the nearest non-active edge after the n-1th active edge, therefore, after the set signal changes from valid to invalid, the nth active edge of the clock signal received by the frequency divider After that, before the nearest non-active edge after the active edge, the signal at the input terminal of the first inverter is the nth clock signal received by the two frequency divider after the set signal changes from valid to invalid. Before the active edge, after the nearest non-active edge before the active edge, the signal at the output of the second inverter is inverted, that is, after the set signal changes from valid to invalid, the two-frequency divider receives Before the nth active edge of the received clock signal and after the n-1th active edge, the signal at the output end of the second inverter is inverted. Therefore, after the set signal changes from valid to invalid, the two After the nth active edge of the clock signal received by the frequency divider and before the nearest non-active edge after the active edge, the signal output by the first inverter is after the set signal changes from valid to invalid. The signal at the output of the second inverter before the nth active edge of the clock signal received by the frequency divider and after the n-1th active edge; and after the nearest non-active edge after the nth active edge, Before the n+1th active edge, the signal at the input terminal of the first inverter latched in the first latch is after the nth active edge and before the nearest non-active edge after the active edge, the first inverter Therefore, after the set signal changes from active to inactive, after the nth active edge of the clock signal received by the frequency divider, after the nearest non-active edge, the n+1th active The signal output by the first inverter before the edge is still before the nth active edge and after the n-1th active edge of the clock signal received by the frequency divider after the set signal changes from valid to invalid signal at the output of the second inverter.

The first setting circuit 21 in the two-frequency divider shown in Figure 2 will not load the signal to the input end of the second inverter INV2 after the setting signal SET is changed from valid to invalid; therefore, in the clock signal After an active edge of , before the nearest non-active edge after the active edge, that is, both the first controllable switch SW1 and the second controllable switch SW2 are closed, and the third controllable switch SW3 and the fourth controllable switch SW4 are both open , the input terminal of the second inverter INV2 receives the signal of the output terminal of the third inverter INV3, and at this time, the signal of the output terminal of the third inverter INV3 is the nearest non-active edge before the active edge and before the active edge After the edge (that is, when the first controllable switch SW1 and the second controllable switch SW2 are both off, and the third controllable switch SW3 and the fourth controllable switch SW4 are both closed), the input terminal of the third inverter INV3 An inverted signal of the received signal, that is, an inverted signal of the output terminal of the first inverter INV1.

When the active edge is the first active edge of the clock signal received by the frequency divider after the set signal is changed from valid to invalid, before the active edge and after the nearest non-active edge before the active edge, The signal at the output terminal of the first inverter is the signal output by the first inverter when the set signal is valid, that is, the second level signal. Therefore, after the first active edge, the nearest active edge after the active edge Before the non-active edge, the signal received by the input terminal of the second inverter is the first level signal, at this time, the second inverter outputs the second level signal, that is, the second output terminal of the frequency divider is the second level; and after the nearest non-active edge after the first active edge and before the second active edge of the clock signal, the signal at the input terminal of the second inverter latched in the first latch After the first active edge and before the nearest non-active edge after the active edge, the signal at the input terminal of the second inverter, that is, the first level signal, therefore, the second inverter After the flat signal is inverted, the second level is still output, that is to say, after the first active edge of the clock signal received by the frequency divider after the set signal changes from valid to invalid, the set signal changes from valid to invalid. Before the second active edge of the clock signal received by the frequency divider after becoming invalid, the second output terminal of the frequency divider is at the second level.

When the active edge is the nth (n is greater than 1) active edge of the clock signal received by the frequency divider after the set signal changes from valid to invalid, the nearest active edge before the active edge After the non-active edge, the signal at the output end of the first inverter is the n-1th function of the clock signal received by the frequency divider after the first inverter changes from valid to invalid. After the edge, the signal output before the nearest non-active edge after the n-1th active edge, therefore, after the set signal changes from valid to invalid, the nth active edge of the clock signal received by the frequency divider After that, before the nearest non-active edge after the active edge, the signal at the input end of the second inverter is the nth clock signal received by the frequency divider after the set signal changes from valid to invalid. Before the active edge, after the nearest non-active edge before the active edge, the signal at the output of the first inverter is inverted, that is, after the set signal is changed from valid to invalid, the two frequency divider receives Before the nth active edge of the received clock signal and after the n-1th active edge, the signal at the output terminal of the first inverter is inverted. Therefore, after the set signal changes from valid to invalid, the two After the nth active edge of the clock signal received by the frequency divider, the signal output by the second inverter before the nearest non-active edge after the active edge is after the set signal changes from valid to invalid, the two The signal at the output of the first inverter before the nth active edge of the clock signal received by the frequency divider and after the n-1th active edge; and after the nearest non-active edge after the nth active edge, Before the n+1th active edge, the signal at the input terminal of the second inverter latched in the first latch is after the nth active edge and before the nearest non-active edge after the active edge, the second inverter Therefore, after the set signal changes from active to inactive, after the nth active edge of the clock signal received by the frequency divider, after the nearest non-active edge, the n+1th active The signal output by the second inverter before the edge is still before the nth active edge and after the n-1th active edge of the clock signal received by the frequency divider after the set signal changes from valid to invalid signal at the output of the first inverter.

According to the above description, it can be known that the two-level frequency divider provided by the embodiment of the present invention outputs a second level signal through the first output terminal of the two-frequency divider when the set signal is valid, and outputs a second level signal through the two-frequency divider. The output end outputs a first level signal. The two-frequency divider provided by the embodiment of the present invention passes through the two-way frequency divider after the setting signal changes from valid to invalid, after the first active edge of the clock signal received by the two-frequency divider, and before the second active edge. The first output terminal of the frequency divider outputs the first level signal, and outputs the second level signal through the second output terminal of the frequency divider, so that when the setting signal changes from valid to invalid, a signal with a determined phase is output . In the frequency divider provided by the embodiment of the present invention, after the setting signal changes from valid to invalid, after the nth (n is greater than 1) active edge of the clock signal received by the frequency divider, the n+1th active edge Before the edge, the signal output by the first output terminal of the two-frequency divider, and the n-1th clock signal received by the two-frequency divider after the setting signal of the two-frequency divider changes from valid to invalid After the active edge and before the nth active edge, the signal output by the second output terminal of the two-frequency divider is the same; the two-frequency divider provided by the embodiment of the present invention changes from valid to invalid after the setting signal. After the nth (n is greater than 1) active edge and before the n+1th active edge of the clock signal received by the two-frequency divider, the signal output through the second output terminal of the two-frequency divider is the same as the two The frequency divider passes through the first output of the frequency divider after the n-1th active edge of the clock signal received by the two frequency divider and before the nth active edge after the set signal changes from valid to invalid The signals output by the terminal are the same; thus, after the setting signal is changed from valid to invalid, the frequency of the output signal of the two-frequency divider is half of the frequency of the clock signal received by the two-frequency divider, thereby realizing the After the signal changes from valid to invalid, the function of dividing the frequency of the received clock signal by two.

Optionally, in the frequency divider provided by the embodiment of the present invention, when the set signal SET is valid, the first control signal Ctr1 is set to the second level signal, and the second control signal Ctr2 is set to the first level signal .

Therefore, the first setting circuit 21 in the two frequency divider shown in FIG. The input terminal of the inverter INV2 is loaded with a second level signal; since the first control signal Ctr1 is a second level signal and the second control signal Ctr2 is a first level signal when the set signal SET is valid, therefore, the set When the bit signal SET is valid, both the first controllable switch SW1 and the second controllable switch SW2 are turned off, and the third controllable switch SW3 and the fourth controllable switch SW4 are both closed, so the first inverter INV1 outputs the second level signal, the first output terminal OUT1 of the two frequency divider is the second level, the second inverter INV2 outputs the first level signal, and the second output terminal OUT2 of the two frequency divider is the first level and, when the set signal SET is valid, the input terminal of the third inverter INV3 is at the second level, and the input terminal of the fourth inverter INV4 is at the first level.

That is to say, when the setting signal is valid, the first output terminal OUT1 of the frequency divider shown in FIG. 2 is always at the second level, and the second output terminal OUT2 of the frequency divider is always at the first level. level.

When the first level is high and the second level is low, the active edge of the clock signal is the rising edge of the clock signal, the inactive edge of the clock signal is the falling edge of the clock signal, and the set signal is high When the set signal is valid and the low level is invalid, the circuit timing diagram of the two-frequency divider shown in FIG. 2 is shown in FIG. 3 .

In Fig. 3, when the setting signal is effective, the first output end of the frequency divider shown in Fig. 2 is the second level, and the second output end of the frequency divider is the first level; and in After the setting signal changes from valid to invalid, and before the first active edge of the first control signal after the setting signal changes from valid to invalid, the first output terminal of the two-frequency divider is at the second level, and the two-divider The second output terminal of the frequency converter is the first level; and after the first active edge of the first control signal after the setting signal changes from valid to invalid, before the second active edge of the first control signal, the two The first output terminal of the frequency divider is at the first level, and the second output terminal of the two-frequency divider is at the second level. After the nth (n is greater than 1) active edge of the first control signal after the set signal changes from active to inactive, and before the n+1 active edge of the first control signal, the first output of the two frequency divider The level of the terminal, after the n-1th active edge of the first control signal after the set signal changes from valid to invalid, and before the nth active edge of the first control signal, the second output of the two frequency divider The level of the terminal is the same; after the nth (n is greater than 1) active edge of the first control signal after the set signal changes from valid to invalid, and before the n+1th active edge of the first control signal, the two-frequency The level of the second output terminal of the device, after the n-1th active edge of the first control signal after the set signal is changed from valid to invalid, and before the nth active edge of the first control signal, the frequency division by two The level of the first output terminal of the device is the same.

It can be seen from Figure 3 that each transparent transmission time is half a cycle of the clock signal received by the frequency divider, and each inversion time is half a cycle of the clock signal received by the frequency divider; The time is used to close the third controllable switch in Fig. 2, transmit the signal of the output end of the first inverter to the input end of the third inverter, and latch it in the second latch; The fourth controllable switch in Figure 2 is closed, and the signal at the output terminal of the second inverter is transmitted to the input terminal of the fourth inverter, and is latched in the second latch; the inversion time is used to convert the signal of Figure 2 The first controllable switch in is closed, and the signal from the output terminal of the fourth inverter is transmitted to the input terminal of the first inverter, and is latched in the first latch, and is used to convert the second controllable switch in Fig. The control switch is closed, and the signal at the output terminal of the third inverter is transmitted to the input terminal of the second inverter, and is latched in the first latch.

Optionally, the frequency divider by two provided in the embodiment of the present invention is shown in FIG. 4, and further includes a second setting circuit 24; when the setting signal is valid, the first control signal is a clock signal, and the second The control signal is a clock blocking signal;

Wherein, the clock blocking signal CLKB is complementary to the clock signal CLK, that is, when the clock blocking signal CLKB is at the first level, the clock signal CLK is at the second level, and when the clock blocking signal CLKB is at the second level, the clock signal CLK is at the first level ; On an active edge of the clock signal CLK, both the first controllable switch SW1 and the second controllable switch SW2 change from open to closed, and the third controllable switch SW3 and the fourth controllable switch SW4 both change from closed to open open; on an inactive edge of the clock signal CLK, both the first controllable switch SW1 and the second controllable switch SW2 change from closed to open, and the third controllable switch SW3 and the fourth controllable switch SW4 both change from open to become closed;

The second setting circuit 24 is used to load the first level signal to the input terminal of the third inverter INV3 and load the second level signal to the input terminal of the fourth inverter INV4 when the set signal SET is valid. signal; and when the set signal SET is invalid, stop loading signals to the input terminal of the third inverter INV3 and the input terminal of the fourth inverter INV4;

Wherein, the driving capability of the part of the second setting circuit 24 that loads the signal to the input terminal of the third inverter INV3 is greater than the driving capability of the first inverter INV1, and the driving capability of the second setting circuit 24 to the fourth inverter INV3 is greater than that of the first inverter INV1. The driving capability of the part where the signal is loaded on the input terminal of the inverter INV4 is greater than the driving capability of the second inverter INV2.

The first set circuit 21 in the two frequency divider shown in FIG. 4 will load the first level signal to the input terminal of the first inverter INV1 when the set signal SET is valid, and will load the first level signal to the second inverter INV1 The input terminal of the device INV2 is loaded with a second level signal; when the clock signal CLK is at the first level, the clock blocking signal CLKB is at the second level, at this time, both the first controllable switch SW1 and the second controllable switch SW2 are closed, Both the third controllable switch SW3 and the fourth controllable switch SW4 are turned off, therefore, the first inverter INV1 outputs a signal of the second level, the first output terminal OUT1 of the two frequency divider is at the second level, and the second The two inverter INV2 outputs the first level signal, and the second output terminal OUT2 of the two frequency divider is at the first level; when the clock signal CLK is at the second level, the clock blocking signal CLKB is at the first level, and the , both the first controllable switch SW1 and the second controllable switch SW2 are turned off, and the third controllable switch SW3 and the fourth controllable switch SW4 are both closed. Since the third inverter INV3 in the second setting circuit 24 The driving capability of the part where the signal is loaded at the input terminal of the first inverter INV1 is greater than the driving capability of the first inverter INV1. Therefore, even if the second setting circuit 24 loads the first level signal to the input terminal of the third inverter INV3, the two The first output terminal OUT1 of the frequency divider is still at the second level; because the driving capability of the part of the second setting circuit 24 that loads the signal to the input terminal of the fourth inverter INV4 is greater than that of the second inverter INV2 Therefore, even if the second setting circuit 24 loads the second level signal to the input terminal of the fourth inverter INV4, the second output terminal OUT2 of the frequency divider by two is at the first level.

That is to say, when the setting signal is valid, the first output terminal OUT1 of the two-frequency divider shown in FIG. 4 is always at the second level, and the second output terminal OUT2 of the two-frequency divider is always at the first level. level.

The first setting circuit 21 in the two-frequency divider shown in FIG. 4 will no longer load a signal to the input terminal of the first inverter INV1 after the setting signal SET changes from valid to invalid, and will no longer load the signal to the input terminal of the first inverter INV1 The input terminal of the second inverter INV2 is loaded with a signal, and the second setting circuit 24 in the two frequency divider will not load a signal to the input terminal of the third inverter INV3 when the setting signal SET is invalid, and No signal will be loaded to the input terminal of the fourth inverter INV4; therefore, the working principle of the frequency divider by two shown in Fig. The working principle of the frequency converter is the same after the setting signal SET is changed from valid to invalid, and will not be repeated here.

When the first level is high and the second level is low, the active edge of the clock signal is the rising edge of the clock signal, the inactive edge of the clock signal is the falling edge of the clock signal, and the set signal is high When the set signal is valid and the low level is invalid, the circuit timing diagram of the two-frequency divider shown in FIG. 4 is shown in FIG. 5 .

In Fig. 5, when the setting signal is effective, the first output end of the frequency divider shown in Fig. 4 is the second level, and the second output end of the frequency divider is the first level; and in After the setting signal changes from valid to invalid, before the first active edge of the clock signal received by the frequency divider after the setting signal changes from valid to invalid, the first output terminal of the frequency divider is the second Level, the second output terminal of the two-frequency divider is the first level; and after the first active edge of the clock signal received by the two-frequency divider after the set signal changes from valid to invalid, the two Before the second active edge of the clock signal received by the frequency divider, the first output terminal of the two-frequency divider is at the first level, and the second output terminal of the two-frequency divider is at the second level. After the nth (n is greater than 1) active edge of the clock signal received by the two-frequency divider after the set signal changes from valid to inactive, the n+1th active edge of the clock signal received by the two-frequency divider Before the edge, the level of the first output terminal of the two-frequency divider, and after the n-1th active edge of the clock signal received by the two-frequency divider after the set signal changes from active to inactive, the two-frequency divider Before the nth active edge of the clock signal received by the frequency divider, the level of the second output terminal of the frequency divider is the same; after the set signal changes from valid to invalid, the level of the clock signal received by the frequency divider After the nth (n is greater than 1) active edge, before the n+1th active edge of the clock signal received by the two-frequency divider, the level of the second output terminal of the two-frequency divider is the same as the set signal After the n-1th active edge of the clock signal received by the two-frequency divider after it becomes invalid, before the n-th active edge of the clock signal received by the two-frequency divider, the two-frequency divider The levels of the first output terminals are the same.

The set signal can transition when the clock signal is at a high level (in Figure 5, the set signal is illustrated as an example when the clock signal is at a high level), or it can transition when the clock signal is at a low level. However, it is not allowed to jump when the clock signal jumps to avoid possible metastable states. When the set signal jumps when the clock signal is high, then after the set signal changes from valid to invalid, each transparent transmission time is half a cycle of the clock signal; when the set signal is low when the clock signal jump, then before the first active edge of the clock signal after the set signal changes from valid to invalid and after the set signal changes from valid to invalid, the transparent transmission time is less than half a period of the clock signal, while the rest of the transparent transmission time The transmission time is half a period of the clock signal; when the transparent transmission time is too small, it will cause the output signal error of the frequency divider by two. Therefore, preferably, the setting signal received by the divider-by-two is changed from valid to invalid when the clock signal it receives is at the first level. Wherein, the transparent transmission time is used to close the third controllable switch in Fig. 4, transmit the signal of the output end of the first inverter to the input end of the third inverter, and lock it in the second latch; And it is used to close the fourth controllable switch in FIG. 4 , transmit the signal at the output terminal of the second inverter to the input terminal of the fourth inverter, and latch it in the second latch.

When the setting signal changes from valid to invalid, each inversion time is half a cycle of the clock signal, wherein the inversion time is used to close the first controllable switch in Figure 4 and turn the fourth inverter The signal at the output terminal of the first inverter is transmitted to the input terminal of the first inverter, and is latched in the first latch, and is used to close the second controllable switch in Figure 2, and transmits the signal at the output terminal of the third inverter to the input of the second inverter and latched in the first latch.

所述一路高速信号的传输速度为所述2ⁿ路低速信号之和；A high-speed multiplexer provided by an embodiment of the present invention includes at least one synthesizing circuit, wherein one synthesizing circuit (as shown in FIG. 6, taking n=3 as an example in FIG. 6) includes k 2:1 multiplexers Multiplexers (4 first-stage 2:1 multiplexers 611 in Figure 6, two second-stage 2:1 multiplexers 612 and one third-stage 2:1 Multiplexer 613) and n two frequency dividers 62 provided by the embodiment of the present invention, the one synthesizing circuit is used to synthesize a group of 2 ^n- way low-speed signals into a group of one-way high-speed signal circuits, k and n are positive integers,

The transmission speed of the one high-speed signal is the sum of the 2 ⁿ low-speed signals;

In a synthesis circuit, the same stage of 2:1 multiplexer 61 receives the same frequency clock signal, the first stage of 2:1 multiplexer receives the low speed signal, and the last stage of 2:1 multiplexer The signal output by the user is the high-speed signal, and the signal received by each level of 2:1 multiplexer except the first level of 2:1 multiplexer is the signal received by the previous level of 2:1 multiplexer The signal output by the user; the clock signal received by the 2:1 multiplexer at all levels except the last level of 2:1 multiplexer is the last 2:1 multiplexer of this level Stage 2: The clock signal received by the multiplexer is divided by a frequency divider by 62 to output the signal;

Each 2:1 multiplexer is used for synthesizing two received signals with a frequency of f into one with a frequency of 2 under the control of a clock signal with a frequency f output by the frequency divider 62 *f signal.

Wherein, a 2:1 multiplexer, as shown in FIG. 7 , includes a first flip-flop 71, a second flip-flop 72, a third flip-flop 73 and a 2:1 selector 74;

The input end of the first flip-flop 71 receives the first data signal P1 with frequency f, the clock signal end CLK of the first flip-flop 71 receives the clock signal CLK1 with frequency f, and the output end of the first flip-flop 71 is connected to 2:1 a first input terminal of the selector 74;

The input end of the second flip-flop 72 receives the second data signal P2 whose frequency is f, the clock signal end CLK of the second flip-flop 72 receives the clock signal CLK1 whose frequency is f, and the output end of the second flip-flop 72 is connected to the third trigger The input terminal of the device 73; the clock signal terminal CLK of the third flip-flop 73 receives the clock signal CLK2 complementary to the clock signal CLK1 with a frequency of f, and the output terminal of the third flip-flop 73 is connected to the second input of the 2:1 selector 74 terminal; the control terminal C of the 2:1 selector 74 receives the complementary clock signal CLK2 of the clock signal CLK1 whose frequency is f;

The first flip-flop 71 is configured to synchronize the first data signal P1 with frequency f with the clock signal CLK1 with frequency f, and output the synchronized first data signal P11;

The second flip-flop 72 is configured to synchronize the second data signal P2 with frequency f with the clock signal CLK1 with frequency f, and output the synchronized second data signal P21;

The third flip-flop 73 is configured to shift the phase of the second data signal P21 synchronized with the clock signal CLK1 with a frequency f by π, and output the phase-shifted second data signal P22;

The 2:1 selector 74 is used to connect the first input terminal of the 2:1 selector 74 with the 2:1 selector when the clock signal CLK2 complementary to the clock signal CLK1 with frequency f is a first level signal The output terminal of 74 is connected; And when the clock signal CLK2 complementary to the clock signal CLK1 with frequency f is the second level signal, the second input terminal of the 2:1 selector 74 is connected with the 2:1 selector 74 The output terminal is connected.

When the delay of the first flip-flop, the delay of the second flip-flop and the delay of the third flip-flop in a 2:1 multiplexer are all the first delay, the 2:1 multiplexer The hold time of the 2:1 selector in the multiplexer is less than the first delay, and the setup time of the 2:1 selector in the 2:1 multiplexer is less than the 2:1 multiplexer received The difference between half the cycle of the clock signal and the first time delay;

The difference between half the period of the clock signal received by a 2:1 multiplexer and the total delay is greater than that of a 2:1 multiplexer receiving the signal output by the 2:1 multiplexer The setup time of the trigger, and the total delay is greater than the hold time of the trigger in the 2:1 multiplexer receiving the signal output by the 2:1 multiplexer, wherein the total delay is the sum of the time delay of the 2:1 selector in the 2:1 multiplexer and the time delay of the 2 frequency divider that provides the clock signal for the 2:1 multiplexer.

Among them, each flip-flop in a 2:1 multiplexer, such as the first flip-flop, the second flip-flop, and the third flip-flop, can be a D flip-flop, or a JK flip-flop, RS flip-flop A flip-flop that can realize the function of a D flip-flop.

FIG. 7 also includes a two-frequency divider 62 for reducing the frequency of the received clock signal CLK _in by half, and outputting two complementary clock signals whose frequency has been reduced by half.

If the first level is high level and the second level is low level, the active edge of the clock signal is the rising edge of the clock signal, the inactive edge of the clock signal is the falling edge of the clock signal, and the 2:1 selector is When its own control terminal is at a high level, connect its first input terminal with its own output terminal, and when its own control terminal is at a low level, connect its own second input terminal with its own output terminal, The circuit timing diagram of the two frequency divider shown in FIG. 7 is shown in FIG. 8 .

In Fig. 8, the time delay of the first flip-flop, the time delay of the second flip-flop and the time delay of the third flip-flop are all Dly_Dff, that is to say, when Dly_Dff after the active edge of the clock signal CLK1, the first The synchronized first data signal P11 output by the flip-flop changes, and at Dly_Dff after the active edge of the clock signal CLK2 complementary to the clock signal CLK1, the phase-shifted second data signal P22 output by the third flip-flop changes , due to a period of time before the moment when the signal at the control terminal of the 2:1 selector changes (that is, the transition edge of the clock signal, including the rising edge of the clock signal and the falling edge of the clock signal), that is, within the setup time, and A period of time after the moment when the signal at the control end of the 2:1 selector changes, that is, within the holding time, the input signal received by the 2:1 selector changes, which may cause an error in the output of the 2:1 selector. Therefore, In Fig. 7, the hold time of 2:1 selector 74 is less than Dly_Dff, and the setup time of 2:1 selector 74 is less than T_CLK1/2-Dly_Dff, wherein, T_CLK1/2 is that the first flip-flop and the second flip-flop receive Half of the period of the clock signal CLK1, because the period of the clock signal CLK1 received by the first flip-flop and the second flip-flop is equal to the period of the clock signal CLK2 received by the third flip-flop, therefore, T_CLK1/2-Dly_Dff and T_CLK2 /2−Dly_Dff, T_CLK2/2 is half of the period of the clock signal CLK2 received by the third flip-flop 73 and the 2:1 selector 74 . That is to say, a reasonable selection of the flip-flops and 2:1 selectors in the 2:1 multiplexer can make the delay of the flip-flops (including the first flip-flop, the second flip-flop and the third flip-flop) effective Utilization, to solve the problem of tight timing in the process of high-frequency signal processing.

When the signal is transmitted between two stages of 2:1 multiplexers, the circuit structure is shown in Figure 9, the 2:1 selector is located in the nth stage of 2:1 multiplexer, and the first flip-flop is located in In the n+1th stage 2:1 multiplexer, of course, the second flip-flop can also receive the signal output by the 2:1 selector. In Figure 9, only the first flip-flop receives the signal output by the 2:1 selector. signal as an example. If the first level is high level and the second level is low level, the active edge of the clock signal is the rising edge of the clock signal, the inactive edge of the clock signal is the falling edge of the clock signal, and the 2:1 selector is When its own control terminal is at a high level, connect its first input terminal with its own output terminal, and when its own control terminal is at a low level, connect its own second input terminal with its own output terminal, The circuit timing diagram of the two-frequency divider shown in FIG. 9 is shown in FIG. 10 .

In FIG. 10 , Dly_div is the time delay of the frequency divider providing control signals for the 2:1 selector in FIG. 9 , and Dly_Mux is the time delay of the 2:1 selector in FIG. 9 . At Dly_div+Dly_Mux after the active edge of the clock signal with frequency f, the signal output by the 2:1 selector changes, so the hold time of the first flip-flop receiving the signal output by the 2:1 selector in Figure 9 Less than Dly_div+Dly_Mux, the setup time of the first flip-flop receiving the signal output by the 2:1 selector in FIG. 9 is less than 1/f-(Dly_div+Dly_Mux). That is to say, it is reasonable to select the flip-flop in the 2:1 multiplexer that receives the signal output by a 2:1 multiplexer, and the 2:1 in the 2:1 multiplexer can be selected The time delay of the device is effectively used to solve the problem of tight timing in the process of high-frequency signal processing.

Data_Mux in FIG. 10 refers to the signal output by the 2:1 selector 74 in FIG. 9 , and Data_DFF in FIG. 10 refers to the signal output by the first flip-flop 71 in FIG. 9 .

As the frequency of the clock signal continues to increase, the period of the clock signal continues to decrease, and 1/f-(Dly_div+Dly_Mux) gradually becomes smaller, so that the establishment time of the first flip-flop is greater than or equal to 1/f-(Dly_div+Dly_Mux ), when the signal is transmitted between two stages of 2:1 multiplexers, the circuit structure is shown in Figure 11. In FIG. 11, a delayer 111 may also be included, which is used to provide the nth level 2: 1 multiplexer (only the nth level 2: 1 multiplexer is shown in FIG. 11 2:1 selector 74) The two frequency divider 62 that provides the clock signal delays the clock signal received by the preset time, and sends the clock signal after the preset time delay to the receiver that receives the output of the 2:1 multiplexer The 2:1 multiplexer of the signal, that is, the n+1th stage 2:1 multiplexer (only the first one of the n+1th stage 2:1 multiplexer is shown in Figure 11 flip-flop 71); wherein, sending the clock signal delayed by a preset time length to the n+1th stage 2:1 multiplexer refers to sending the clock signal delayed by a preset time length to the n+1th stage The clock signal terminal of the first flip-flop in the 2:1 multiplexer, and the clock signal terminal of the second flip-flop in the n+1th stage of the 2:1 multiplexer, and will be delayed by a preset time The complementary clock signal of the last clock signal is sent to the clock signal terminal of the third flip-flop in the n+1th stage 2:1 multiplexer, and the clock signal terminal of the n+1th stage 2:1 multiplexer The control terminal of the 2:1 selector;

Wherein, half of the period of the clock signal received by the first flip-flop in the n-th stage 2:1 multiplexer, that is, the sum of the difference between 1/f and the total time delay and the preset time length is greater than The setup time of the flip-flop in the 2:1 multiplexer receiving the signal output by the 2:1 multiplexer; the difference between the total delay and the preset duration is greater than the receiving time of the The hold time of the flip-flops in the 2:1 multiplexer for the signal output by the 2:1 multiplexer; the total delay is the 2:1 selector in the nth stage of the 2:1 multiplexer The sum of the time delay Dly_Mux of and the time delay Dly_DFF of the two frequency divider 62 that provides the clock signal for the n-th stage 2:1 multiplexer.

If the first level is high level and the second level is low level, the active edge of the clock signal is the rising edge of the clock signal, the inactive edge of the clock signal is the falling edge of the clock signal, and the 2:1 selector is When its own control terminal is at a high level, connect its first input terminal with its own output terminal, and when its own control terminal is at a low level, connect its own second input terminal with its own output terminal, The circuit timing diagram of the two-frequency divider shown in FIG. 11 is shown in FIG. 12 .

In FIG. 12 , Dly_div is the time delay of the divider-by-two providing control signal for the 2:1 selector in FIG. 11 , and Dly_Mux is the time delay of the 2:1 selector in FIG. 11 . At Dly_div+Dly_Mux after the active edge of the clock signal with frequency f, the signal output by the 2:1 selector changes, but due to, Figure 11 (Figure 11 only receives the signal output by the 2:1 selector with the first flip-flop The signal is taken as an example to illustrate, the second flip-flop receives the signal output by the 2:1 selector (similar to this), the clock signal output to the first flip-flop is delayed by Dly_B after passing through the delayer, therefore, in Figure 11 The hold time of the first flip-flop receiving the signal output by the 2:1 selector is less than Dly_div+Dly_Mux-Dly_B, and the setup time of the first flip-flop receiving the signal output by the 2:1 selector in Figure 11 is less than 1/f+Dly_B -(Dly_div+Dly_Mux).

Data_Mux in FIG. 12 refers to the signal output by the 2:1 selector 74 in FIG. 11 , and Data_DFF in FIG. 12 refers to the signal output by the first flip-flop 71 in FIG. 11 . CLK1_f_Dly in FIG. 12 is a signal output by the delayer 111 in FIG. 11 .

Preferably, when the second frequency divider includes a second set circuit, the set signal received by the two frequency divider is that the set signal sent to the high-speed multiplexer passes through the two It is obtained after synchronizing the clock signal received by the synthesizing circuit where the frequency converter is located. Wherein, the set signal received by the frequency divider by two can be synchronized with the clock signal received by the synthesizer circuit where the frequency divider by two is located, and the connection relationship between the frequency divider by two and the flip-flop DFF is shown in Figure 13 (In Fig. 13, only two synthesizing circuits are included in the high-speed multiplexer for illustration. Of course, more than two synthesizing circuits may be included in the high-speed multiplexer). In Figure 13, the flip-flop is D flip-flop as an example for illustration, of course, other flip-flops can also be used for synchronization, and Figure 13 only includes two frequency dividers in the two synthesis circuits, in practice, The synchronized signal output by the flip-flop can drive the frequency divider in each synthesis circuit in a multiplexer, therefore, the flip-flop requires a relatively large driving capability and the volume of the flip-flop is relatively large. In Figure 13, two buffers are also included. The clock signal CLK_f received by the synthesis circuit where the frequency divider is located is buffered by one buffer, and the set signal SET sent to the high-speed multiplexer is buffered by another buffer. Buffer buffers. In FIG. 13, DIV represents a frequency divider by two, DFF represents a D flip-flop, and a triangle icon represents a buffer.

When only the first setting circuit is included in the frequency divider by two, the connection relationship between the frequency divider DIV and the flip-flop DFF is shown in Figure 14 (in Figure 14 only the high-speed multiplexer contains two synthesizing circuit as an example, of course, more than two synthesis circuits can be included in a high-speed multiplexer). Figure 14 also includes two buffers, the clock signal CLK_f received by the synthesis circuit where the frequency divider is located is buffered by one buffer, and the set signal SET sent to the high-speed multiplexer is buffered by another buffer buffer. For the meaning of the icons in Fig. 14, please refer to the description of Fig. 13 .

The high-speed multiplexer provided by the embodiment of the present invention further includes at least one buffer, and the at least one buffer is distributed in a clock tree, and is used to receive the clock signal sent to the high-speed multiplexer, and provide Clock signals are provided for each synthesizing circuit in the high-speed multiplexer;

Wherein, the output terminals of the buffers that output the clock signals for the respective synthesizing circuits in the high-speed multiplexer are directly connected; the clock signals provided for each synthesizing circuit are input to the first one of the synthesizing circuits A frequency divider by two, the output of the first frequency divider by two provides a clock signal for the last stage of the 2:1 multiplexer in the synthesis circuit.

Because the output ends of the buffers that output the clock signals for each synthesizing circuit in the described high-speed multiplexer are directly connected, therefore, the jitters of the clock signals received by different synthesizing circuits in the high-speed multiplexer are consistent of.

Optionally, for each synthesizing circuit in the high-speed multiplexer provided in the embodiment of the present invention, the clock signal received by each synthesizing circuit is the clock signal sent to the high-speed multiplexer through It is obtained after being buffered by the same number of buffers in the at least one buffer, so that the time delays of the clock signals received by the synthesis circuits in the high-speed multiplexer will be relatively consistent.

Optionally, the transmission paths of the clock signals output by the buffers that output the clock signals to the multiple synthesizing circuits in the high-speed multiplexer provided by the embodiment of the present invention adopt a clock tree distribution, therefore, in the high-speed multiplexer The delays of the clock signals received by different synthesizing circuits are more consistent.

When the clock tree provided by the embodiment of the present invention has one level and only one buffer is included in the clock tree, the structure of the clock tree is shown in FIG. 15 . The clock tree shown in FIG. 15 includes only one buffer, and the buffer must be able to drive each synthesis circuit in the high-speed multiplexer. Therefore, the driving capability of the buffer must be strong enough.

When the clock tree provided by the embodiment of the present invention is divided into three levels, and the clock tree includes multiple buffers, the structure of the clock tree is shown in FIG. 16 . A plurality of buffers in the third stage in FIG. 16 jointly drives each synthesis circuit in the high-speed multiplexer, which reduces the requirement on the driving capability of each buffer.

The buffers in the clock tree provided by the embodiment of the present invention are distributed in a clock tree, and the clock tree receives the clock signal sent to the high-speed multiplexer and provides Provides a clock signal. Since the output terminals of the buffers that output clock signals for the various synthesizing circuits in the high-speed multiplexer are directly connected, the jitters of the clock signals received by different synthesizing circuits in the high-speed multiplexer are consistent. Because the clock signals received by each synthesis circuit in the high-speed multiplexer are all the clock signals sent to the high-speed multiplexer pass through the same number of buffers in the at least one buffer The buffered clock signal, and the transmission path of the clock signal output from the buffer that outputs the clock signal to multiple synthesizing circuits in the high-speed multiplexer adopts a clock tree distribution, so each synthesizing circuit in the high-speed multiplexer The delay of the clock signal received by the circuit is consistent.

Those skilled in the art can understand that the drawing is only a schematic diagram of a preferred embodiment, and the modules or processes in the drawing are not necessarily necessary for implementing the present invention.

Those skilled in the art can understand that the modules in the device in the embodiment can be distributed in the device in the embodiment according to the description in the embodiment, or can be located in one or more devices different from the embodiment according to corresponding changes. The modules in the above embodiments can be combined into one module, and can also be further split into multiple sub-modules.

The serial numbers of the above embodiments of the present invention are for description only, and do not represent the advantages and disadvantages of the embodiments.

Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these modifications and variations.

Claims (10)

1. A frequency divider by two, characterized in that it comprises a first controllable switch, a second controllable switch, a third controllable switch, a fourth controllable switch, a first inverter, a second inverter, a third inverter, a fourth inverter, a first latch, a second latch and a first setting circuit; One end of the first controllable switch is respectively connected to the input end of the first inverter and one end of the first latch, and the other end of the first controllable switch is connected to the fourth inverter the output terminal of the first controllable switch, the control terminal of the first controllable switch receives the first control signal; One end of the second controllable switch is respectively connected to the input end of the second inverter and the other end of the first latch, and the other end of the second controllable switch is connected to the third inverter the output terminal of the switch, and the control terminal of the second controllable switch receives the first control signal; One end of the third controllable switch is respectively connected to the output end of the first inverter and the first output end of the frequency division by two, and the other end of the third controllable switch is respectively connected to the second lock One end of the register and the input end of the third inverter, and the control end of the third controllable switch receives the second control signal; One end of the fourth controllable switch is respectively connected to the output end of the second inverter and the second output end of the frequency division by two, and the other end of the fourth controllable switch is respectively connected to the second lock The other end of the register and the input end of the fourth inverter, the control end of the fourth controllable switch receives the second control signal; The first setting circuit is used to load the first level signal to the input terminal of the first inverter when the setting signal is valid, so that the first output terminal is at the second level; The input end of the inverter is loaded with a second level signal, so that the second output end is at the first level; and when the set signal is invalid, stop supplying the input end of the first inverter and the first level The input terminals of the two inverters are loaded with signals; The first control signal is complementary to the second control signal, and after the setting signal changes from valid to invalid, the first control signal is a clock signal, and the second control signal is a clock blocking signal; Both the first controllable switch and the second controllable switch are used to close when the first control signal is a first level signal, and to close when the first control signal is a second level signal open; the third controllable switch and the fourth controllable switch are both used to close when the second control signal is a first level signal, and to close when the second control signal is a second level signal Disconnect when the signal is flat; The first latch is configured to latch the signal at the input end of the first inverter, and latch the signal at the input end of the second inverter; The second latch is configured to latch the signal at the input terminal of the third inverter and latch the signal at the input terminal of the fourth inverter after the setting signal changes from valid to invalid. 2. two frequency dividers as claimed in claim 1, is characterized in that, described two frequency dividers also comprise the second setting circuit; The second setting circuit is configured to load the first level signal to the input terminal of the third inverter when the setting signal is valid, and load the second level signal to the input terminal of the fourth inverter. level signal; and when the set signal is invalid, stop loading signals to the input terminal of the third inverter and the input terminal of the fourth inverter; Wherein, the driving capability of the part of the second setting circuit that loads the signal to the input terminal of the third inverter is greater than the driving capability of the first inverter, and the driving capability of the part of the second setting circuit that loads the signal to the input terminal of the third inverter The drive capability of the portion of the input terminal of the fourth inverter loaded with a signal is greater than the drive capability of the second inverter. 3. The frequency divider according to claim 1, wherein when the setting signal is valid, the first control signal is set to a second level signal, and the second control signal is set to is the first level signal. 4. A high-speed multiplexer, characterized in that it comprises at least one synthesizing circuit, wherein one synthesizing circuit comprises k 2:1 multiplexers and n as described in any one of claims 1 to 3 A two frequency divider, the one synthesizing circuit is used for synthesizing a group of 2 ⁿ -way low-speed signals into a group of one-way high-speed signal circuit, k and n are both positive integers,

The transmission speed of the one high-speed signal is the sum of the 2 ⁿ low-speed signals; In a synthesis circuit, the same stage 2:1 multiplexer receives the same frequency clock signal, the first stage 2:1 multiplexer receives said low speed signal, and the last stage 2:1 multiplexes The signal output by the device is the high-speed signal, and the signal received by each stage of 2:1 multiplexer except the first stage of 2:1 multiplexer is the signal received by the previous stage of 2:1 multiplexer The signal output by the multiplexer; the clock signal received by the 2:1 multiplexers at all levels except the last stage 2:1 multiplexer is received by the latter stage of the 2:1 multiplexer The clock signal is output after the clock signal is divided by a frequency divider by two; Each 2:1 multiplexer is used to synthesize two received signals with a frequency of f into one with a frequency of 2 under the control of a clock signal with a frequency f output by a frequency divider. *f signal. 5. The high-speed multiplexer as claimed in claim 4, wherein a 2:1 multiplexer includes a first flip-flop, a second flip-flop, a third flip-flop and a 2:1 selector ; The input end of the first flip-flop receives the first data signal with frequency f, the clock signal end of the first flip-flop receives the clock signal with frequency f, and the output end of the first flip-flop is connected to the 2 : 1 first input terminal of the selector; The input end of the second flip-flop receives the second data signal with frequency f, the clock signal end of the second flip-flop receives the clock signal with frequency f, and the output end of the second flip-flop is connected to the first The input terminals of three flip-flops; the clock signal end of the third flip-flop receives a clock signal complementary to the clock signal with frequency f, and the output end of the third flip-flop is connected to the second of the 2:1 selector input terminal; the control terminal of the 2:1 selector receives a clock signal complementary to the clock signal with frequency f; The first flip-flop is used to synchronize the first data signal with frequency f with the clock signal with frequency f; The second flip-flop is used to synchronize the second data signal with frequency f with the clock signal with frequency f; The third flip-flop is used to shift the phase of the second data signal synchronized with the clock signal of frequency f by π; The 2:1 selector is configured to connect the first input terminal to the output terminal of the 2:1 selector when the clock signal complementary to the clock signal with frequency f is a first level signal ; and when the clock signal complementary to the clock signal with frequency f is a second level signal, connecting the second input end to the output end of the 2:1 selector. 6. The high-speed multiplexer as claimed in claim 5, wherein, when the 2:1 multiplexer receives the difference between half of the period of the clock signal and the total time delay, less than the received The setup time of the flip-flop in the 2:1 multiplexer when receiving the 2:1 multiplex of the signal output by the 2:1 multiplexer The device also includes a delay device; The delayer is used to delay the clock signal received by the 2 frequency divider that provides the clock signal to the 2:1 multiplexer for a preset period of time, and send the clock signal delayed by the preset period of time to the receiver The 2:1 multiplexer outputs the signal to the 2:1 multiplexer. 7. The high-speed multiplexer according to any one of claims 4 to 6, wherein when the second frequency divider includes a second setting circuit, the setting received by the two frequency divider The bit signal is obtained after the set signal received by the high-speed multiplexer is synchronized with the clock signal received by a synthesizer circuit where the frequency divider is located. 8. The high-speed multiplexer according to any one of claims 4 to 7, wherein the high-speed multiplexer comprises at least one buffer, and the at least one buffer adopts a clock tree distribution, using For receiving the clock signal sent to the high-speed multiplexer, and providing a clock signal for each synthesis circuit in the high-speed multiplexer; Wherein, the output terminals of the buffers that output the clock signals for the respective synthesizing circuits in the high-speed multiplexer are directly connected; the clock signals provided for each synthesizing circuit are input to the first one of the synthesizing circuits A frequency divider by two, the output of the first frequency divider by two provides a clock signal for the last stage of the 2:1 multiplexer in the synthesis circuit. 9. The high-speed multiplexer as claimed in claim 8, wherein the clock signals received by each synthesizing circuit in the high-speed multiplexer are sent to the high-speed multiplexer The clock signal of the multiplexer is obtained after being buffered by the same number of buffers in the at least one buffer. 10. The high-speed multiplexer according to claim 9, wherein the transmission path of the clock signal output from the buffer outputting the clock signal to a plurality of synthesizing circuits adopts a clock tree distribution.

Images