CN103872985B - High-voltage sine wave driving signal generating device - Google Patents

Abstract

The present invention is a high-voltage sine wave driving signal generating device, including a general computer, a single-chip microcomputer, a field programmable logic gate array, a digital frequency synthesizer, a transformer, a first low-pass filter, a bias voltage generator, a signal amplification module, Bias power supply, high-voltage power supply, high-voltage amplification module, clamping circuit, and second low-pass filter; the amplitude-controllable sine wave signal output by the digital frequency synthesizer is amplified by cascading two-stage signal amplification modules and high-voltage amplification modules The high-voltage sine wave signal is obtained by clamping through the bottom clamping circuit, and the noise is removed through the first low-pass filter after the direct digital frequency synthesizer and the second low-pass filter after the signal clamping. The invention simplifies the generation method of the sine wave, makes the frame frequency of the electronic multiplication charge-coupled device CCD60 reach more than 1000 Hz, doubles the frequency of similar foreign cameras, and is used for the high-frequency and high-voltage gain drive of the charge-coupled device to generate electronic gain.

Description

A high-voltage sine wave drive signal generator

technical field

The invention belongs to the field of low-light imaging, and relates to a high-voltage sine wave drive signal generating device, which is mainly used for driving a unique electronic gain register of an EMCCD to generate electronic gain.

Background technique

Electron Multiplying Charge Coupled Device (EMCCD) integrates hundreds of electron multiplication registers on the silicon chip, which can amplify signal electrons by more than 1000 times in the electronic domain and obtain very high sensitivity, especially suitable for Imaging under low light conditions. However, the charge-coupled device requires a unique sine wave or square wave driving signal with a low voltage of 4.0V and a high voltage of 20V-50V to generate electronic gain. This requirement is very difficult in the actual implementation of the circuit. In addition, the readout amplifiers of some electron multiplication CCDs can reach a pixel clock frequency above 18MHz after special design. For example, the CCD60 of E2V Company with an area array size of 128×128 can reach 1000 frames per second at a pixel clock frequency of 18MHz. theoretical frame rate. This further requires the driving frequency of the high-voltage gain driving signal to reach 20 MHz, which is very strict on the bandwidth of the circuit generating the high-voltage driving signal.

At present, finished cameras with charge-coupled devices can be purchased in foreign markets, such as Andor's DV860 camera, whose readout noise can reach 65e-, and the highest gain multiple can reach 1000 times, but its design is conservative, and the highest frame rate can only reach 500 frames per second is far from the theoretical maximum frame rate of 1000 frames per second of CCD60, and has a very large room for improvement. To achieve the maximum theoretical frame rate, two problems must be overcome: high-voltage gain drive technology up to 20MHz and low-noise processing technology under high-speed transfer of charge packets.

The charge-coupled device camera peripheral drive technology is currently a research hotspot for experts in the field of low-light imaging at home and abroad, but they are all concentrated in the low-frequency research field with a pixel clock of about 10MHz, which is far from satisfying the high frame frequency charge-coupled device with a pixel clock of more than 20MHz. Camera driver requirements. It adopts the technology of synthesizing digital frequency into discrete digital sine wave signal in FPGA and then uses DA to convert it into analog sine wave signal, which is more complicated to realize. At the same time, due to the problem of insufficient bandwidth of key circuit modules, the driving frequency of 20MHz cannot be achieved. . Therefore, how to realize the high-voltage gain drive signal of the charge-coupled device with a drive frequency of more than 20MHz and a voltage amplitude of more than 45V is the first problem to be solved in the development of a high frame frequency charge-coupled device camera.

Contents of the invention

(1) Solved technical problems

In order to solve the problem that the existing charge-coupled device high-voltage gain sine wave drive device cannot reach the driving frequency of 20MHz and the charge-coupled device 60 cannot reach the highest frame frequency of 1000Hz, a charge-coupled device with a signal frequency of 20MHz and a signal amplitude of 45V was invented. Coupling device sine wave drive.

(2) Technical solution

A high-voltage sine wave drive signal generating device provided by the present invention mainly includes a general-purpose computer, a single-chip microcomputer, a field programmable logic gate array, a digital frequency synthesizer, a transformer, a first low-pass filter, a bias voltage generator, and a signal amplifier Module, bias power supply, high-voltage power supply, high-voltage amplification module, clamping circuit, and second low-pass filter, wherein: the single-chip microcomputer is connected with a general-purpose computer, and the single-chip microcomputer generates and outputs the internal parameters of the digital frequency synthesizer according to the control command word sent by the general-purpose computer The configuration parameters of the register; the digital frequency synthesizer is connected with the field programmable logic gate array and the single-chip microcomputer, and receives the synchronous clock provided by the field programmable logic gate array as the main clock signal, and at the same time receives the configuration of the internal parameter register of the digital frequency synthesizer output by the single-chip microcomputer Parameters, output differential sine wave signals according to configuration parameter information; the transformer is connected to a digital frequency synthesizer for converting differential sine wave signals into single-ended sine wave signals; the first low-pass filter is connected to the transformer for filtering out digital The frequency synthesizer outputs the stepped noise in the sine wave signal, and outputs a smooth sine wave signal; the signal amplification module is connected with the low-pass filter and the bias voltage generator, and receives the bias voltage output by the bias voltage generator and the first The smooth sine wave signal output by the low-pass filter generates and outputs a first-level sine wave signal with an AC component amplified 5 times and with a certain amount of DC bias; the high-voltage amplifier module is connected with the signal amplifier module and the high-voltage power supply, and the high-voltage amplifier module Receive the voltage output by the high-voltage power supply as the power supply, and the high-voltage amplification module amplifies the first-level sine wave signal output by the signal amplification module by 9 times and outputs the second-level sine wave signal; the clamping circuit is connected with the high-voltage amplification module and the bias power supply, and the bias The power supply provides the bias voltage for the clamping circuit, and the clamping circuit clamps the bottom of the secondary sine wave signal output by the high-voltage amplifying module to a voltage of 4.0V, and outputs a secondary sine wave signal with a 4.0V DC bias; The second low-pass filter is connected with the clamping circuit to filter out the noise of the secondary sine wave signal with a 4.0V DC bias output by the clamping circuit, and obtain and provide a high-voltage sine wave with a maximum frequency of 20MHz for the electronic multiplication charge-coupled device single-frequency signal.

(3) Beneficial effects

The present invention increases the frequency of the high-voltage sine wave drive signal of the charge coupler from the original 10MHz to 20MHz, which is 100% higher than the drive frequency of the existing device, and can increase the shooting frame frequency of the 60-type charge coupler from 500 frames per second The highest theoretical frame rate is 1000 frames per second, which is doubled compared with similar foreign cameras, and greatly simplifies the generation method of sine waves, which can meet the driving requirements of all E2V company's EMCCD products for high-voltage gain signals, and has a very good universal sex.

Description of drawings

Fig. 1 is the embodiment block diagram of the high-voltage sine wave drive signal generating device of the electron multiplying charge-coupled device up to 20MHz in the present invention;

Fig. 2 is a third-order passive low-pass filter in an embodiment of the present invention;

Fig. 3 is an embodiment in which the signal amplification module is a first-stage amplification circuit in the present invention;

Fig. 4 is the clamping circuit embodiment of the diode bottom clamping circuit in the present invention;

Fig. 5 is the embodiment that low-pass filter circuit is RC low-pass filter circuit among the present invention;

Fig. 6 is a sine wave driving signal generated by the embodiment of the device of the present invention.

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

The present invention is directed to the embodiments of charge-coupled devices (CCD), and the charge-coupled devices are planar array charge-coupled devices. Those skilled in the art can realize the high voltage related to driving any planar charge-coupled device through the following embodiments of the present invention. The sine wave drive signal generating device, the following only takes the high-voltage sine wave drive signal generating device driving the electron multiplying charge-coupled device in the CCD camera as an example to introduce the embodiment:

Figure 1 shows a high-voltage sine wave drive signal generating device for an electronic multiplier charge-coupled device up to 20MHz, including a general-purpose computer PC, a single-chip microcomputer MCU, a field programmable logic gate array FPGA, a digital frequency synthesizer DDS, a transformer, and a first low-pass filter, bias voltage generator, signal amplification module, bias power supply, high-voltage power supply, high-voltage amplification module, clamp circuit, second low-pass filter; the first low-pass filter uses a three-stage passive low-pass filter. The clamping circuit uses a diode clamping circuit. The digital frequency synthesizer uses a monolithic integrated direct digital frequency synthesizer. The second low-pass filter uses an RC low-pass filter circuit. The high-voltage power supply is a 50V high-voltage power supply. Among them: the single-chip microcomputer is connected with the general-purpose computer, and the single-chip microcomputer generates and outputs the configuration parameters of the internal parameter register of the digital frequency synthesizer according to the control command word sent by the general-purpose computer; the digital frequency synthesizer is connected with the field programmable logic gate array and the single-chip microcomputer, and receives field programmable The synchronous clock provided by the logic gate array is used as the main clock signal, and at the same time, it receives the configuration parameters of the internal parameter register of the digital frequency synthesizer output by the microcontroller, and outputs a differential sine wave signal according to the configuration parameter information; the transformer is connected with the digital frequency synthesizer to convert the differential The sine wave signal is converted into a single-ended sine wave signal; the first low-pass filter is connected with the transformer, and is used to filter the stepped noise in the output sine wave signal of the digital frequency synthesizer, and output a smooth sine wave signal; the signal amplification module is connected with the The low-pass filter and the bias voltage generator are connected to receive the bias voltage output by the bias voltage generator and the smooth sine wave signal output by the first low-pass filter, generate and output an AC component that is amplified by 5 times and has a certain The first-level sine wave signal of the DC bias; the high-voltage amplification module is connected with the signal amplification module and the high-voltage power supply, and the high-voltage amplification module receives the voltage output by the high-voltage power supply as the power supply, and the high-voltage amplification module uses the first-level sine wave signal output by the signal amplification module Amplify 9 times and output the secondary sine wave signal; the clamping circuit is connected with the high-voltage amplifying module and the bias power supply, the bias power supply provides the bias voltage for the clamping circuit, and the clamping circuit outputs the secondary sine wave signal output by the high-voltage amplifying module The bottom of the clamp is clamped to a 4.0V voltage, and outputs a secondary sine wave signal with a 4.0V DC bias; the second low-pass filter is connected to the clamping circuit to filter out the output of the clamping circuit with a 4.0V DC The noise of the biased secondary sine wave signal is obtained and a high-voltage sine wave single-frequency signal with a maximum frequency of 20MHz is obtained and provided for the electron multiplying charge-coupled device.

The general-purpose computer sends command words to control the internal program of the single-chip microcomputer, realizes the control of the internal register of the digital frequency synthesizer through the single-chip microcomputer, and outputs a sine wave signal with controllable phase, amplitude and frequency. The digital frequency synthesizer outputs a differential sine wave signal with an amplitude of 1V, and the field programmable logic gate array provides the synchronous clock of the digital frequency synthesizer to realize the internal drive signal and high voltage sine wave drive of the field programmable logic gate array Signal synchronization, used to simplify the generation of sine wave signals. The cut-off frequency of the first low-pass filter is a third-order passive low-pass filter of 40 MHz, which is used to filter out the step-like noise in the sine wave signal output by the digital frequency synthesizer and smooth the sine wave signal. The signal amplification module adopts a 1GHz high-bandwidth, 1350V/μs large slew rate operational amplifier, combined with the bias voltage output by the bias voltage generator, to amplify the sine wave signal output by the first low-pass filter after denoising by 5 times To 5V peak-to-peak value, and with a 1.5V DC signal, it provides a necessary DC voltage for the high-voltage amplifier module. The high-voltage amplification module adopts 200MHz high bandwidth,

The high-voltage amplifier with a large slew rate of 15000V/μs uses a 50V high-voltage power supply to power the high-voltage amplifier, and amplifies the 5V peak-to-peak sine wave signal output by the signal amplification module by 9 times to a 45V peak-to-peak sine wave signal. In order to meet the special requirements of the charge-coupled device's high-voltage gain drive signal with a low voltage of 4.0V, a clamp circuit is used to clamp the bottom of the high-voltage sine wave signal output by the high-voltage amplifier to 4.0V DC voltage, so as to realize the bottom voltage required by the charge-coupled device. The level is 4.0V, and the highest voltage is 49V, which is less than the basic requirement that the maximum safe voltage is not more than 50V. In order to ensure that the general-purpose computer sends command words to control the internal program of the single-chip microcomputer, the internal register of the digital frequency synthesizer is controlled through the single-chip microcomputer, and the sine wave signal with controllable phase, amplitude and frequency is output. In order to ensure that the maximum frequency of the high-voltage sine wave signal output by the device of the present invention can reach 20MHz, the following safeguard measures are mainly taken: the digital frequency synthesizer can output a sine wave signal frequency above 20MHz, and the internal clock lock of the digital frequency synthesizer is set by the single-chip microcomputer. The phase loop register increases its internal operating frequency to

400MHz, which enables the digital-to-analog converter inside the digital frequency synthesizer to achieve at least 20 equal divisions for each cycle of the output sine wave signal, which is used to effectively reduce the step noise of the sine wave output signal; the bandwidth of the transformer is selected to be 300MHz, which is greater than the It is necessary to output a sine wave signal frequency above 20MHz to ensure that the signal will not be lost when passing through the transformer; the cut-off frequency of the low-pass filter is 40MHz, which is greater than the maximum signal frequency of 20MHz, to eliminate high-frequency noise to the greatest extent, while retaining the sine wave of 20MHz Signal: The bandwidth of the transport operational amplifier used in the signal amplification module circuit is 1GHz, and the effective bandwidth after 5 times amplification is 200MHz, which is greater than the signal bandwidth of 20MHz. At the same time, the slew rate is 1350V/μs, which is greater than the minimum slew rate of the internal operational amplifier of the signal amplification module. The required 628V/μs; the bandwidth of the high-voltage amplifier module is 200MHz, and the bandwidth after 9 times amplification is 22MHz, which is greater than the maximum signal frequency of 20MHz. At the same time, the slew rate is 15000V/μs, which is higher than the minimum slew rate requirement of this stage amplifier 5652V/μs .

When the single-chip microcomputer is powered on in the system, first complete the corresponding setting of the internal phase register, amplitude register, frequency register and clock phase-locked loop register of the direct digital frequency synthesizer. After completing the setting, wait for the 8-byte control command of the general computer software. The amplitude of the direct digital synthesizer output signal needs to be adjusted. Initialize and set the frequency of the signal output by the digital frequency synthesizer to the desired value, such as 18MHz, the phase is set to 0, the output frequency of the clock phase-locked loop is 400MHz, and the electronic multiplier charge-coupled device drive signal inside the field programmable logic gate array FPGA To maintain synchronization, the signal amplitude is set to 0.36V peak-to-peak value, and the corresponding output signal amplitude of the entire device is 0.36×45=16.2V, plus the subsequent 4V DC level bottom clamp, which is about the lowest amplitude of the high-voltage gain voltage of the electronic multiplication charge-coupled device Value 20V.

In order to ensure that the high-voltage sine wave signal output by the device maintains a strict timing phase relationship with the electronic multiplication charge-coupled device driving timing signal generated by the field programmable logic gate array FPGA, one output channel from the field programmable logic gate array FPGA is connected to the internal drive of the FPGA. The single-ended clock with the same source is input to the digital frequency synthesizer DDS as the main clock, and after the register of the digital frequency synthesizer DDS is set, a valid signal is sent by the microcontroller to activate the electronic multiplication charge inside the field programmable logic gate array FPGA The coupling device drives the timing module and the internal register of the digital frequency synthesizer DDS, so that the two modules start working at the same time, so as to control the electronic multiplier charge-coupled device driving signal and digital frequency synthesis generated inside the field programmable logic gate array FPGA The high-voltage drive signal generated by the DDS maintains a fixed timing relationship every time it is powered on. By adjusting the phase register inside the digital frequency synthesizer DDS, the first level drive gate R1 drive signal of the electron multiplier charge-coupled device can be connected to the high-voltage The sine wave drive signal maintains the required timing relationship.

The sine wave signal output by the digital frequency synthesizer DDS uses a digital-to-analog converter (DAC) to convert the internal discrete sine wave sequence value into an analog signal, so step-shaped high-frequency noise will inevitably appear, and it is necessary to add a filter in the follow-up In addition, only the useful sine wave signal is retained. Considering factors such as single-frequency characteristics of effective signals, system power consumption, and printed circuit board PCB area, the first low-pass filter as shown in Figure 2 adopts a third-order passive low-pass filter with a narrow transition band, and the cutoff frequency Set to 40MHz, the third-order passive low-pass filter implementation includes: capacitors C32, C34, C35, C36, C42, C43, C44, C46, C47, C48, and C51, and inductors L1, L2, L3, and L4. Among them: capacitors C32, C34, C35, and C36 are connected in parallel, capacitors C46, C47, C48, and C51 are connected in parallel, the input end of capacitor C32 is connected to the output end of the transformer, the input end of capacitor C34 is connected to the output end of inductor L1, and the input end of capacitor C35 is The input terminal is connected to the output terminal of the inductor L2, the input terminal of the capacitor C36 is connected to the output terminal of the inductor L3, the output terminals of the capacitors C32, C34, C35, and C36 are connected to the ground, and the input terminal IN of the inductor L1 is connected to the output terminal of the transformer , the input end of the inductor L2 is connected to the output end of the inductor L1, the input end of the inductor L3 is connected to the output end of the inductor L2, the input end of the inductor L4 is connected to the output end of the inductor L3, and the input end of the capacitor C42 is connected to the output of the transformer The input end of capacitor C43 is connected to the output end of capacitor C42, the input end of capacitor C44 is connected to the output end of capacitor C43, the input end of capacitor C46 is connected to the output end of the transformer, and the input end of capacitor C47 is connected to the output end of capacitor C42. For the output terminal, the input terminal of the capacitor C51 is connected to the output terminal of the capacitor C43, the input terminal of the capacitor C48 is connected to the output terminal of the capacitor C44, and the output terminals of the capacitors C46, C47, C51 and C48 are connected to the ground. The single-ended sine wave signal output by the transformer enters the first low-pass filter for low-pass filtering, all the noise above the cut-off frequency 40MHz is filtered out, and only the effective sine wave signal is retained and output by the output terminal OUT of the inductor L4 to the signal amplifier module.

As shown in Figure 3, the signal amplification module is an embodiment of the first stage amplification circuit, including: DC power supply V1, V2, V3, potentiometer R1, amplifier U2, input resistors R2, R3, R4, feedback resistor R5, DC power supply V2 The filter capacitors C1, C2 of the DC power supply V3, the filter capacitors C3, C4. The potentiometer R1 is a three-terminal voltage dividing resistor, the input terminal of the potentiometer R1 is connected to the DC power supply V1, one output terminal of the potentiometer R1 is connected to the ground, and the other output terminal of the potentiometer R1 is connected to the input resistors R2 and R3 The input terminal of the input resistor R3 is connected to the ground, the input terminal INPUT of the input resistor R4 is connected to the output terminal of the first filter, the non-inverting input terminal of the amplifier U2 is connected to the output terminal of the input resistor R2, and the inverting input terminal connected to the output terminal of the input resistor R4, the input terminal of the feedback resistor R5 is connected to the output terminal OUT of the amplifier U2, the output terminal of the feedback resistor R5 is connected to the inverting input terminal of the amplifier U2, and the output terminal of the DC power supply V2 is connected to the amplifier U2 The positive power supply input terminal of the DC power supply V2 is connected to the ground, the filter capacitors C1 and C2 are connected in parallel, the input terminals of the filter capacitors C1 and C2 are connected to the output terminal of the DC power supply V2, and the output terminals of the filter capacitors C1 and C2 are connected to to the ground, the output terminal of the DC power supply V3 is connected to the negative power supply input terminal of the amplifier U2, the ground terminal of the DC power supply V3 is connected to the ground, the filter capacitors C3 and C4 are connected in parallel, and the input terminals of the filter capacitors C3 and C4 are connected to the DC power supply V3 The output terminals, the output terminals of the filter capacitors C3 and C4 are connected to the ground. The signal amplifying module is a first-stage amplifying circuit, which mainly amplifies the sine wave signal output by the filter to within the effective output range of the high-voltage amplifying module of the second-stage amplifying circuit. The amplification factor is 5 times, the corresponding minimum signal gain-bandwidth product requirement is 5×20MHz=100MHz, the minimum slew rate is 2×PI×signal frequency×signal amplitude=2×3.14×20MHz×5V=628V/μs, where PI is pi = 3.1415927, and requires a low-noise operational amplifier. The selected operational amplifier U2 has a typical index of 1GHz bandwidth, 1350V/μs slew rate, and 3nV/Hz ^1/2 noise voltage. At the same time, in order to achieve the purpose of adjusting the DC level of the output signal of the first-stage amplifying circuit, a potentiometer is used to divide a DC voltage, which can provide an adjustable DC bias voltage for the first-stage amplifying circuit.

The high-voltage amplifier module is the second-stage amplifier circuit, which is responsible for amplifying the 5V peak-to-peak voltage output by the previous stage by 9 times to a 45V peak-to-peak voltage. The minimum signal gain-bandwidth product required by the second-stage amplifier circuit is 20×9=180MHz, and the minimum slew rate is 2×PI×signal frequency×signal amplitude=2×3.14×20MHz×45V=5652V/μs, where PI is PI = 3.1415927, the selected high-voltage amplifier is a variant amplifier, its gain-bandwidth product is 200MHz, and the slew rate is 15000V/μs, which can meet the application requirements. In addition, the amplifier is powered by a single power supply, and the system voltage is converted to 52V by a DC-DC conversion module. Before entering the amplifier, it is stabilized by a high-voltage linear regulator LDO to reach 50V output, which meets the application requirements of the amplifier. .

The 45V peak-to-peak high-voltage sine wave signal output by the high-voltage amplifying circuit has a certain DC level, which cannot meet the application requirements of the high-voltage gain drive signal of the electronic multiplier charge-coupled device being 4.0V lower and the high voltage up to 50V. A diode clamping circuit is added to the terminal, the input terminal INPUT of the clamping circuit clamps the bottom of the output signal of the high-voltage amplifier circuit to a DC voltage of 4.0V, and the output terminal OUT of the clamping circuit outputs a DC bias of 4.0V The secondary sine wave signal is used to meet the high-voltage gain drive requirements of electron multiplied charge-coupled devices. The specific implementation method of the clamping circuit includes, as shown in FIG. 4 , a DC blocking capacitor C5 , a resistor R6 , a diode D1 , filter capacitors C6 and C7 , and a power supply V4 . Among them, the input terminal INPUT of the DC blocking capacitor C5 is connected to the output terminal of the high-voltage amplifying module, the resistor R6 is connected in parallel with the diode D1, the input terminal of the resistor R6 and the diode D1 is connected to the output terminal of the power supply V4, and the filter capacitor C6 is connected in parallel with the filter capacitor C7 , the input terminals of the filter capacitor C6 and the filter capacitor C7 are connected to the output terminal of the power supply V4, the output terminals of the filter capacitor C6 and the filter capacitor C7 are connected to the ground, and the output terminal OUT of the DC blocking capacitor C5 outputs a 4.0V DC bias Secondary sine wave signal.

In order to filter out the interference noise introduced during the signal generation process, a first-stage RC low-pass filter is performed after the high-voltage sine wave signal is clamped, considering the power consumption of the high-voltage amplifier, heat dissipation, and the ability of the electronic multiplier charge-coupled device itself to drive the driving signal According to the demand, set the cut-off frequency of the RC low-pass filter to 5 times the driving frequency of the charge-coupled device 100MHz. The specific implementation method is shown in Figure 5, including the resistor R7 and the capacitor C8. The output terminal of the bit circuit, the input terminal of the capacitor C8 is connected to the output terminal OUT of the resistor R7, the output terminal of the capacitor C8 is connected to the ground, and the electronic gain is generated from the output terminal OUT of the resistor R7 to the electronic gain control gate of the electronic multiplier charge-coupled device .

FIG. 6 The device generates a sine wave drive signal with a frequency of 20 MHz and an amplitude of 45 V, wherein the square wave is the drive signal for the first horizontal drive gate R1 of the electron multiplying charge-coupled device.

The above is only a specific implementation mode in the present invention, but the scope of protection of the present invention is not limited thereto. Anyone familiar with the technology can understand the conceivable transformation or replacement within the technical scope disclosed in the present invention. All should be covered within the scope of the present invention, therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (8)

1. a kind of high pressure sine wave drive signal generating means it is characterised in that：Mainly include all-purpose computer, single-chip microcomputer, show Field programmable logic gate array, digital frequency synthesizer, transformer, the first low pass filter, bias voltage generator, signal are put Big module, bias supply, high voltage power supply, high pressure amplifying, clamp circuit, the second low pass filter, wherein：

Single-chip microcomputer is connected with all-purpose computer, and single-chip microcomputer generates according to the control command word that all-purpose computer sends and exports numeral The configuration parameter of frequency synthesizer inner parameter register；

Digital frequency synthesizer is connected with field programmable gate array, single-chip microcomputer, receives field programmable gate array The synchronised clock providing, as master clock signal, receives the digital frequency synthesizer inner parameter register of single-chip microcomputer output simultaneously Configuration parameter, according to configuration parameter information output differential sine wave signal；

Transformer is connected with digital frequency synthesizer, for differential sine wave signal is converted into single-ended sine wave signal；

First low pass filter is connected with transformer, stepped in digital frequency synthesizer sine wave output signal for filtering Noise, the sine wave signal of output smoothing；

Signal amplification module is connected with the first low pass filter, bias voltage generator, receives bias voltage generator output Bias voltage and the smooth sine wave signal of the first low pass filter output, generate and export a road AC compounent and amplify 5 Times and there is the one-level sine wave signal of certain direct current biasing amount；

High pressure amplifying is connected with signal amplification module, high voltage power supply, and high pressure amplifying receives the electricity of high voltage power supply output As power supply, the one-level sine wave signal that signal amplification module exports is amplified 9 times and exports two pressure by high pressure amplifying Level sine wave signal；

Clamp circuit is connected with high pressure amplifying, bias supply, and bias supply provides bias voltage, clamper electricity for clamp circuit The bottom engagement of two grades of sine wave signals that high pressure amplifying is exported by road is on 4.0V voltage, and exports with 4.0V direct current Two grades of sine wave signals of biasing；

Second low pass filter is connected with clamp circuit, filters with 4.0V direct current biasing two grades of sines of clamp circuit output The noise of ripple signal, obtains and provides for electron multiplying charge coupled apparatus the high pressure sine wave single-frequency letter of peak frequency 20MHz Number.

2. high pressure sine wave drive signal generating means according to claim 1 it is characterised in that：All-purpose computer sends Command word control single chip computer internal processes, by the control to digital frequency synthesizer internal register for the chip microcontroller, export The controllable sine wave signal of phase place, amplitude, frequency.

3. high pressure sine wave drive signal generating means according to claim 1 it is characterised in that：Described numerical frequency is closed Output amplitude of growing up to be a useful person size is the differential sine wave signal of 1V, and provides Digital Frequency Synthesize by field programmable gate array The synchronised clock of device, the drive signal realized within field programmable gate array is synchronous with high pressure sine wave drive signal, For simplifying the generation process of sine wave signal.

4. high pressure sine wave drive signal generating means according to claim 1 it is characterised in that：Described first low pass filtered The cut-off frequency of ripple device is the three rank passive low ventilating filters of 40MHz, is used for filtering digital frequency synthesizer sine wave output letter Stepped noise in number, smooth sinusoidal wave signal.

5. high pressure sine wave drive signal generating means according to claim 1 it is characterised in that：Described signal amplifies mould Block adopts 1GHz high bandwidth, 1350V/ μ s big slew rate operational amplifier, in conjunction with the bias voltage of bias voltage generator output, The sine wave signal of output after the first low pass filter denoising is amplified 5 times and arrives 5V peak-to-peak value, and the direct current signal with 1.5V, There is provided a necessary DC voltage for high pressure amplifying.

6. high pressure sine wave drive signal generating means according to claim 5 it is characterised in that：Described high voltage amplifier mould Block adopts 200MHz high bandwidth, the high-voltage amplifier of the especially big slew rate of 15000V/ μ s, is high voltage amplifier using 50V high voltage power supply Device is powered, and the 5V peak-to-peak value sine wave signal of signal amplification module output is amplified 9 times of sine wave letters being changed into 45V peak-to-peak value Number.

7. high pressure sine wave drive signal generating means according to claim 1 it is characterised in that：For meeting Charged Couple Device high voltage gain drive signal low-voltage is the particular/special requirement of 4.0V, the high pressure being exported high-voltage amplifier using clamp circuit Sine wave signal bottom engagement is on 4.0V DC voltage, thus the bottom level realizing charge-coupled image sensor requirement is 4.0V, Ceiling voltage is 49V.

8. high pressure sine wave drive signal generating means according to claim 1 it is characterised in that：Defeated for ensureing this device The high pressure sine wave signal peak frequency going out can reach 20MHz, mainly takes following safeguard：

Digital frequency synthesizer can export the sine wave signal frequency of more than 20MHz, and arranges numerical frequency conjunction by single-chip microcomputer Internal clock phase-locked loop ring register of growing up to be a useful person improves its internal operating frequencies to 400MHz, can make the internal number of digital frequency synthesizer Each cycle of the sine wave signal to output for the weighted-voltage D/A converter realizes at least 20 deciles, reduces sinewave output letter for effective Number stair-wise noise；

The bandwidth selection of transformer is 300MHz, more than the sine wave signal frequency of required output more than 20MHz, is used for guaranteeing Signal passes through will not incur loss during transformer；

Low pass filter cutoff frequency is 40MHz, more than peak signal frequency 20MHz, eliminates high-frequency noise to greatest extent, and protects Stay the sine wave signal of 20MHz；

The a width of 1GHz of operational amplifier band that signal amplification module circuit adopts, the effective bandwidth after amplifying 5 times is 200MHz, greatly In 20MHz signal bandwidth, slew rate is 1350V/ μ s simultaneously, more than the minimum slew rate of signal amplification module internal arithmetic amplifier The 628V/ μ s requiring；

The a width of 200MHz of high pressure amplifying amplifier band, a width of 22MHz of band after amplifying 9 times is more than peak signal frequency 20MHz, Slew rate is 15000V/ μ s simultaneously, requires 5652V/ μ s more than the minimum slew rate of this operational amplifier.