CN103872121B - HFET based on channel array structure - Google Patents

Abstract

The present invention relates to a kind of HFET based on channel array structure, including hetero-junctions, described hetero-junctions includes first that stacking from top to bottom is arranged, second semiconductor layer, first, second semiconductor interface is formed with two-dimensional electron gas, arrange active on first semiconductor layer, leakage and grid, grid is arranged at source, between drain electrode, and it is provided with channel array in the hetero-junctions below grid, this channel array is made up of a plurality of raceway groove being set up in parallel, the two ends of any of which raceway groove point to source electrode and drain electrode respectively, and cover the grid metal level for constituting grid the most continuously on the upper surface of arbitrary raceway groove and two side.The present invention uses structure based on channel array design, and form gate-all-around structure by grid metal being covered the sidewall on the top of raceway groove and both sides, thus enhance the modulation capability to raceway groove, it is applicable to all semi-conductor electronic devices worked based on two-dimensional electron gas at heterojunction boundary, and the various requirement of actual application can be met simultaneously.

Description

Heterojunction Field Effect Transistor Based on Trench Array Structure

This application is a divisional application with the application number 201110083011.7, the application date is April 2, 2011, and the title is "Heterojunction Field Effect Transistor Based on Tunnel Array Structure".

technical field

The invention relates to a semiconductor electronic device, in particular to a heterojunction field effect transistor based on a channel array structure.

Background technique

A semiconductor heterojunction is composed of two or more different semiconductor materials. Due to the different physical and chemical parameters (such as electron affinity, energy band structure, dielectric constant, lattice constant, etc.) between different semiconductor materials, various physical and chemical properties will be mismatched at the contact interface, so that Heterojunctions have many new properties. The basic structure of a heterojunction field effect transistor consists of a heterojunction composed of a wide bandgap material and a narrow bandgap material. In this heterojunction, the N-type impurity-doped wide bandgap material acts as an electron supply layer to provide a large number of electrons to the undoped narrow bandgap material, or a large number of electrons are generated due to the polarization effect of the strongly polarized material, and these electrons are accumulated in the A two-dimensional electron gas is formed in the triangular potential well formed by the energy difference in the conduction bands of the two materials. Due to the scattering away from the donor ionization center, it exhibits high mobility. A two-dimensional electron gas with high concentration and high mobility is used as a conductive channel, and the electron concentration in the channel is modulated by the gate voltage. A source region and a drain region are arranged on both sides of the gate to form a heterojunction field effect transistor. Due to its very high cut-off frequency and oscillation frequency, high current density, small short-channel effect and good noise performance, heterojunction field effect transistors are used in microwave low-noise amplifiers, high-speed digital integrated circuits, high-speed static random access memories, It has a very wide range of applications in high temperature circuits, power amplifiers and microwave oscillator circuits.

At present, many material systems have been applied to heterojunction field effect transistors, and excellent results have been achieved. For example, GaAs-based heterojunction field effect transistors (HFETs) have been widely used in the fields of high frequency, ultra high frequency and microwave radio frequency. In the millimeter wave band, compared with GaAs, InP has attracted people's attention due to its superior performance. InP has a higher breakdown electric field and electron average velocity, and there is a large conduction band discontinuity at the heterojunction InAlAs/InGaAs interface, a two-dimensional electron gas density, and a high electron mobility in the channel, so InP Base devices are more suitable for high frequency applications. In addition, Si/SiGe-based and GaN-based heterojunction field effect transistors, which have attracted much attention recently, have also attracted people's attention due to their materials and the advantages of forming heterojunctions.

In general, the heterojunction has a very high density of two-dimensional electron gas in the absence of an external bias, and the formed device is a depletion device. However, from an application point of view, enhanced HEMTs have many advantages. For example, in high-frequency PA and LNA applications, enhanced HEMTs can eliminate the use of negative voltage sources, thereby reducing circuit complexity and cost; in digital applications, the integration of depletion-mode and enhanced HEMTs forms Direct coupled field effect transistor logic (DCFL) can provide the simplest circuit structure; in power electronics applications, due to system reliability and cost requirements, there is usually no negative power supply, so the core switching devices used in power electronics systems must be enhanced type (normally off) device. An important application of heterojunction field effect transistors is in high-frequency, high-speed circuit systems, which require higher device cut-off frequencies and maximum oscillation frequencies.

At present, the technologies for realizing enhanced HEMT devices include trench gate technology, fluorine treatment technology and the so-called GIT technology of p-type gate. The technical process control is very difficult, and the reliability of fluorine treatment technology and GIT technology has yet to be verified. In addition, based on the ordinary HEMT structure, the improvement of the frequency performance of the device mainly depends on reducing the gate length. The current technology has realized a device with a gate length of 30-50nm. If it is necessary to further improve the frequency characteristics of the device, it will inevitably encounter to great craft difficulty. Based on the above reasons, we propose a new HEMT device structure, which can realize a wide range of adjustment of the device threshold voltage, and even realize an enhanced device, and can effectively improve the frequency performance of the device under the condition of the same gate length.

Contents of the invention

In view of the deficiencies in the prior art, the purpose of the present invention is to propose a heterojunction field effect transistor with a new structure to meet the needs of practical applications.

In order to realize the above-mentioned purpose of the invention, the present invention has adopted following technical scheme:

A heterojunction field effect transistor based on a channel array structure, comprising a heterojunction, the heterojunction comprising a first semiconductor layer and a second semiconductor layer stacked from top to bottom, the first semiconductor layer and the A two-dimensional electron gas is formed at the interface of the second semiconductor layer, a source, a drain, and a gate are arranged on the first semiconductor layer, and the gate is arranged between the source and the drain, and it is characterized in that:

More than one channel is formed in the heterojunction below the gate, and the two ends of the electronic channel point to the source and the drain respectively.

Further speaking, a channel array composed of a plurality of channels arranged side by side is provided in the heterojunction below the gate.

A gate metal layer for forming a gate is continuously covered on the upper end surface and two side walls of the channel.

Preferably, an insulating layer or an oxide layer is further provided between the upper end surface and side walls of the channel and the gate metal layer.

The width of the channel is 1 nm˜10 μm.

The gate metal layer extends from a selected position between two ends of the channel to cover an edge portion of an end of the channel close to the source or the drain.

The gate metal layer is distributed between two ends of the channel.

A Schottky contact, a metal-insulator-semiconductor contact or a metal-oxide layer-semiconductor contact is formed between the gate and the heterojunction.

The heterojunction field effect transistor also includes a field plate structure.

The heterojunction field effect transistor adopts planar isolation or mesa isolation.

A heterojunction field effect transistor based on a channel array structure, comprising a heterojunction, the heterojunction comprising a first semiconductor layer and a second semiconductor layer stacked from top to bottom, the first semiconductor layer and the A two-dimensional electron gas is formed at the interface of the second semiconductor layer, a source, a drain, and a gate are arranged on the first semiconductor layer, and the gate is arranged between the source and the drain, and it is characterized in that:

More than one channel is formed in the heterojunction below the gate. the gate metal layer of the gate;

The first semiconductor layer and the second semiconductor layer are respectively a layered structure formed of at least one semiconductor material or a stacked structure formed of two or more semiconductor materials or a combination thereof.

The channels are plural, arranged side by side to form a channel array, and each channel has a width of 1nm-10μm.

Preferably, the first semiconductor layer is GaN, Al _x Ga _1-x N, AlN, In _x Al _1-x N, In _x Aly Ga _{1-xy N} , In _x Al _1-x As, In _x A layered structure formed by any one of Ga _1-x As, Al _x Ga _1-x As, and In _x Al _1-x Sb, or a stacked structure formed by any two or more materials or a combination thereof, wherein, 0 ≤ x ≤ 1, 0 ≤ Y ≤ 1, and 0 ≤ x+Y ≤ 1.

Preferably, the second semiconductor layer is GaN, Al _x Ga _1-x N, AlN, In _x Al _1-x N, In _x Aly Ga _{1-xy N} , In _x Al _1-x As, In _x A layered structure formed by any one of Ga _1-x As, Al _x Ga _1-x As and InP, or a stacked structure formed by any two or more materials or a combination thereof, where 0≤x≤1,0 ≤ Y ≤ 1, and 0 ≤ x+Y ≤ 1.

Of course, the above-mentioned first semiconductor layer and second semiconductor layer may also be formed of other semiconductor materials known to those skilled in the art besides the above-mentioned materials.

The working principle of the new structure heterojunction field effect transistor is:

For a single channel, the gate metal covers the channel. In addition to the modulation from the vertical direction above, the modulation of the gate to the channel also has modulation from both sides of the sidewall, because when the channel width is reduced, the gate regulation from both sides of the sidewall cannot be ignored, thus forming a ring gate effect. This ring-grid structure can bring about the following effects:

(1) The gate modulation of the sidewall increased by the gate-around structure will increase the control capability of the device, thereby increasing the transconductance of the device and also increasing the gate capacitance. Through process adjustment, the increase in transconductance is greater than the increase in gate capacitance, which can lead to an increase in the cut-off frequency of the device;

(2) With the increase of gate control capability, the channel structure will deplete more two-dimensional electron gas compared with traditional devices under the same gate voltage, causing a positive shift in the threshold voltage of the device;

(3) This ring-gate structure makes the electric field of each channel more uniform. In the case of such a uniform electric field and high electric field, the electrons in the channel can obtain greater energy, which may make the acoustic phonons in the channel and intervalley phonon scattering become the dominant scattering mechanism, and this scattering has a very weak sensitivity to the lattice temperature. Therefore, the new structure heterojunction field effect transistor can maintain a stable drain saturation current at high temperature.

Further analysis, due to the introduction of channels, the current of a single channel is much smaller than that of traditional devices, so the heat dissipation is better than traditional devices, so it can effectively suppress the self-heating effect existing in traditional heterojunction field effect transistors . In the heterojunction of some strongly polarizable materials (such as GaN material system), the two-dimensional electron gas in the channel is mainly caused by the polarization effect (spontaneous polarization and piezoelectric polarization). At the edge of the channel, due to the release of the stress, the piezoelectric polarization effect disappears, and the part of the two-dimensional electron gas caused by the polarization effect at the interface of the channel edge will also disappear, thereby making the threshold voltage of the device further to the positive direction. drift. Finally, when the upper gate is used, due to the work function difference between the gate metal and the semiconductor, the two-dimensional electron gas under the gate and at the edge of the channel will be further depleted. If the threshold voltage of the device without the gate is already Very close to zero in the negative direction, the application of the gate metal will likely drift the threshold voltage of the device to a positive value, thereby forming an enhancement-mode heterojunction field-effect transistor.

The new structure field-effect transistor can be completed by traditional semiconductor micro-processing technology, and the equipment that can be used includes photolithography systems (such as electron beam lithography, ion beam lithography, immersion lithography, distributed exposure and optical exposure, etc.) , nanoimprinting, etching equipment (RIE, ICP, etc.), ion implantation equipment, etc.

Description of drawings

Fig. 1a is a three-dimensional structural schematic diagram of a Schottky gate heterojunction field effect transistor based on a channel array structure in embodiment 1;

Figure 1b is a top view of the Schottky gate heterojunction field effect transistor based on the channel array structure in embodiment 1;

Figure 1c is a partial enlarged view of the Schottky gate heterojunction field effect transistor based on the channel array structure in embodiment 1;

Fig. 2 is a schematic cross-sectional structure diagram of a channel array of a Schottky gate in Fig. 1;

3 is a schematic cross-sectional structure diagram of a metal-insulator-semiconductor (MIS) contact channel array in Embodiment 2;

4 is a schematic diagram of a three-dimensional structure of a Schottky gate heterojunction field effect transistor with a single channel in Embodiment 3;

5 is a schematic diagram of a three-dimensional structure of a heterojunction field effect transistor in which the gate metal overlaps with the edge of the channel array near the source in Example 4;

FIG. 6 is a schematic three-dimensional structure diagram of a heterojunction field effect transistor in which the gate metal overlaps with the edge of the channel array near the drain in Embodiment 5. FIG.

detailed description

The core design concept of the heterojunction field effect transistor of the present invention is to adopt a channel array structure, and its basic structure is shown in Figures 1a-1c. A channel array is fabricated between the source and drain of the heterojunction field effect transistor and under the gate. The structure of the channel array is shown in Figure 2, which is formed by connecting one or more channels in parallel.

Generally speaking, realizing the technical scheme of the present invention is:

The new structure heterojunction field effect transistor based on the channel array structure introduces the channel array structure on the basis of the traditional heterojunction field effect transistor structure. One or more channels are formed in parallel.

Specifically, the channel array structure is applicable to all semiconductor electronic devices based on the operation of two-dimensional electron gas at the heterojunction interface.

The isolation of the heterojunction field effect transistor may adopt planar isolation or mesa isolation.

Preferably, the width of the channels in the channel array can be from several nanometers to several micrometers, that is, in the range of 1 nm to 10 μm.

The planar geometry of the channels in the channel array is regular or irregular.

The channel array can be a single channel or a plurality of channels.

In the channel array, the dimensions of the parallel channels are the same size or different sizes; the shapes of the parallel channels are the same shape or different shapes.

The gate metal covers the channel array.

The gate metal overlaps with the side of the edge of the channel array close to the source end or the drain end, or does not overlap with the edge of the channel array.

The shape of the gate metal is a common, T-shaped or V-shaped gate; the size of the gate metal is submicron or larger.

The contact formed between the gate metal and the semiconductor can be a Schottky contact, or in order to further reduce the gate leakage current and increase the breakdown voltage of the device, a metal-insulator-semiconductor contact or a metal-oxide layer-semiconductor contact can also be used touch.

There may be no field plate in the structure of the heterojunction field effect transistor, or a field plate may also be added to increase the breakdown voltage of the device and improve the performance of the device.

It should be noted that the channel described in the present invention is a conductive channel known to those skilled in the art, which is actually formed in a heterojunction located below the gate with two ends pointing to the source respectively. and the strip of the drain electrode, the two sides of the strip are respectively provided with grooves from the first semiconductor layer to the second semiconductor layer, and at the same time, the upper end surface and the two side walls of the strip are continuously covered with a gate metal layer. The aforementioned channel array is an array structure composed of several strips distributed in parallel.

In order to make the substantive structural features, implementation methods and beneficial effects of the heterojunction field effect transistor of the present invention easier to understand, the technical solution of the present invention will be described in further non-limiting detail below in combination with several preferred embodiments and accompanying drawings.

Example 1

Referring to Fig. 1a, the Schottky gate heterojunction field effect transistor based on channel array structure is composed of heterojunction epitaxial material (including semiconductor 1 and semiconductor 2), source 3, drain 4, channel array 5 and gate Pole 6 composition. Wherein, the semiconductor 1 and the semiconductor 2 constituting the heterojunction can be any semiconductor material that can form a two-dimensional electron gas 7 at the heterojunction. The two-dimensional electron gas 7 in the channel is adjusted and controlled through the gate 6, so as to control the device to be in the cut-off region, the linear region and the saturation region. The channel array 5 is formed by a plurality of channels 8 connected in parallel, and is located between the source 3 and the drain 4 and in the active region below the gate 6 . In this embodiment, the gates 6 are located between the channel arrays 5, which can be clearly seen in Figures 1b and 1c. As can be seen from FIG. 2 , the gate metal 6 covers the top and both sides of the channel 8 , forming a gate-all-around structure to regulate the heterojunction channel. According to the structure described in this embodiment, taking AlGaN/GaN HEMT as an example, the width of the channel 8 is 70nm, a total of 1000 channels are connected in parallel, the metal thickness of the gate 6 is 300nm, the length of the gate 6 is 300nm, the gate 6 and The structure design with a pitch of 2µm between the source 3 and a pitch of 3µm between the gate 6 and the drain 4, compared with the traditional structure device, can realize the enhanced AlGaN/GaN HEMT with a threshold voltage of 0.15V, and increase the transconductance of the device by five When the parasitic gate capacitance is doubled, the cut-off frequency of the device can be at least doubled.

Example 2

Referring to FIG. 3 , the insulated gate heterojunction field effect transistor based on the channel array structure includes a semiconductor 1 , a semiconductor 2 , an insulating dielectric layer 9 and a gate 6 . A high-density two-dimensional electron gas exists at the heterojunction interface. An insulating dielectric layer covers the channel array 5 , and the uppermost layer is covered with gate metal to modulate the two-dimensional electron gas in the channel. Wherein, the insulating dielectric layer may be an oxide (such as silicon dioxide, aluminum oxide, hafnium oxide, etc.), or a non-oxide dielectric layer (such as silicon nitride, aluminum nitride, etc.). According to this embodiment, taking AlGaN/GaN HEMT as an example, a layer of Al ₂ O ₃ with a thickness of 10 nm is deposited between the gate 6 metal and AlGaN by ALD, which can reduce the gate leakage current by four orders of magnitude. The control ability of the gate to the channel is effectively enhanced.

Example 3

Referring to FIG. 4 , the single channel heterojunction field effect transistor includes a semiconductor 1 , a semiconductor 2 , a source 3 , a drain 4 , a channel 8 and a gate 6 . A high-density two-dimensional electron gas 7 exists at the heterojunction interface. The device consists of a single channel 8, and the gate 6 covers both sides of the channel 8 to modulate the two-dimensional electron gas 7 at the heterointerface. The source 3 is grounded, and the drain 4 is applied with a forward voltage to make channel electrons flow from the source 3 to the drain 4 . According to this embodiment, taking the AlGaN/GaN heterojunction as an example, the width of the channel 8 is 500 nm, the metal thickness of the gate 6 is 300 nm, and the length of the gate ₆ is 300 nm. The saturation leakage current is 850mA/mm, and the maximum peak transconductance is 195mS/mm, compared with the saturation leakage current of 570mA/mm at V _gs =1.5V of traditional AlGaN/GaN HEMT devices, and the maximum peak transconductance is 155mS/mm . Both the saturation leakage current and the maximum peak transconductance of the device are increased.

Example 4

Referring to FIG. 5 , in this embodiment, the gate 10 overlaps with the side of the channel array 5 that is close to the source 3 . The whole transistor is composed of heterojunction epitaxial material (including semiconductor 1 and semiconductor 2 ), source 3 , drain 4 , channel array 5 and gate 7 . The gate 7 is not located between the channel arrays 5 , but partly covers the channel array 5 , and another part covers the active region between the channel array 5 and the source 3 . Thus, a structure in which the gate 7 overlaps with the edge of the channel array 5 close to the source 3 is formed. According to this embodiment, taking an AlGaN/GaN HEMT device as an example, the width of a single channel 8 in the channel array 5 is 200nm, the length of the channel 8 is 1µm, a total of 1000, the metal thickness of the gate 10 is 300nm, and the gate 10 The length is 500nm, and the length of the metal part of the gate 10 covering the channel array 5 is 300nm. Compared with the traditional device, the transconductance of the channel array device is increased by five times, and the parasitic gate capacitance is increased by two times, so that the cut-off frequency of the device can be increased by at least two times.

Example 5

Referring to FIG. 6 , in this embodiment, the gate 11 overlaps with the edge of the channel array 5 which is close to the drain 4 . The whole transistor is composed of heterojunction epitaxial material (including semiconductor 1 and semiconductor 2 ), source 3 , drain 4 , channel array 5 and gate 11 . The gate 11 is not located between the channel arrays 5 , but partly covers the channel array 5 , and another part covers the active region between the channel array 5 and the drain 4 . Thus, a structure in which the gate 11 overlaps with the edge of the channel array 5 close to the drain 4 is formed. According to this embodiment, taking the AlGaN/GaN HEMT device as an example, the width of a single channel 8 in the channel array is 200nm, the length of the channel 8 is 1µm, a total of 1000, the metal thickness of the gate 11 is 300nm, and the length of the gate 11 is The length of the metal portion of the gate 11 covering the channel array 5 is 300 nm. Compared with the traditional device, the transconductance of the channel array device is increased by five times, and the parasitic gate capacitance is increased by two times, so that the cut-off frequency of the device can be increased by at least two times.

The above-mentioned Schottky gate heterojunction field effect transistors (Example 1, Example 4 and Example 5), single channel field effect transistors (Example 3) and insulated gate transistors based on the channel array structure respectively The field effect transistor (Example 2) is taken as an example to illustrate the technical solution of the present invention. In actual design, the channel array structure can be applied to heterojunction field effect transistors with or without field plates; corresponding to each channel, the dimensions of the parallel channels can be the same size or different sizes; the shape can be be the same shape or not the same shape. Therefore, the above-mentioned embodiments are only to illustrate the technical concept and characteristics of the present invention, and its purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly, and not to limit the protection scope of the present invention. All equivalent changes or modifications made according to the spirit of the present invention shall fall within the protection scope of the present invention.

Claims (8)

1. A heterojunction field effect transistor based on a channel array structure, comprising a heterojunction, the heterojunction comprising a first semiconductor layer and a second semiconductor layer stacked from top to bottom, the first semiconductor A two-dimensional electron gas is formed at the interface between the layer and the second semiconductor layer, a source, a drain, and a gate are arranged on the first semiconductor layer, and the gate is arranged between the source and the drain, and it is characterized in that : The heterojunction below the gate is provided with a channel array, and the channel array is composed of a plurality of channels arranged side by side with a width of 1 nm to 10 μm, wherein the two ends of any channel point to the source respectively. electrode and drain, and the upper end surface and both side walls of any channel are continuously covered with a gate metal layer for constituting the gate, and the gate metal layer is selected from one of the two ends of the channel. The position extends to cover the edge portion of one end of the channel close to the source or the drain. 2. The heterojunction field effect transistor based on the channel array structure according to claim 1, characterized in that the first semiconductor layer and the second semiconductor layer have a layered structure formed of at least one semiconductor material or are formed by A stacked structure formed of two or more semiconductor materials or a combination thereof. 3. The heterojunction field effect transistor based on the channel array structure according to any one of claims 1-2, characterized in that an upper end face and two side walls of the channel and a gate metal layer are further provided There is an insulating dielectric layer. 4. The heterojunction field effect transistor based on the channel array structure according to any one of claims 1-2, characterized in that a Schottky contact or metal-insulation is formed between the gate and the heterojunction layer-semiconductor contact. 5. The heterojunction field effect transistor based on the channel array structure according to claim 1, characterized in that the heterojunction field effect transistor further comprises a field plate structure. 6 . The heterojunction field effect transistor based on the channel array structure according to claim 1 , wherein planar isolation or mesa isolation is adopted in the heterojunction field effect transistor. 7. The heterojunction field effect transistor based on the channel array structure according to claim 1, characterized in that the first semiconductor layer is GaN, AlxGa1 _{- xN} , AlN, InxAl1 _{- x} Formed from any one of N, In _x Al _y Ga _1-xy N, In _x Al _1-x As, In _x Ga _1-x As, Al _x Ga _1-x As and In _x Al _1-x Sb A layered structure or a laminated structure formed by any two or more materials or a combination thereof, where 0≤x≤1, 0≤Y≤1, and 0≤x+Y≤1. 8. The heterojunction field effect transistor based on the channel array structure according to claim 1, characterized in that the second semiconductor layer is GaN, AlxGa1 _{- xN} , AlN, InxAl1 _{- x} A layered structure formed by any one of N, In _x Al _y Ga _1-xy N, In _x Al _1-x As, In _x Ga _1-x As, Al _x Ga _1-x As and InP or any A laminated structure formed by two or more materials or a combination thereof, where 0≤x≤1, 0≤Y≤1, and 0≤x+Y≤1.