CN103871889A - PMOS (P-channel metal oxide semiconductor) transistor and forming method thereof - Google Patents
PMOS (P-channel metal oxide semiconductor) transistor and forming method thereof Download PDFInfo
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- CN103871889A CN103871889A CN201210553318.3A CN201210553318A CN103871889A CN 103871889 A CN103871889 A CN 103871889A CN 201210553318 A CN201210553318 A CN 201210553318A CN 103871889 A CN103871889 A CN 103871889A
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- H10D30/00—Field-effect transistors [FET]
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- H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
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Abstract
一种PMOS晶体管及其形成方法，所述PMOS晶体管包括：半导体衬底、位于半导体衬底上的栅极结构、位于栅极结构侧壁上的主侧墙和位于主侧墙两侧半导体衬底内的锗硅层，所述锗硅层呈线宽逐渐减小的阶梯状。本发明PMOS晶体管的形成方法工艺简单，所形成PMOS晶体管性能较佳。
A PMOS transistor and a method for forming the same, the PMOS transistor comprising: a semiconductor substrate, a gate structure on the semiconductor substrate, main sidewalls on the sidewalls of the gate structure, and semiconductor substrates on both sides of the main sidewall The inner silicon germanium layer is in the shape of a ladder with gradually decreasing line width. The method for forming the PMOS transistor of the present invention is simple in process, and the performance of the formed PMOS transistor is better.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of PMOS transistor and forming method thereof.
Background technology
Transistor is just being widely used at present as the most basic semiconductor device, and along with the raising of component density and the integrated level of semiconductor device, transistorized grid size becomes than in the past shorter; But transistorized grid size shortens and can make transistor produce short-channel effect, and then produces leakage current, finally affects the electric property of semiconductor device.At present, prior art mainly, by improving the stress of transistor channel region, to improve carrier mobility, and then improves transistorized drive current, reduces the leakage current in transistor.
The method that prior art improves the stress of transistor channel region is: form stress liner layer in transistorized source/drain region, wherein, the material of the transistorized stress liner layer of PMOS is SiGe (SiGe), between SiGe in silicon in Semiconductor substrate and stress liner layer because lattice mismatch forms compression, thereby improve PMOS transistorized performance; The material of the stress liner layer of nmos pass transistor is carborundum (SiC), between the carborundum in the silicon in Semiconductor substrate and stress liner layer because lattice mismatch forms tension stress, thereby improve the performance of nmos pass transistor.
Prior art, in the time that formation has the PMOS transistor of stress liner layer, comprises the steps:
With reference to figure 1, Semiconductor substrate 101 is provided, form grid structures on described Semiconductor substrate 101 surfaces, described grid structure comprise the gate dielectric layer 103 that is positioned in Semiconductor substrate 101, be positioned at the grid 105 on gate dielectric layer 103 and be positioned at gate dielectric layer 103 and grid 105 sidewalls on side wall 107;
With reference to figure 2, by being dry-etched in the interior formation opening 109 of Semiconductor substrate 101 of grid structure both sides;
With reference to figure 3, by the Semiconductor substrate 101 of opening 109 bottoms and sidewall described in wet-etching technology etching, form the groove that is Sigma (Sigma or Σ) shape;
Continue with reference to figure 3, in described groove, fill full germanium silicon layer 111.
But, along with the development of semiconductor technology, more and more higher to the requirement of device performance, the transistorized formation method of existing PMOS improve aspect the PMOS transistor performance that forms effect limited; And, carry out the more difficult control of Sigma's shape groove shapes of wet etching formation by the Semiconductor substrate on open bottom and sidewall, the transistorized unstable properties of the PMOS that forms.
The transistors with stress liner layer please refer to the U.S. Patent application that publication number is US2011256681A1 more.
Summary of the invention
The problem that the present invention solves is to provide a kind of PMOS transistor and forming method thereof, reduces and forms PMOS transistorized technology difficulty, improve the transistorized performance of the PMOS that forms.
For addressing the above problem, the invention provides a kind of transistorized formation method of PMOS, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, is formed with grid structure;
On the sidewall of described grid structure, form master wall;
The semiconductor substrate surface of oxidation master wall both sides, forms the first oxide layer;
Remove described the first oxide layer, in Semiconductor substrate, form the first groove;
On the sidewall of master wall side and the first groove, form pseudo-side wall;
Be oxidized the semiconductor substrate surface in the first groove of pseudo-side wall both sides, form the second oxide layer;
Remove described the second oxide layer, form the second groove connecting with the first groove in Semiconductor substrate, the live width of described the second groove is less than the live width of the first groove;
Remove described pseudo-side wall;
In groove, fill full germanium silicon layer.
Accordingly, the present invention also provides a kind of PMOS transistor, comprise: Semiconductor substrate, be positioned at grid structure in Semiconductor substrate, be positioned at the master wall on grid structure sidewall and be positioned at the germanium silicon layer of master wall semiconductor substrates on two sides, described germanium silicon layer is stepped that live width reduces gradually.
Compared with prior art, technical solution of the present invention has the following advantages:
Semiconductor substrate surface by oxidation master wall both sides forms the first oxide layer, and remove the first oxide layer, in Semiconductor substrate, form the first groove, on the sidewall of master wall side and the first groove, form pseudo-side wall again, and be oxidized the semiconductor substrate surface in the first groove of pseudo-side wall both sides, form the second oxide layer, and remove the second oxide layer, in Semiconductor substrate, form the second groove that is less than the first groove with the first groove perforation and live width; Then remove pseudo-side wall, in groove, fill full germanium silicon layer.After pseudo-side wall is removed, the first groove and the second groove have formed the cascade groove that live width reduces gradually, make formed germanium silicon layer also stepped, due to stepped germanium silicon layer and Semiconductor substrate mismatch larger, increase the compression stress that puts on PMOS transistor channel region, and then improved the mobility of charge carrier in PMOS transistor channel region; In addition, because the thickness of the first formed oxide layer, the second oxide layer and pseudo-side wall is more easy to control, the shape of the germanium silicon layer that forms is more easy to control, has reduced the transistorized technology difficulty of formation PMOS, to form PMOS transistor performance more stable.
Further, the thickness of described pseudo-side wall is 10nm ~ 20nm, the distance on PMOS transistor channel region and immediate stepped germanium silicon layer top is 10nm ~ 20nm, the compression stress that puts on PMOS transistor channel region is larger, further improve the mobility in hole in PMOS transistor channel region, improved the transistorized performance of PMOS.
Further, described grid structure top is also coated with stop-layer, injury-free with grill-protected electrode structure in the formation of the formation of oxide layer and removal, pseudo-side wall and in removing technique, has further ensured the transistorized performance of formation PMOS.
Accompanying drawing explanation
Fig. 1 to Fig. 3 is that existing technique forms the transistorized schematic diagram of PMOS;
Fig. 4 to Figure 14 is by being formed the transistorized schematic diagram of PMOS in embodiment of the transistorized formation method of PMOS of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Set forth in the following description a lot of details so that fully understand the present invention, implemented but the present invention can also adopt other to be different from alternate manner described here, therefore the present invention is not subject to the restriction of following public specific embodiment.
Just as described in the background section, along with the development of semiconductor technology, more and more higher to the requirement of device performance, the transistorized formation method of existing PMOS improve aspect the PMOS transistor performance that forms effect limited; And, carry out the more difficult control of Sigma's shape groove shapes of wet etching formation by the Semiconductor substrate on open bottom and sidewall, the transistorized unstable properties of the PMOS that forms.
For above-mentioned defect, the invention provides a kind of transistorized formation method of PMOS, after master wall on grid structure in Semiconductor substrate and grid structure sidewall forms, semiconductor substrate surface by oxidation master wall both sides forms the first oxide layer, and remove the first oxide layer, in Semiconductor substrate, form the first groove, on the sidewall of master wall side and the first groove, form pseudo-side wall again, and be oxidized the semiconductor substrate surface in the first groove of pseudo-side wall both sides, form the second oxide layer, and removal the second oxide layer, in Semiconductor substrate, form with the first groove and connect, and live width is less than the second groove of the first groove, then remove pseudo-side wall, in groove, fill full germanium silicon layer.The transistorized formation method of PMOS of the present invention technique is simple, the transistorized performance of the PMOS that forms better.
Be elaborated below in conjunction with accompanying drawing.
With reference to figure 4, Semiconductor substrate 201 is provided, in described Semiconductor substrate 201, be formed with grid structure.
Concrete, the material of described Semiconductor substrate 201 is silicon, germanium silicon or silicon-on-insulator.In the present embodiment, the material of described Semiconductor substrate 201 is silicon.
Described grid structure comprises the gate dielectric layer 203 being positioned in Semiconductor substrate 201 and is positioned at the grid 205 on described gate dielectric layer 203.In the present embodiment, the material of described gate dielectric layer 203 is silica, and the material of described grid 205 is polysilicon.
In the present embodiment, after forming grid 205, stop-layer 209 is formed on the top that is also included in grid 205, and the material of described stop-layer 209 is silicon nitride (SiN), to protect described grid 205 in subsequent technique.
It should be noted that, in the present embodiment, in described Semiconductor substrate 201, be also formed with fleet plough groove isolation structure 202, for defining the transistorized active area of PMOS.
In other embodiments, the material of described stop-layer 209 also can be amorphous carbon.
Continue with reference to figure 4, form the main spacer material 207a that covers described stop-layer 209, Semiconductor substrate 201 and fleet plough groove isolation structure 202 upper surfaces and gate dielectric layer 203, grid 205 and stop-layer 209 sidewalls.
Described main spacer material 207a can be silicon nitride or amorphous carbon single layer structure, also can be the double-decker that comprises silicon oxide layer and be positioned at the silicon nitride layer on silicon oxide layer.
Concrete, in the time that the material of described stop-layer 209 is silicon nitride, described main spacer material 207a can be silicon nitride single layer structure or comprises silicon oxide layer and the double-decker that is positioned at the silicon nitride layer on silicon oxide layer; In the time that the material of described stop-layer 209 is amorphous carbon, described main spacer material 207a is amorphous carbon single layer structure.
In the present embodiment, described main spacer material 207a is the double-decker that comprises silicon oxide layer and silicon nitride layer.
With reference to figure 5, main spacer material 207a described in Fig. 4 is carried out to etching, to remaining the main spacer material being positioned on stop-layer 209, gate dielectric layer 203 and grid 205 sidewalls, form master wall 207b.
In the present embodiment, the method that forms master wall 207b can be anisotropic dry etch, and it specifically forms technique and is well known to those skilled in the art, and does not repeat them here.
With reference to figure 6, by Semiconductor substrate 201 surfaces described in plasma enhanced chemical vapor deposition technique oxidation Fig. 5, form the first oxide layer 211.
In the present embodiment, the reacting gas of described plasma enhanced chemical vapor deposition technique is ozone or oxygen, the pressure of described plasma enhanced chemical vapor deposition technique is 1torr ~ 100torr, power is 50W ~ 1500W, flow is 100sccm ~ 20000sccm, and temperature is 100 ℃ ~ 600 ℃.
In the time carrying out plasma enhanced chemical vapor deposition technique, in the Semiconductor substrate 201 of the oxonium ion entering part thickness in settling chamber, and react with silicon or germanium atom in Semiconductor substrate 201, form the first oxide layer 211 on Semiconductor substrate 201 surfaces.
In the present embodiment, the material of first oxide layer 211 that forms is silica.
With reference to figure 7, remove oxide layer 211 described in Fig. 6, expose the sidewall of master wall 207b below segment thickness Semiconductor substrate 201, form the first groove 212.
In the present embodiment, the method for removing described oxide layer 211 is dry etching or wet etching.Concrete, in the time that the method for the described oxide layer 211 of removal is dry etching, its etching gas can be fluorine-containing gas; In the time that the method for the described oxide layer 211 of removal is wet etching, the solution of described wet etching can be hydrofluoric acid solution.
With reference to figure 8, form stop-layer 209 and fleet plough groove isolation structure 202 upper surfaces, the bottom surface of the first groove 212 and the pseudo-spacer material 213a of sidewall and master wall 207 sides in coverage diagram 7.
The material of described pseudo-spacer material 213a can be amorphous carbon, silicon nitride or carbonitride of silicium; The thickness of described pseudo-spacer material 213a is 10nm ~ 20nm.
Concrete, when described master wall 207b is silicon nitride single layer structure or when comprising silicon oxide layer and being positioned at the double-decker of the silicon nitride layer on silicon oxide layer, the material of described pseudo-spacer material 213a can be amorphous carbon; In the time that described master wall 207b is amorphous carbon single layer structure, the material of described pseudo-spacer material 213a can be silicon nitride or carbonitride of silicium.Because the material of pseudo-spacer material 213a is different from the material of the master wall 207 exposing, in the time of the pseudo-side wall of follow-up removal, can avoid master wall 207 to cause damage.
In the present embodiment, the material of described pseudo-spacer material 213a is amorphous carbon, and the method that forms described pseudo-spacer material 213a can be chemical vapor deposition method.
With reference to figure 9, pseudo-spacer material 213a described in Fig. 8 is carried out to etching, to remaining the pseudo-spacer material being positioned on master wall 207 sides and the first groove 212 sidewalls, form pseudo-side wall 213b.
In the present embodiment, the method for pseudo-spacer material 213a described in Fig. 8 being carried out to etching is dry etching, and as anisotropic dry etch, its concrete etching technics is well known to those skilled in the art, and does not repeat them here.The thickness of the pseudo-side wall 213b that forms is 10nm ~ 20nm.
Continue with reference to figure 9, be oxidized pseudo-side wall 213b semiconductor substrates on two sides 201 surfaces by plasma enhanced chemical vapor deposition technique, form the second oxide layer 215.
In the present embodiment, the method that forms the second oxide layer 215 is identical with the method that forms the first oxide layer 211, does not repeat them here.
With reference to Figure 10, remove the second oxide layer 215 described in Fig. 9, expose the sidewall of pseudo-side wall 213b below segment thickness Semiconductor substrate 201, the second groove 216 connecting at the interior formation of Semiconductor substrate 201 and the first groove 212, the live width of described the second groove 216 is less than the live width of the first groove 212.
In the present embodiment, the method for removing the second oxide layer 215 is identical with the method for removing the first oxide layer 211, does not repeat them here.
With reference to Figure 11, remove pseudo-side wall 213b described in Figure 10, expose the cascade groove that the live width that is made up of the first groove 212 and the second groove 216 reduces gradually.
In the present embodiment, the method for removing described pseudo-side wall 213b is cineration technics, and the reacting gas of described cineration technics is oxygen.
With reference to Figure 12, in cascade groove described in Figure 11, form germanium silicon 217, the upper surface of described germanium silicon layer 217 is not less than the upper surface of the Semiconductor substrate 201 of grid structure below.
In the present embodiment, the method that forms described germanium silicon layer 217 is epitaxial growth technology, and the germanium silicon layer 217 forming is also stepped.
With reference to Figure 13, for the enlarged drawing of Semiconductor substrate 201 in rectangular broken line region in Figure 12, it shows in Figure 12 10 diverse location 201a, 201b, 201c, 201d, 201e, 201f, 201g, 201h, 201i and 201j in grid structure lower semiconductor substrate 201, wherein position 201a, 201b, the transistorized channel region of the corresponding PMOS of 201c.After in Figure 12, germanium silicon layer 217 forms, by microbeam diffraction approach (Nano-Beam Electron Diffraction, referred to as NBD or NBED) edge, above-mentioned 10 positions in Semiconductor substrate 201 is measured with the stress of PMOS transistor channel region parallel direction, and the stress of desired location 201j is 0, percent strain is 0, the percent strain (unit is: %) to all the other 9 positions is calculated.
As shown in figure 14, in Semiconductor substrate 201, the percent strain of position 201a, 201b, 201c, 201d, 201e, 201f, 201g, 201h, 201i and 201j is respectively-0.8% ,-0.8% ,-0.7% ,-0.5% ,-0.6% ,-0.6% ,-0.7% ,-0.7% ,-0.5% and 0, wherein, "-" represents that edge, each position is compression stress with the stress of PMOS transistor channel region parallel direction.For position 201a, its edge is compression stress with the stress of PMOS transistor channel region parallel direction, and size is 1.3 Gpa.Position 201b, 201c, 201d, 201e, 201f, 201g, 201h and 201i are along can by the stress of position 201a and Figure 14 is corresponding obtaining with the stress of PMOS transistor channel region parallel direction.
As shown in Figure 14, by germanium silicon layer 217 is formed stepped, make the lattice misfit Du Genggao of germanium silicon layer 217 and Semiconductor substrate 201, improve the compression stress in PMOS transistor channel region, and then can improve in PMOS transistor the migration rate of charge carrier (" hole ") in channel region, improve the transistorized response speed of formation PMOS.
And, because germanium silicon layer 217 and the distance of PMOS transistor channel region can be by the THICKNESS CONTROL of pseudo-side wall 213b in Figure 10, therefore can reduce by the thickness of the pseudo-side wall 213b of attenuate the distance of germanium silicon layer 217 and PMOS transistor channel region, further improve the compression stress in PMOS transistor channel region, improved the transistorized performance of PMOS.
In addition, because the shape of pseudo-side wall 213b, the first oxide layer 211 and the second oxide layer 215 can accurately be controlled, therefore, the shape of the cascade groove that forms can accurately be controlled, the shape that has guaranteed to be formed at both sides, PMOS transistor channel region germanium silicon layer 217 is consistent, reduce the transistorized technology difficulty of formation PMOS, made formed PMOS transistor performance more stable.
It should be noted that, in other embodiments, can also utilize the method for above-mentioned formation the second groove 216 in Semiconductor substrate 201, to form successively several grooves that live width is successively decreased and mutually connect, to form the cascade groove that comprises more than two stratum, and then in formed cascade groove, fill germanium silicon layer, form the stepped germanium silicon layer that each stratum width successively decreases, further to improve the lattice misfit degree of germanium silicon layer and Semiconductor substrate, improve the mobility of the charge carrier in PMOS transistor channel region that forms.
Also it should be noted that, when the transistorized side wall of PMOS is silica-silicon-nitride and silicon oxide (oxide-nitride-oxide, referred to as ONO) when structure, after described cascade groove forms, also comprise: the surface at described master wall 207b forms silicon oxide layer, and silicon nitride layer and silicon oxide layer in described silicon oxide layer and described master wall 207 form the transistorized side wall of PMOS jointly.
With reference to Figure 12, the present invention also provides a kind of PMOS transistor, comprising:
Be arranged in the fleet plough groove isolation structure 202 of Semiconductor substrate 201;
Be positioned at the grid structure in Semiconductor substrate 201, described grid structure comprises the gate dielectric layer 203 being positioned in Semiconductor substrate 201 and is positioned at gate dielectric layer 203 upper gate 205;
Be positioned at the stop-layer 209 of grid 205 tops;
Be positioned at the master wall 207b on gate dielectric layer 203, grid 205 and stop-layer 209 sidewalls;
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible variation and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (19)
1. the transistorized formation method of PMOS, is characterized in that, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, is formed with grid structure;
On the sidewall of described grid structure, form master wall;
The semiconductor substrate surface of oxidation master wall both sides, forms the first oxide layer;
Remove described the first oxide layer, in Semiconductor substrate, form the first groove;
On the sidewall of master wall side and the first groove, form pseudo-side wall;
Be oxidized the semiconductor substrate surface in the first groove of pseudo-side wall both sides, form the second oxide layer;
Remove described the second oxide layer, form the second groove connecting with the first groove in Semiconductor substrate, the live width of described the second groove is less than the live width of the first groove;
Remove described pseudo-side wall;
In groove, fill full germanium silicon layer.
2. the transistorized formation method of PMOS as claimed in claim 1, is characterized in that, the method that forms the first oxide layer and the second oxide layer is plasma enhanced chemical vapor deposition technique.
3. the transistorized formation method of PMOS as claimed in claim 2, it is characterized in that, the pressure of described plasma enhanced chemical vapor deposition technique is 1torr ~ 100torr, and power is 50W ~ 1500W, gas flow is 100sccm ~ 20000sccm, and temperature is 100 ℃ ~ 600 ℃.
4. the transistorized formation method of PMOS as claimed in claim 2, is characterized in that, the reacting gas of described plasma enhanced chemical vapor deposition technique is oxygen or ozone.
5. the transistorized formation method of PMOS as claimed in claim 1, is characterized in that, before removing described pseudo-side wall, also comprises: by the method that forms the second groove, form successively several grooves that live width is successively decreased in Semiconductor substrate.
6. the transistorized formation method of PMOS as claimed in claim 1, is characterized in that, the thickness of described pseudo-side wall is 10nm ~ 20nm.
7. the transistorized formation method of PMOS as claimed in claim 1, is characterized in that, the material of described master wall is silicon nitride.
8. the transistorized formation method of PMOS as claimed in claim 7, is characterized in that, the material of described pseudo-side wall is amorphous carbon.
9. the transistorized formation method of PMOS as claimed in claim 8, is characterized in that, the method for removing described pseudo-side wall is cineration technics.
10. the transistorized formation method of PMOS as claimed in claim 1, is characterized in that, the material of described master wall is amorphous carbon.
The transistorized formation method of 11. PMOS as claimed in claim 10, is characterized in that, the material of described pseudo-side wall is silicon nitride or carbonitride of silicium.
The transistorized formation method of 12. PMOS as claimed in claim 11, is characterized in that, the method for removing described pseudo-side wall is dry etching.
The transistorized formation method of 13. PMOS as claimed in claim 1, is characterized in that, the method for removing described oxide layer is dry etching.
The transistorized formation method of 14. PMOS as claimed in claim 13, is characterized in that, the etching gas of described dry etching is fluoro-gas.
The transistorized formation method of 15. PMOS as claimed in claim 1, is characterized in that, the method for removing described oxide layer is wet etching.
The transistorized formation method of 16. PMOS as claimed in claim 15, is characterized in that, the solution of described wet etching is hydrofluoric acid solution.
The transistorized formation method of 17. PMOS as claimed in claim 1, is characterized in that, described grid structure comprises: be positioned at the gate dielectric layer in Semiconductor substrate and be positioned at the grid on described gate dielectric layer.
The transistorized formation method of 18. PMOS as claimed in claim 17, is characterized in that, before forming master wall, also comprises on the sidewall of described grid structure: stop-layer is formed on the top at described grid.
19. 1 kinds of PMOS transistors, comprise: Semiconductor substrate, be positioned at grid structure in Semiconductor substrate, be positioned at the master wall on grid structure sidewall and be positioned at the germanium silicon layer of master wall semiconductor substrates on two sides, it is characterized in that, described germanium silicon layer is stepped that live width reduces gradually.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105826364A (en) * | 2015-01-07 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Transistor and formation method thereof |
| CN108878529A (en) * | 2017-05-16 | 2018-11-23 | 中芯国际集成电路制造（天津）有限公司 | Semiconductor devices and its manufacturing method |
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| US20070020861A1 (en) * | 2005-07-16 | 2007-01-25 | Chartered Semiconductor Mfg Ltd And 2) Ibm | Method to engineer etch profiles in Si substrate for advanced semiconductor devices |
| CN101133482A (en) * | 2005-01-06 | 2008-02-27 | 英特尔公司 | Devices with stepped source/drain regions |
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- 2012-12-18 CN CN201210553318.3A patent/CN103871889A/en active Pending
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| JPS63111611A (en) * | 1986-10-30 | 1988-05-16 | Fujitsu Ltd | Manufacturing method of semiconductor device |
| CN101133482A (en) * | 2005-01-06 | 2008-02-27 | 英特尔公司 | Devices with stepped source/drain regions |
| US20070020861A1 (en) * | 2005-07-16 | 2007-01-25 | Chartered Semiconductor Mfg Ltd And 2) Ibm | Method to engineer etch profiles in Si substrate for advanced semiconductor devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105826364A (en) * | 2015-01-07 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Transistor and formation method thereof |
| CN105826364B (en) * | 2015-01-07 | 2019-01-29 | 中芯国际集成电路制造(上海)有限公司 | Transistor and forming method thereof |
| CN108878529A (en) * | 2017-05-16 | 2018-11-23 | 中芯国际集成电路制造（天津）有限公司 | Semiconductor devices and its manufacturing method |
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Application publication date: 20140618 |