CN103869559A - Pixel structure - Google Patents

Abstract

The present invention provides a pixel structure, including a substrate, a plurality of gate lines, a plurality of data lines and at least one first pixel. Gate lines and data lines are arranged on the substrate. The first pixel is disposed on the substrate and electrically connected to the corresponding gate line and data line. The first pixel includes a first electrode, a first dielectric layer and a second electrode. The first electrode is disposed on the substrate. The first dielectric layer is disposed on the first electrode, and the first dielectric layer has at least a first island portion. The second electrode is disposed on the upper surface of the first island portion, and the second electrode partially exposes the upper surface of the first island portion. The pixel structure provided by the present invention can effectively improve liquid crystal efficiency without increasing the capacitive load between the common electrode and the data line.

Description

pixel structure

technical field

The invention relates to a pixel structure, in particular to a pixel structure with high liquid crystal efficiency and low capacitance load.

Background technique

With the continuous improvement of liquid crystal display technology, liquid crystal display panels have been widely used in flat-screen TVs, notebook computers, mobile phones and various types of consumer electronic products. In order to solve the shortcoming of the conventional liquid crystal display panel with too narrow viewing angle, a fringe field switching (FFS) liquid crystal display panel has been developed in the industry. TFT substrate) on different planes, and the electric field generated by the common electrode and the pixel electrode achieves the specification of wide viewing angle.

The pixel structure of the known fringe field switching liquid crystal display panel includes a dielectric layer disposed between the common electrode and the pixel electrode, and disposed between the data line and the common electrode. The thickness of the dielectric layer will affect the efficiency of the liquid crystal. To be precise, under the same voltage difference, the thicker the dielectric layer is, the smaller the electric field of the liquid crystal is, so the efficiency of the liquid crystal is lower; on the contrary, the thicker the dielectric layer is The smaller the liquid crystal electric field is, the higher the liquid crystal efficiency will be. Therefore, considering the liquid crystal efficiency, the thickness of the dielectric layer should be as thin as possible. However, in the case that the common electrode is above the pixel electrode, the thickness of the dielectric layer is also related to the capacitive load between the common electrode and the data line, that is, the smaller the thickness of the dielectric layer, the less the common electrode and the data line. The larger the capacitive load between the data lines, the greater the load on the power.

Therefore, the known pixel structure of the fringe field switching liquid crystal display panel cannot balance the liquid crystal efficiency and the capacitive load between the common electrode and the data line.

Contents of the invention

To overcome the defects of the prior art, one of the objectives of the present invention is to provide a pixel structure with high liquid crystal efficiency and low capacitive load.

An embodiment of the present invention provides a pixel structure, including a substrate, a plurality of gate lines, a plurality of data lines and at least one first pixel. The gate line and the data line are arranged on the substrate. The first pixel is disposed on the substrate and electrically connected to the corresponding gate line and data line. The first pixel includes a first electrode, a first dielectric layer and a second electrode. The first electrode is disposed on the substrate. The first dielectric layer is disposed on the first electrode, and the first dielectric layer has at least one first island portion. The second electrode is disposed on the upper surface of the first island-shaped part, and the second electrode partially exposes the upper surface of the first island-shaped part.

Another embodiment of the present invention provides a pixel structure, including a substrate, a plurality of gate lines, a plurality of data lines, and at least one first pixel. The gate line and the data line are arranged on the substrate. The first pixel is disposed on the substrate and electrically connected to the corresponding gate line and data line. The first pixel includes a first electrode, a first dielectric layer and a second electrode. The first electrode is disposed on the substrate. The first dielectric layer is disposed on the first electrode, wherein the first dielectric layer has one or more than one first island-shaped parts respectively located in one or more buffer areas of the pixel area, and the multi-flat parts are respectively located in the pixel within a plurality of connecting regions of the buffer zone, where each connecting region is located between two adjacent buffer zones. The second electrode includes a plurality of branch electrodes disposed on the first dielectric layer, wherein each branch electrode has two end portions respectively disposed in the buffer zone, a turning portion disposed in the buffer zone, and two connecting portions respectively disposed in the first The islands are located on the upper surface of the island and are respectively located in the connecting area, wherein the two ends of each connecting part are respectively connected with the end part and the turning part.

Yet another embodiment of the present invention provides a pixel structure, including a substrate, a plurality of gate lines, a plurality of data lines, at least one first pixel and at least one second pixel. The gate line and the data line are arranged on the substrate. The first pixel is disposed on the substrate and electrically connected to the corresponding gate line and data line. The first pixel includes a first electrode, a first dielectric layer and a second electrode. The first electrode is disposed on the substrate. The first dielectric layer is disposed on the first electrode, and the first dielectric layer has at least one first island portion. The second electrode is disposed on the upper surface of the first island portion. The second pixel includes a third electrode, a second dielectric layer and a third electrode. The third electrode is disposed on the substrate. The second dielectric layer is disposed on the third electrode, and the second dielectric layer does not have an island portion. The fourth electrode is disposed on the upper surface of the second dielectric layer.

The dielectric layer of the pixel structure of the present invention has a design of unequal thickness, and the distance between adjacent branch electrodes is not equal to the distance between adjacent islands, so it can be achieved without increasing the capacitive load between the common electrode and the data line. Under the circumstances, the efficiency of liquid crystal can be effectively improved.

Description of drawings

FIG. 1 is a schematic top view of a pixel structure according to a first embodiment of the present invention.

2 is a schematic cross-sectional view of the pixel structure of the first embodiment of the application of the liquid crystal panel of the present invention along the line A-A' in FIG. 1 .

3 to 6 illustrate schematic diagrams of the method for fabricating the pixel structure in this embodiment.

FIG. 7 is a schematic top view of a pixel structure according to a second embodiment of the present invention. FIG. 8 is a schematic cross-sectional view of the pixel structure according to the second embodiment of the present invention along the line B-B' and line C-C' in FIG. 7 .

FIG. 9 is a schematic top view of a pixel structure according to a third embodiment of the present invention.

FIG. 10 is a schematic cross-sectional view of the pixel structure according to the third embodiment of the present invention along the line D-D' in FIG. 9 .

FIG. 11 is a schematic diagram of a pixel structure according to a fourth embodiment of the present invention.

FIG. 12 is a schematic diagram of a pixel structure of a fifth embodiment of the present invention.

FIG. 13 is a schematic cross-sectional view of the first pixel shown in FIG. 12 along line E-E'.

FIG. 14 is a schematic cross-sectional view of the second pixel shown in FIG. 12 along the line F-F'.

FIG. 15 is a schematic top view of a pixel structure according to a sixth embodiment of the present invention.

Wherein, the reference signs are explained as follows:

1 pixel structure

10 Substrate

C LCD panel

GL Gate Line

DL data line

P pixel

10P pixel area

P1 first pixel

12 first electrode

14 The first dielectric layer

16 Second electrode

141 First island

14T upper surface

16A Slot

16B branch electrode

16T end point

16S turning part

16C Connection part

SW Active switching element

20 Substrate

30 Display medium layer

G Gate

S source

D Drain

CH Semiconductor channel layer

CL Common Line

14B Bottom

142 Second island

14U recessed

T thickness and

D Depth

G1 spacing

G2 spacing

16E Edge electrode

17 sacrificial pattern

2 pixel structure

10PB buffer

10PC connection area

143 flat part

3 pixel structure

G3 spacing

G4 spacing

d1 distance

d2 distance

4 pixel structure

h1 thickness and

h2 thickness and

h3 thickness

5 pixel structure

P2 Second Pixel

32 The third electrode

34 Second dielectric layer

36 The fourth electrode

34T upper surface

36B branch electrode

36E Edge electrode

6 pixel structure

Detailed ways

In order for those skilled in the art to have a better understanding of the present invention, preferred embodiments of the present invention are enumerated below, together with the accompanying drawings, to describe in detail the composition and desired effects of the present invention. In addition, in order to highlight the features of the present invention, the pixel structure and the liquid crystal panel in the drawings are shown schematically.

Please refer to Figure 1 and Figure 2. FIG. 1 is a schematic top view of the pixel structure of the first embodiment of the present invention, and FIG. 2 is a schematic cross-sectional view of the pixel structure of the first embodiment of the application of the liquid crystal panel of the present invention along the line AA' in FIG. 1 . In the following description, the pixel structure of the fringe electric field switching liquid crystal display panel is taken as an example, but the pixel structure of the present invention can also be applied to other suitable display panels. As shown in FIGS. 1 and 2 , the pixel structure 1 of this embodiment includes a substrate 10 , a plurality of gate lines GL, a plurality of data lines DL and a plurality of pixels P. As shown in FIG. The substrate 10 may include a transparent substrate such as a glass substrate, a plastic substrate or a quartz substrate, but not limited thereto. The substrate 10 can be various types of rigid substrates or flexible substrates. The gate lines GL and the data lines DL intersect each other and define a plurality of pixel regions 10P (also called sub-pixel regions). Pixels P (also referred to as sub-pixels) are respectively disposed in corresponding pixel regions 10P, wherein at least one of the pixels P is a first pixel P1, which includes a first electrode 12, a first dielectric layer 14 and a second electrode 16 . The first electrodes 12 are disposed on the substrate 10, and the first electrodes 12 are electrically connected to the corresponding data lines DL. The first dielectric layer 14 is disposed on the first electrode 12 , wherein the first dielectric layer 14 has at least one first island portion 141 . The second electrode 16 is disposed on the upper surface 14T of the first island portion 141 , the second electrode 16 partially exposes the upper surface 14T of the first island portion 141 , and the second electrode 16 is electrically connected to a common potential. In this embodiment, the first electrode 12 is a pixel electrode, and the second electrode 16 is a common electrode, but not limited thereto. For example, in a variant embodiment, the first electrode 12 may be a common electrode, and the second electrode 16 may be a pixel electrode. In this embodiment, the first electrode 12 may be a complete planar electrode without slits or branch electrodes. The second electrode 16 includes a plurality of branch electrodes 16B, and a slit 16A is formed between adjacent branch electrodes 16B. In addition, each branch electrode 16B has two terminal portions 16T, a turning portion 16S, and two connecting portions 16C. The two connecting portions 16C are, for example, an elongated structure, and the two connecting portions 16C can be arranged parallel to each other or non-parallel to each other, and the turning portion 16S has a turning point, for example, the turning portion 16S can be substantially a V-shaped structure. Both ends of the connecting portion 16C are respectively connected to the terminal portion 16T and the turning portion 16S, and the terminal portion 16T is disposed on the upper surface 14T of the corresponding first island-shaped portion 141 and partially exposes the upper surface 14T of the first island-shaped portion 141 , the turning portion 16S is disposed on the corresponding upper surface 14T of the first island-shaped portion 141 , and partially exposes the upper surface 14T of the first island-shaped portion 141 . In addition, the connecting portion 16C may be selectively disposed or not disposed on the upper surface 14T of the first island portion 141 .

The first electrode 12 and the second electrode 16 can be transparent electrodes, and their materials can include various transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), aluminum indium oxide (AIO) ), indium oxide (InO), gallium oxide (gallium oxide, GaO), carbon nanotubes, silver nanoparticles, metals or alloys with a thickness less than 60 nanometers (nm), organic transparent conductive materials, or other suitable transparent conductive materials. The material of the first dielectric layer 14 may include an inorganic dielectric material such as silicon nitride, silicon oxide or silicon oxynitride, an organic dielectric material, an organic/inorganic hybrid dielectric material, or a combination of the above materials. In addition, the first dielectric layer 14 can be a single layer structure or a composite layer structure.

The liquid crystal panel C of this embodiment may further include a plurality of active switching elements SW, storage capacitor elements (not shown), alignment films (not shown), common lines CL, another substrate 20 and a display medium layer 30 . The active switching element SW may include, for example, a thin film transistor element, and the thin film transistor element may be a bottom gate type thin film transistor element, a top gate type thin film transistor element or other types of thin film transistor elements. The active switching element SW includes a gate G, a source S, a drain D and a semiconductor channel layer CH. The gate G is electrically connected to the corresponding gate line GL, the source S is electrically connected to the corresponding data line DL, the drain D is electrically connected to the corresponding first electrode 12, and the material of the semiconductor channel layer CH can be Various silicon-based semiconductor materials such as amorphous silicon, polycrystalline silicon, microcrystalline silicon, and nanocrystalline silicon, or oxide semiconductor materials such as indium gallium zinc oxide (IGZO). The common line CL can be electrically connected to the second electrode 16 to provide a common potential to the second electrode 16 . In this embodiment, the common line CL is a straight wire substantially parallel to the gate line L, but not limited thereto. In other variant embodiments, the common line CL can be other shapes of wires, such as L-shaped wires, H-shaped wires or O-shaped wires. The substrate 20 may include a light-transmitting substrate on which necessary display elements such as color filters, light-shielding patterns, and alignment films (not shown) may be disposed. The display medium layer 30 is disposed between the substrate 10 and the substrate 20 , to be precise, the display medium layer 30 may be disposed between the alignment film on the substrate 10 and the alignment film on the substrate 20 . In this embodiment, the display medium layer 30 can be a liquid crystal layer, and the liquid crystal layer can be driven by the electric field generated by the voltage difference between the first electrode 12 and the second electrode 16 when displaying.

As shown in FIG. 2 , the number of the first island-shaped portion 141 in this embodiment is one or more than one, and the first dielectric layer 14 further includes a bottom 14B and at least one second island-shaped portion 142 . The first island 141 and the second island 142 are located on the bottom 14B to form a plurality of depressions 14U. To be precise, two adjacent first islands 141 and the bottom 14B below form a depression 14U. Moreover, the adjacent first island-shaped portion 141 and the second island-shaped portion 142 and the bottom portion 14B thereunder also form a recess 14U. In addition, the thickness T of the bottom 14B of the first dielectric layer 14 and the first island portion 141 is greater than the depth D of the recess 14U. The second electrode 16 includes a plurality of branch electrodes 16B, wherein the branch electrodes 16B are respectively disposed on the upper surface 14T of the first island-shaped portion 141, and respectively expose a part of the upper surface 14T of the corresponding first island-shaped portion 141, and The second island portion 142 at least partially overlaps the corresponding data line DL. In addition, the distance G1 between two adjacent branch electrodes 16B is greater than the distance G2 between two adjacent first island-shaped portions 141 . In addition, the second electrode 16 may further include at least one edge electrode 16E disposed on the upper surface 14T of the second island portion 142 and may expose a portion of the upper surface 14T of the second island portion 142 .

In the present invention, the first electrode 12 and the second electrode 16 are separated by the first dielectric layer 14 , so the liquid crystal efficiency will be affected by the thickness of the first dielectric layer 14 . For example, when the voltage difference between the first electrode 12 and the second electrode 16 is fixed, when the thickness of the first dielectric layer 14 is smaller, the liquid crystal electric field generated by the voltage difference will be larger, so It has higher liquid crystal efficiency, or, when the thickness of the first dielectric layer 14 is smaller, the voltage difference between the first electrode 12 and the second electrode 16 does not need to be too high to achieve the required liquid crystal electric field. Furthermore, since the size of the distance G1 between two adjacent branch electrodes 16B of the second electrode 16 will affect the electric field between the first electrode 12 and the second electrode 16, the liquid crystal efficiency will also be affected by the two adjacent branch electrodes. The influence of the gap G1 between the electrodes 16B (that is, the width of the slit 16A). In addition, the second electrode 16 and the data line DL are also isolated by the first dielectric layer 14, so a larger thickness of the first dielectric layer 14 can effectively reduce the capacitive load between the second electrode 16 and the data line DL. , while avoiding generating too much electrical load. That is to say, in consideration of liquid crystal efficiency, the thickness of the first dielectric layer 14 should be as small as possible; in consideration of loading effect, the thickness of the first dielectric layer 14 should be as large as possible. Therefore, in order to balance liquid crystal efficiency and load effect, in this embodiment, the first dielectric layer 14 has a design of unequal thickness, for example, the thickness and T is greater than the depth D of the recess 14U; in addition, the distance G1 between two adjacent branch electrodes 16B is greater than the distance G2 between two adjacent first island-shaped portions 141 .

Please refer to Table 1. Table 1 lists the depth D of the depression 14U and the thickness and T of the bottom 14B and the first island-like portion 141 at different ratios (D/T), as well as the distance G2 and the branching distance between two adjacent first island-like portions 141. Simulation results of liquid crystal efficiency at different ratios (G2/G1) of the gap G1 between the electrodes 16B. Please refer to Table 1 and Figure 2 at the same time. The definition of LC efficiency is as follows:

LC efficiency=T%/(array Tr×CF Tr×AR), where

T% is the transmittance of the liquid crystal panel C;

Array Tr is the penetration rate of pixel structure 1;

CF Tr is the transmittance of the substrate 20 (with a color filter, a light-shielding pattern and an alignment film); and

AR is the aperture ratio of the liquid crystal panel C.

Table 1

The liquid crystal efficiency in Table 1 is equal to the distance G2 between two adjacent first island-like portions 141 and the distance G1 between the branch electrodes 16B (G2/G1=100%) and the first dielectric layer 14 does not have a depression The simulation results obtained by setting the liquid crystal efficiency under the condition of 14U (D/T=0) as a reference value (set to 100%). It can be seen from Table 1 that within the range where the ratio of the distance G2 between two adjacent first island-shaped portions 141 to the distance G1 between two adjacent branch electrodes 16B is greater than or equal to 40% and less than 100%, also That is, when 40%≦G2/G1<100%, the efficiency of the liquid crystal is significantly improved. When 60%≦G2/G1<100%, the liquid crystal efficiency is better improved; when 80%≦G2/G1<100%, the liquid crystal efficiency is better improved. In addition, the ratio of the depth D of the depression 14U to the thickness of the bottom 14B and the first island 141 and T is greater than or equal to 20% and less than or equal to 80%, that is, when 20%≦D/T≦80 %, the liquid crystal efficiency has been significantly improved. When 40%≦D/T≦80%, the liquid crystal efficiency is better improved; when 60%≦D/T≦80%, the liquid crystal efficiency is better improved. Therefore, in the pixel structure 1 of the present embodiment, it is confirmed that the ratio (G2/G1) and/or When the ratio (D/T) of the depth D of the recess 14U to the thickness and T of the bottom 14B and the first island portion 141 is adjusted within the above range, the liquid crystal efficiency of the liquid crystal panel C can be significantly improved.

Please refer to FIG. 3 to FIG. 6 , and refer to FIG. 1 together. 3 to 6 illustrate schematic diagrams of the method for fabricating the pixel structure in this embodiment. As shown in FIG. 3 , a substrate 10 is provided, and gate lines GL (as shown in FIG. 1 ), data lines DL, active switching elements SW (as shown in FIG. 1 ) and first electrodes 12 are formed on the substrate 10 . Subsequently, a first dielectric layer 14 is sequentially formed on the substrate 10 to cover the gate lines GL (as shown in FIG. 1 ), the data lines DL, the active switching elements SW (as shown in FIG. 1 ) and the first electrodes 12 . Next, the second electrode 16 is formed on the upper surface 14T of the first dielectric layer 14 . After that, a sacrificial pattern 17 , such as a patterned photoresist pattern, is formed on the second electrode 16 , wherein the sacrificial pattern 17 exposes a part of the second electrode 16 . As shown in FIG. 4, the second electrode 16 exposed by the sacrificial pattern 17 is then removed to form a plurality of branch electrodes 16B and at least one edge electrode 16E, and then part of the first dielectric layer exposed by the sacrificial pattern 17 is removed. Layer 14. Since the first dielectric layer 14 exposed by the sacrificial pattern 17 is only partially removed, the first dielectric layer 14 exposed by the sacrificial pattern 17 and not removed will form the bottom 14B, which is covered by the sacrificial pattern 17 and The unremoved first dielectric layer 14 will form the first island portion 141 and the second island portion 142 , and the position of the removed first dielectric layer 14 will form a recess 14U. In this embodiment, the steps of forming the branch electrodes 16B and the edge electrodes 16E and forming the recess 14U can be implemented by using a two-stage etching process. For example, a wet etching process may be performed to etch away the second electrode 16 exposed by the sacrificial pattern 17 to form the branch electrodes 16B and the edge electrodes 16E, and then a dry etching process may be performed to etch away the exposed portion of the sacrificial pattern 17. part of the first dielectric layer 14 to form the recess 14U, but the embodiment is not limited thereto.

As shown in FIG. 5 , part of the second electrode 16 is then removed from the side to reduce the width of each branch electrode 16B and the width of the edge electrode 16E, so that the distance G1 between two adjacent branch electrodes 16B is greater than two The distance G2 between adjacent first island-shaped portions 141 . In this embodiment, the distance G1 is greater than the distance G2, wherein the distance G1 is, for example, 5 micrometers, and the distance G2 is, for example, 2 micrometers to 5 micrometers, but not limited thereto. In this embodiment, the step of laterally removing part of the second electrode 16 can be implemented by using a wet etching process. As shown in FIG. 6 , the sacrificial pattern 17 is finally removed to produce the pixel structure 1 of this embodiment.

In the pixel structure 1 of this embodiment, the recess 14U corresponds to all positions between any two adjacent branch electrodes 16B, that is to say, the length of the recess 14U is substantially equal to the length of the branch electrodes 16B, but the present invention The pixel structure is not limited to the above embodiments. The following will introduce the pixel structures of other embodiments of the present invention in sequence, and in order to compare the differences of the embodiments and simplify the description, the same symbols are used to mark the same elements in the following embodiments, and mainly for each The differences between the embodiments will be described, and the repeated parts will not be repeated.

Please refer to Figure 7 and Figure 8. FIG. 7 is a schematic top view of the pixel structure of the second embodiment of the present invention, and FIG. 8 is a pixel structure of the second embodiment of the present invention drawn along the BB' section line and CC' section line of FIG. 7 The schematic cross-section shown. As shown in Figures 7 and 8, in the pixel structure 2 of this embodiment, the pixel area 10P includes one or more buffer areas 10PB and connection areas 10PC, wherein the connection area 10PC is located between two adjacent buffer areas 10PB , and there is a buffer zone 10PB between two adjacent connection areas 10PC. The first island portion 141 of the first dielectric layer 14 is located in the buffer zone 10PB, and the flat portion 143 of the first dielectric layer 14 is located in the connection area 10PC. The two end portions 16T and the turning portion 16S of each branch electrode 16B are located in the buffer zone 10PB, and the two connection portions 16C are located in the connection area 10PC. To further illustrate, in this embodiment, the first dielectric layer 14 only has the design of the first island portion 141 and the recess 14U in the buffer zone 10PB, and the relative relationship between the first island portion 141, the recess 14U and the branch electrodes 16B Similar to the first embodiment, there is a planar portion 143 in the connection area 10PC without the design of the island portion and the depression. Since the pattern of the terminal portion 16T and the turning portion 16S of the branch electrode 16B of the second electrode 16 is relatively twisted (kink), it will affect the liquid crystal efficiency of the buffer area 10PB, so this embodiment can only be used for the first dielectric layer of the buffer area 10PB. Layer 14 forms the first island portion 141 and the recess 14U, and the first dielectric layer 14 in the connection area 10PC then forms a flat portion 143, thereby the liquid crystal efficiency in the buffer area 10PB can be adjusted, so that the buffer area 10PB and the connection area 10PC has substantially the same liquid crystal efficiency to improve the display uniformity of the pixel structure 2 .

Please refer to Figure 9 and Figure 10. 9 is a schematic top view of the pixel structure of the third embodiment of the present invention, and FIG. 10 is a schematic cross-sectional view of the pixel structure of the third embodiment of the present invention along the line D-D' in FIG. 9 . As shown in FIG. 9 and FIG. 10 , in the pixel structure 3 of this embodiment, the number of the first island-shaped portion 141 is one, and the first island-shaped portion 141 and the second island-shaped portion 142 are located on the bottom 14B to form a structure. Debossed 14U. The sum T of the thicknesses of the bottom 14B of the first dielectric layer 14 and the first island portion 141 is greater than the depth D of the recess 14U. The branch electrode 16B of the second electrode 16 is disposed on the upper surface 14T of the first island portion 141 and partially exposes the upper surface 14T of the first island portion 141 , and the second island portion 142 overlaps the data line DL. In addition, the second electrode 16B further includes an edge electrode 16E disposed on the upper surface 14T of the second island portion 142 . The edge electrode 16E can be electrically connected to the branch electrode 16B, the edge electrode 16E partially exposes the upper surface 14T of the second island portion 142, and the distance G3 between the edge electrode 16E and the adjacent branch electrode 16B is larger than that of the second island portion 142. The distance G4 between the portion 142 and the adjacent first island portion 141 .

As shown in FIG. 10 , since the distance d1 of the first electrode 12 protruding from the branch electrode 16B of the second electrode 16 and the distance d2 of the first electrode 12 and the edge electrode 16E of the second electrode 16 will affect the electric field, the position of The liquid crystal efficiency is affected by the distance d1 between the first electrode 12 and the branch electrode 16B of the second electrode 16 and the distance d2 between the first electrode 12 and the edge electrode 16E of the second electrode 16 . Especially when the pixel per inch (PPI) of the display panel is different, the distance d1 of the first electrode 12 protruding from the branch electrode 16B of the second electrode 16 and the distance d1 between the first electrode 12 and the edge electrode 16E of the second electrode 16 The distance d2 will also be different accordingly. Therefore, in this embodiment, the ratio of the distance G4 between the second island-shaped portion 142 and the adjacent first island-shaped portion 141 and the distance G3 between the edge electrode 16E and the adjacent branch electrode 16B is adjusted to improve the edge The liquid crystal efficiency of the region between the electrode 16E and the branch electrode 16B. In this embodiment, the distance G3 is greater than the distance G4, wherein the distance G3 is, for example, 2 microns to 6 microns, and the distance G4 is, for example, 0.8 microns to 6 microns, and is not limited thereto.

Please refer to Figure 11. FIG. 11 is a schematic diagram of a pixel structure according to a fourth embodiment of the present invention. As shown in FIG. 11 , different from the first embodiment, in the pixel structure 4 of this embodiment, the thickness h1 of the bottom 14B of the first dielectric layer 14 and the thickness of the second island 142 is greater than that of the first dielectric layer 14 The thickness sum h2 of the bottom 14B and the first island-shaped portion 141 of the first dielectric layer 14 is greater than the thickness h3 of the bottom 14B of the first dielectric layer 14 . In this embodiment, the thickness h1 is 0.4 micron to 0.8 micron, the thickness h2 is 0.15 micron to 0.6 micron, and the thickness h3 is 0.03 micron to 0.48 micron, but not limited thereto. That is to say, the distance between the branch electrode 16B of the second electrode 16 and the first electrode 12 is smaller than the distance between the edge electrode 16E of the second electrode 16 and the data line DL. In this way, since the distance between the branch electrode 16B of the second electrode 16 and the first electrode 12 is small, the voltage difference between the first electrode 12 and the second electrode 16 will generate a large liquid crystal electric field, so it can be improved. Liquid crystal efficiency; on the other hand, because the distance between the edge electrode 16E and the data line DL is relatively large, it has a better isolation effect, which can effectively reduce the capacitive load between the edge electrode 16E and the data line DL, and avoid unnecessary Useful for displaying effects.

Please refer to Figure 12 to Figure 14. 12 is a schematic diagram of a pixel structure according to a fifth embodiment of the present invention, FIG. 13 is a schematic cross-sectional view of the first pixel in FIG. 12 along the section line EE', and FIG. The cross-sectional schematic diagram shown by the section line FF'. As shown in FIG. 12 , the pixel P of the pixel structure 5 of this embodiment may include at least one first pixel P1 and at least one second pixel P2 . As shown in FIG. 13 , the first pixel P1 includes a first electrode 12 , a first dielectric layer 14 and a second electrode 16 . The first electrodes 12 are disposed on the substrate 10, and the first electrodes 12 are electrically connected to the corresponding data lines DL. The first dielectric layer 14 is disposed on the first electrode 12, wherein the first dielectric layer 14 has at least one first island portion 141, a bottom 14B and at least one second island portion 142, and the first island portion 141 and the second island portion 142 are located on the bottom 14B to form a plurality of depressions 14U. To be precise, two adjacent first island-shaped portions 141 and the bottom 14B below them form a depression 14U, and the adjacent first island-shaped portions 141 and second island-shaped portions 142 and the bottom 14B below them form a recess 14U. A depression 14U is also formed, wherein the depression 14U has a depth D, and the depth D is, for example, 0.15 μm to 0.8 μm, but not limited thereto. In this embodiment, the first electrode 12 can be a complete planar electrode, which does not include slits or branch electrodes, and the second electrode 16 includes a plurality of branch electrodes 16B and at least one edge electrode 16E, wherein the branch electrodes The electrodes 16B are respectively disposed on the upper surface 14T of the corresponding first island portion 141 , and the edge electrodes 16E are disposed on the upper surface 14T of the second island portion 142 . In this embodiment, the branch electrode 16B may completely cover the upper surface 14T of the first island-shaped portion 141, or partially expose the upper surface 14T of the first island-shaped portion 141; the edge electrode 16E may completely cover the second island-shaped portion. The upper surface 14T of the second island 142 is partially exposed. The first pixel P1 can adopt the methods disclosed in any of the above-mentioned embodiments.

As shown in FIG. 14 , the second pixel P2 includes a substrate 10 , a third electrode 32 , a second dielectric layer 34 and a fourth electrode 36 . The third electrode 32 is disposed on the substrate 10, and the third electrode 32 is electrically connected to the corresponding data line DL. The second dielectric layer 34 is disposed on the third electrode 32 , wherein the second dielectric layer 34 has a flat upper surface 34T without an island portion. The fourth electrode 36 is disposed on the upper surface 34T of the second dielectric layer 34 . In this embodiment, the third electrode 32 can be a complete planar electrode, which does not include slits or branch electrodes, and the fourth electrode 36 includes a plurality of branch electrodes 36B and at least one edge electrode 36E, and the first The two electrodes 36 are electrically connected to a common potential. In this embodiment, the third electrode 32 is a pixel electrode, and the fourth electrode 36 is a common electrode, but not limited thereto. For example, in a variant embodiment, the third electrode 32 may be a common electrode, and the fourth electrode 36 may be a pixel electrode.

In this embodiment, the first pixel P1 and the second pixel P2 are pixels of different colors. In this embodiment, the liquid crystal efficiencies of pixels of different colors can be individually adjusted. For example, the first pixel P1 is a pixel displaying blue, that is, a blue pixel, and the second pixel P2 is not a pixel displaying blue, that is, includes a red pixel and/or a green pixel, for example. In other variant embodiments, the pixel structure may further include more than three types of different pixels, and each of the three types of pixels has recesses of different depths. For example, blue pixels have dimples with greater depth, green pixels have dimples with less depth, and red pixels have dimples with minimal depth or no dimples.

Please refer to Figure 15. FIG. 15 is a schematic top view of a pixel structure according to a sixth embodiment of the present invention. As shown in FIG. 15 , the difference from the previous embodiments is that each branch electrode 16B of the second electrode 16 of the pixel structure 6 in this embodiment only has two terminal portions 16T and a connecting portion 16C, but does not have a turning portion. That is to say, each branch electrode 16B can be substantially a strip structure, and two ends of the connecting portion 16C are respectively connected to the terminal portion 16T. Except that the branch electrode 16B of the pixel structure 6 of this embodiment does not have a turning portion, the other parts can be the same as the previous embodiment, that is, the pixel structure 6 also has a dielectric layer design with unequal thickness, and can have different requirements as follows: The different aspects disclosed in the foregoing embodiments will not be repeated here.

To sum up, the dielectric layer of the pixel structure of the present invention has unequal thickness design, and the distance between adjacent branch electrodes is not equal to the distance between adjacent island-shaped parts, so the distance between the common electrode and the data line can be increased without increasing the distance between the common electrode and the data line. Effectively improve the liquid crystal efficiency under the condition of capacitive load between them.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (18)

1. A pixel structure, comprising: a substrate; A plurality of gate lines and a plurality of data lines are arranged on the substrate; and At least one first pixel is disposed on the substrate and electrically connected to the corresponding gate line and the data line, wherein the at least one first pixel includes: a first electrode disposed on the substrate; a first dielectric layer disposed on the first electrode, wherein the first dielectric layer has at least one first island; and A second electrode is disposed on an upper surface of the at least one first island-shaped portion, and the second electrode partially exposes the upper surface of the first island-shaped portion. 2. The pixel structure according to claim 1, wherein the number of the at least one first island is plural, the first dielectric layer further comprises a bottom and a second island, and the plurality of first islands An island and the second island are located on the bottom to form a plurality of depressions, the second electrode includes a plurality of branch electrodes, wherein the plurality of branch electrodes are respectively arranged on the plurality of first islands on the upper surface of the plurality of first island-shaped portions, respectively partially exposing the upper surface of the corresponding plurality of first island-shaped portions, and the second island-shaped portion overlaps with the corresponding data lines. 3. The pixel structure according to claim 2, wherein the distance between two adjacent branch electrodes is greater than the distance between two adjacent first island-shaped portions. 4. The pixel structure according to claim 3, wherein the ratio of the distance between two adjacent first islands to the distance between two adjacent branch electrodes is greater than or equal to 40% and less than 100%. 5. The pixel structure as claimed in claim 2, wherein the sum of the thicknesses of the bottom and the first island portion is greater than the depth of the recess. 6 . The pixel structure as claimed in claim 5 , wherein a ratio of the depth of the recess to the sum of the thicknesses of the bottom and the first island portion is greater than or equal to 20% and less than or equal to 80%. 7. The pixel structure as claimed in claim 2, wherein each of the branch electrodes has two end portions, a turning portion and two connecting portions, and the two ends of the plurality of connecting portions are connected to the plurality of end points and the turning portion respectively. part connection, the plurality of end points are arranged on the upper surface of the corresponding first island-shaped part, and partially expose the upper surface of the first island-shaped part, and the turning part is arranged on the corresponding first island-shaped part. on the upper surface of the island-shaped portion and partially exposes the upper surface of the first island-shaped portion. 8. The pixel structure according to claim 2, wherein the sum of the thicknesses of the bottom and the first island-shaped portion is greater than the thickness of the bottom, and the sum of the thicknesses of the bottom and the second island-shaped portion is greater than the sum of the thicknesses of the bottom and the second island-shaped portion The thickness of an island and . 9. The pixel structure according to claim 1, wherein the number of the at least one first island is one, the first dielectric layer further comprises a bottom and a second island, the first island and the second island is located on the bottom to form a depression, the second electrode includes a plurality of branch electrodes, wherein the plurality of branch electrodes are arranged on the upper surface of the first island and partially exposed protruding from the upper surface of the first island-shaped portion, and the second island-shaped portion overlaps with the data line. 10. The pixel structure according to claim 9, wherein the second electrode further comprises an edge electrode disposed on an upper surface of the second island portion and partially exposing the upper surface of the second island portion. surface, and the distance between the edge electrode and the adjacent branch electrode is greater than the distance between the second island-shaped portion and the adjacent first island-shaped portion. 11. The pixel structure according to claim 1, wherein the first electrode is electrically connected to the corresponding data line, and the second electrode is electrically connected to a common potential. 12. The pixel structure according to claim 1, further comprising at least one second pixel disposed on the substrate, wherein the at least one second pixel comprises: a third electrode disposed on the substrate; a second dielectric layer disposed on the third electrode, wherein the second dielectric layer does not have an island; and A fourth electrode is disposed on an upper surface of the second dielectric layer. 13. The pixel structure according to claim 12, wherein the at least one first pixel and the at least one second pixel are pixels of different colors. 14. The pixel structure according to claim 13, wherein the at least one first pixel comprises a blue pixel, and the at least one second pixel comprises a red pixel or a green pixel. 15. The pixel structure as claimed in claim 12, wherein the first electrode and the third electrode comprise pixel electrodes, and the second electrode and the fourth electrode comprise a common electrode. 16. A pixel structure comprising: a substrate; A plurality of gate lines and a plurality of data lines are arranged on the substrate; and At least one first pixel is located in a pixel region, the at least one first pixel is disposed on the substrate and electrically connected to the corresponding gate line and the data line, wherein the at least one first pixel includes: a first electrode disposed on the substrate; A first dielectric layer disposed on the first electrode, wherein the first dielectric layer has: a plurality of first island-shaped parts, respectively located in a plurality of buffer areas in the pixel area; and Multiple flat parts are respectively located in multiple connection areas of the pixel area, wherein each of the connection areas is located between two adjacent buffer areas; and A second electrode, including a plurality of branch electrodes disposed on the first dielectric layer, wherein each branch electrode has: Two end points are respectively arranged in the plurality of buffer zones; a turning portion, disposed in the buffer zone; and Two connection parts are respectively arranged on an upper surface of the at least one first island-shaped part and are respectively located in the plurality of connection areas, wherein both ends of each connection part are respectively connected to the end point part and the turning part . 17. A pixel structure comprising: a substrate; A plurality of gate lines and a plurality of data lines are arranged on the substrate; At least one first pixel is disposed on the substrate and electrically connected to the corresponding gate line and the data line, wherein the at least one first pixel includes: a first electrode disposed on the substrate; a first dielectric layer disposed on the first electrode, wherein the first dielectric layer has at least one first island; and a second electrode disposed on an upper surface of the at least one first island; and At least one second pixel is disposed on the substrate, wherein the at least one second pixel includes: a third electrode disposed on the substrate; a second dielectric layer disposed on the third electrode, wherein the second dielectric layer does not have an island; and A fourth electrode is disposed on an upper surface of the second dielectric layer. 18. The pixel structure according to claim 17, wherein the first pixel is a blue pixel, and the second pixel is not a blue pixel.

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