CN103856191A - CMOS delay circuit and method for restraining temperature drift of the CMOS delay circuit - Google Patents

Abstract

The invention provides a CMOS delay circuit and a method for restraining temperature drift of the CMOS delay circuit. Due to the fact that a delay unit is added between every two adjacent CMOS phase inverters connected in series, the temperature drift of the CMOS delay circuit can be effectively controlled within the ideal range, and the requirement, possibly existing in the actual circuit design, for high precision of the temperature drift is met.

Description

The method that CMOS delay circuit and inhibition CMOS delay circuit temperature are floated

Technical field

The embodiments of the present invention relate to electronic circuit, and relate more specifically to a kind of CMOS delay circuit and suppress the method that CMOS delay circuit temperature is floated.

Background technology

In electronic circuitry design, often to use CMOS inverter.As known to those skilled, for CMOS inverter, the lag characteristic of CMOS inverter is subject to the impact of the various operating conditions such as technique, voltage, temperature (being PVT).What Fig. 1 showed prior art is composed in series the schematic diagram of delay cell by CMOS inverter.As shown in the dotted line amplifier section in Fig. 1, conventional CMOS inverter is made up of two metal-oxide-semiconductor field effect transistors conventionally, and wherein PM1 is PMOS pipe, and NM1 is NMOS pipe.The grid source threshold voltage of NMOS pipe be on the occasion of, the grid source threshold voltage of PMOS pipe is negative value.

The carrier mobility μ of MOSFET can be represented by formula (1):

$\mathrm{\μ}\left(T\right)=\mathrm{\μ}\left(T_0\right)\×{\left[\frac{T_0}{T}\right]}^{3/2}---\left(1\right)$

Wherein T ₀for room temperature, T is actual Kelvin; μ refers to carrier mobility;

For MOSFET, its threshold voltage vt h can be represented by formula (2) with the relation of temperature:

$\mathrm{Vth}\left(T\right)=\mathrm{Vth}\left(T_0\right)-\∂(T-T_0)---\left(2\right)$

Wherein there is T ₀=300K,

vth is the threshold voltage of MOSFET.

The conducting resistance R of MOSFET _onbe expressed from the next:

$\mathrm{Ron}=\frac{1}{{\mathrm{\μC}}_{\mathrm{OX}}\frac{W}{L}\left|(V_{\mathrm{GS}}-V_{\mathrm{th}})\right|}---\left(3\right)$

Wherein, R _onfor the conducting resistance of MOSFET, V _gSfor gate source voltage, the breadth length ratio that W/L is metal-oxide-semiconductor, C _oXfor the coefficient of gate capacitance.

When for example in phase-locked loop or oscillator etc., the circuit of the N being cascaded a CMOS inverter will produce time delay, corresponding time delay

can be represented by formula (4):

$T_{\mathrm{delay}\left(\mathrm{INV}\right)}\≈N\×R_{\mathrm{out}}\×(C_{\mathrm{out}}+C_{\mathrm{in}})---\left(4\right)$

Wherein, R _outrepresent the output resistance of inverter, C _outrepresent the output capacitance of CMOS inverter at the corresponding levels, C _inthe input capacitance that represents next stage inverter, N=2n represents the number of inverter.Conventionally, the NMOS pipe in CMOS inverter and PMOS pipe be another pipe cut-off of pipe conducting always, therefore, and R _outcan equal haply above-mentioned conducting resistance.

From formula (1)-(4) above, for the sequence circuit of N CMOS inverter series connection, corresponding time delay

to increase along with the rising of temperature, and reduce along with the decline of temperature.That is to say, under the impact of said temperature, the time delay of above-mentioned CMOS inverter may produce temperature and float, and can change within a large range; And if in the situation that PVT operating mode all changes, situation may be worse.Especially, for requiring accurately to control in the circuit application of time delay, this is that those skilled in the art institute is less desirable.

Therefore, need now a kind ofly can suppress CMOS delay circuit and the method that temperature is floated.

Summary of the invention

One object of the present invention is at least to solve the temperature that in prior art, CMOS delay circuit exists and floats problem.According to CMOS delay circuit of the present invention with suppress the method that CMOS delay circuit temperature is floated, within can effectively the temperature of CMOS delay circuit being floated and being controlled at ideal range, thereby meet the high-precision requirement that temperature is floated that may exist in side circuit design.

According to an aspect of the present invention, provide a kind of CMOS delay circuit, having comprised: delay cell, be configured between the CMOS inverter of at least two series connection, the temperature delay characteristic of described delay cell is contrary with the temperature delay characteristic of described CMOS inverter.

According to one embodiment of present invention, described delay cell comprises a RC circuit, and described RC circuit comprises a resistance R and a capacitor C, and described resistance R is connected between described two CMOS inverters, one end of described capacitor C is connected with one end of described resistance R, other end ground connection.

According to one embodiment of present invention, described resistance R is the resistance that is negative temperature coefficient.

According to one embodiment of present invention, described resistance is P type polysilicon resistance.

According to one embodiment of present invention, one or more delay cell is configured between the CMOS inverter of any two adjacent and series connection.

According to a further aspect in the invention, a kind of method that also provides the CMOS of inhibition delay circuit temperature to float, it is characterized in that: between the CMOS of at least two series connection inverter, arrange delay cell, the temperature delay characteristic of described delay cell is contrary with the temperature delay characteristic of described CMOS inverter.

According to one embodiment of present invention, described delay cell comprises a RC circuit, and described RC circuit comprises a resistance R and a capacitor C, and described resistance R is connected between described two CMOS inverters, one end of described capacitor C is connected with one end of described resistance R, other end ground connection.

According to one embodiment of present invention, described resistance R is the resistance that is negative temperature coefficient.

According to one embodiment of present invention, described resistance is P type polysilicon resistance.

According to one embodiment of present invention, any two adjacent and series connection CMOS inverter between configure one or more delay cell.

Brief description of the drawings

In the time reading by reference to the accompanying drawings below to the detailed description of exemplary embodiment, these and other object, feature and advantage will become apparent, in the accompanying drawings:

Fig. 1 shows the schematic diagram of the CMOS inverter delay circuit of prior art;

Fig. 2 shows according to the schematic diagram of the improved CMOS delay circuit of various embodiments of the present invention; And

Fig. 3 shows the schematic diagram of the CMOS delay circuit that comprises according to the preferred embodiment of the invention RC circuit.

Embodiment

Fig. 2 shows according to the schematic diagram of the improved CMOS delay circuit of various embodiments of the present invention.This delay circuit comprises the CMOS inverter 210 of N series connection, and wherein N can equal 2n.In an example, this delay circuit also comprises the delay cell 220 between two CMOS inverters that are arranged in arbitrary neighborhood and series connection.This delay cell 220 is the temperature delay characteristic contrary with described CMOS inverter 210.As previously discussed, the temperature delay characteristic of the CMOS inverter 210 of existing N series connection is the rising along with temperature, and postponing increases, and is positive temperature delay characteristic.And delay cell 220 in this example of the present invention is negative temperature lag characteristic, along with the rising of temperature, the latency reduction of delay cell 220.

Be appreciated that and for example improve total delay of delay circuit or time delay, by not only depending on the delay (being determined by process corner, temperature and/or the supply voltage of metal-oxide-semiconductor) of series connection CMOS inverter itself, also depend on the delay of delay cell 220.And because delay cell 220 and CMOS inverter 210 are contrary temperature delay characteristic, delay cell 220 is floated the temperature of compensation CMOS inverter 210, thereby the temperature that suppresses whole delay circuit is floated.It will be understood by those skilled in the art that the delay cell that can implement arbitrary structures, form or quantity, within it all drops on protection scope of the present invention.

Fig. 3 shows the CMOS delay circuit that comprises according to the preferred embodiment of the invention RC circuit.This delay circuit comprises N CMOS inverter 210 and is arranged in the delay cell 220 between any two CMOS inverters of series connection, and wherein N can equal 2n.This delay cell 220 comprises RC circuit.Resistance R is connected in series between two CMOS inverters, capacitor C one end contact resistance R, other end ground connection.R is negative temperature coefficient resister.

The delay or the time delay that comprise the CMOS delay circuit of RC circuit can be illustrated by formula (5):

T _delay(new)＝T _delay(INV)+T _delay(RC) (5)

Wherein, Td _{elay (RC)}≈ R*C.

Described negative temperature coefficient resister R is along with the rising of temperature, and charge carrier number increases, and resistance value reduces; Otherwise along with the reduction of temperature, charge carrier number reduces, resistance value increases.Thus, RC circuit is negative temperature lag characteristic.And T _{delay (INV)}be as previously mentioned positive temperature delay characteristic, therefore in the time that the RC circuit that is negative temperature lag characteristic is cascaded with the CMOS inverter that is positive temperature delay characteristic, RC circuit compensation the temperature of series connection CMOS inverter float, effectively suppressed the temperature drift of whole delay circuit.RC circuit is the preferred embodiment of delay cell, and in addition because RC circuit structure is simple, its favourable part is and is unlikely the complexity that increases original delay circuit.

The preferred embodiment according to the present invention, the resistance R in RC circuit is P type polysilicon resistance, and the resistance value of this P type polysilicon resistance is along with temperature rise, and resistance value reduces.Table 1 shows the resistance-temperature characteristic of P type polysilicon resistance.

Table 1

Temperature DEG C	Resistance (K Ω)
		-40	14.1
-20	13.23
		-10	12.83
20	11.72
		40	11.07
80	9.97
		120	9.17
160	8.87

From table 1, this P type polysilicon resistance is negative temperature characteristic, and the RC circuit of its formation also will be negative temperature lag characteristic, thereby is contrary temperature delay characteristic with CMOS inverter, realizes the compensation that CMOS inverter temperature is floated.

Can accurately design each parameter in delay cell (such as RC circuit), float with the temperature of compensation CMOS inverter substantially.

Following table 2 shows and designs an example with the delay circuit of the present invention of 30ns time delay and the comparison of existing delay circuit.This table 2 is that these two delay circuits are tested under identical PVT (technique, temperature and voltage) operating mode, wherein each self-test the time delay of these two delay circuits under condition of different temperatures the temperature of having calculated them float delay scope.It should be appreciated by those skilled in the art that this table 2 does not form any restriction to the scope of the invention.

Table 2

As seen from the above table, the temperature of existing delay circuit is floated delay scope can approach 40%, than existing delay circuit, delay circuit of the present invention temperature can be floated delay scope be for example effectively controlled at ± 10%, within even less ideal range.Thus, the advantage that the temperature that delay circuit according to the present invention is realized is floated delay scope is apparent.

In practice, those skilled in the art can float the process corner parameter of the continuous feedback adjusting of number range such as CMOS according to the temperature of reality test, and/or the resistance of RC circuit and/or the parameter value of electric capacity, thereby make delay cell such as RC circuit substantially the temperature of compensation CMOS inverter float, to meet the high-precision requirement of in practical application, temperature being floated scope.

According to various embodiments of the present invention, improved delay circuit is applicable to the temperature range of high temperature or low temperature.Can be applied to a variety of IC circuit, for example, in Switching Power Supply, phase-locked loop (PLL) and/or oscillator (OSC).

A kind of method that the present invention also provides the CMOS of inhibition delay circuit temperature to float, any two adjacent and series connection CMOS inverter between arrange delay cell, described delay cell is contrary with the temperature delay characteristic of described CMOS inverter.This delay cell can be RC circuit.Resistance R in this RC circuit is the resistance that is negative temperature coefficient.The resistance of this negative temperature coefficient can be P type polysilicon resistance.It will be understood by those skilled in the art that and can as required one or more delay cell be arranged between the CMOS inverter of any two series connection.For example, can between every two CMOS inverters, arrange one or more delay cell.

According to embodiments of the invention, can test according to reality the quantity of the delay cell of arranging between two CMOS inverters of effect selection, and/or adjust the value of the parameter in delay cell (in RC circuit).

Although described and illustrated embodiments of the invention here, those of ordinary skill in the art by easy imagination for carrying out function described herein and/or obtaining various other means of one or more advantage of result described herein and/or advantage described herein and/or structure and each such variation and/or amendment are considered as in the scope of inventive embodiments described here.More generally, the person skilled in the art will easily understand all parameters described herein, yardstick, material and configuration be for for example and actual parameter, yardstick, material and/or configuration will depend on the present invention's instruction and be applied to one of them or multiple concrete application.

Those skilled in the art are by understanding or can only establish the many equivalent embodiment of concrete inventive embodiments described herein with routine experiment.Therefore only present understand in previous embodiment by example and in the scope of appended claims and equivalents thereof, can use except specifically describe and claimed mode mode realize inventive embodiments.The inventive embodiments of present disclosure relates to each indivedual features described herein, system, product, material, kit and/or method.In addition, if two or more such feature, system, product, material, kit and/or method are not internally inconsistent, in the invention scope of present disclosure, comprise any combination of such feature, system, product, material, kit and/or method.

As all definition that define here and use should be understood to arrange dictionary definition, its ordinary meaning at the term of the definition by reference and in the document of combination and/or definition.

As the indefinite article using in specification and in claims here "/one " unless clearly indicated on the contrary and should be understood to mean " at least one/one ".As the phrase " at least one " using in specification and in claims here should be understood to mean when the list of quoting one or more key element at least one key element of selecting in any one or the multiple key element in the key element from key element is enumerated, but any combination that may not be included at least one key element in the key element one by one of specifically enumerating in key element list and not get rid of the key element in key element list.This definition also allow to exist alternatively in the key element list except quoting at phrase " at least one " the key element of concrete mark, no matter be with those key elements of concrete mark about or irrelevant key element.Therefore, as unrestricted example, " at least one in A and B " (or be equivalent to " at least one in A or B " or be equivalent to " at least one in A and/or B ") can refer in one embodiment at least one A, comprise multiple A and have (and comprising alternatively the key element except B) without B alternatively; Refer in another embodiment at least one B, comprise multiple B and have (and comprising alternatively the key element except A) without A alternatively; Refer in another embodiment at least one A, comprise multiple A and at least one B alternatively, comprise multiple B (and comprising alternatively other key element) alternatively; Etc..

Unless also should be appreciated that clearly instruction on the contrary, here, in the claimed any method that comprises multiple steps or action, the step of method or the order of action may not be limited to the step of record method or the order of action.In addition, any label occurring between the bracket in claims or other symbol only limit by any way in order conveniently to provide and not to be intended to.

Claims (10)

1. a CMOS delay circuit, comprising:

Delay cell, is configured between the CMOS inverter of at least two series connection, and the temperature delay characteristic of described delay cell is contrary with the temperature delay characteristic of described CMOS inverter.

2. circuit according to claim 1, wherein said delay cell comprises a RC circuit, and described RC circuit comprises a resistance R and a capacitor C, and described resistance R is connected between described two CMOS inverters, one end of described capacitor C is connected with one end of described resistance R, other end ground connection.

3. circuit according to claim 2, wherein said resistance R is the resistance that is negative temperature coefficient.

4. circuit according to claim 3, wherein said resistance is P type polysilicon resistance.

5. according to the circuit described in any one in claim 1 to 4, wherein one or more delay cells are configured between the CMOS inverter of any two adjacent and series connection.

6. suppress the method that CMOS delay circuit temperature is floated, comprising:

Between the CMOS of at least two series connection inverter, arrange delay cell, the temperature delay characteristic of described delay cell is contrary with the temperature delay characteristic of described CMOS inverter.

7. method according to claim 6, wherein said delay cell comprises a RC circuit, and described RC circuit comprises a resistance R and a capacitor C, and described resistance R is connected between described two CMOS inverters, one end of described capacitor C is connected with one end of described resistance R, other end ground connection.

8. method according to claim 7, wherein said resistance R is the resistance that is negative temperature coefficient.

9. method according to claim 8, wherein said resistance is P type polysilicon resistance.

10. circuit according to claim 6, wherein any two adjacent and series connection CMOS inverter between configure one or more delay cell.

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