CN103855092B - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
- Publication number
- CN103855092B CN103855092B CN201210497474.2A CN201210497474A CN103855092B CN 103855092 B CN103855092 B CN 103855092B CN 201210497474 A CN201210497474 A CN 201210497474A CN 103855092 B CN103855092 B CN 103855092B
- Authority
- CN
- China
- Prior art keywords
- tensile stress
- layer
- silicon nitride
- dummy gate
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0172—Manufacturing their gate conductors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0181—Manufacturing their gate insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a stress semiconductor manufacturing method. In the method, the tensile stress layer processed by the nitrogen plasma is formed in the NMOS area, and the corrosion rate of the tensile stress silicon nitride processed by the nitrogen plasma in the DHF is greatly reduced compared with that of the tensile stress silicon nitride which is not processed, so that only a small part of the tensile stress silicon nitride in the NMOS area is corroded and removed in the subsequent dummy gate removing process, and most of the tensile stress silicon nitride is preserved, sufficient stress can be provided for a channel, and the possibly adverse effect on a device structure in the subsequent step is avoided, so that the completeness of the device structure is ensured, and the process integration of the back gate process and the double-strain stress layer is realized.
Description
Technical field
The present invention relates to method, semi-conductor device manufacturing method fields, particularly, are related to a kind of applied to grid technique after CMOS
The integrated approach of double strain stress layers.
Background technology
Semiconductor integrated circuit technology maintains or improves transistor after the technology node for entering 90nm characteristic sizes
It can be more and more challenging.After 90nm nodes, stress technique is gradually used to improve the performance of device.Concurrently,
In terms of manufacturing process, the high-K metal gate technology in rear grid technique (gate last) is also gradually used to cope with device
The challenge for constantly reducing and bringing.In stress technique, double strain stress layer (DSL, dual stressliner) technologies with often
It is relatively low to advise processing compatibility height, cost, therefore, is used by major semiconductor manufacturer.
DSL technologies refer to that, in different types of MOSFET region, formation is respectively provided with tensile stress and the stress of compression
Layer forms compressive stress layer in general, forming tensile stress layer in NMOS area in PMOS area.Referring to attached drawing 1, figure is to use DSL
A step in the CMOS manufacturing process of technology.Wherein, on substrate 1, NMOS 2 and PMOS3, different MOS crystal are formed with
Pipe is kept apart by sti structure 4.NMOS 2 includes NMOS dummy gate electrodes 6 and its dummy gate electrode insulating layer 5, and PMOS 3 includes PMOS
Dummy gate electrode 8 and its dummy gate electrode insulating layer 7, dummy gate electrode (dummy gate) and its dummy gate electrode insulating layer are used for rear grid
Technique, dummy gate electrode are usually polysilicon or non-crystalline silicon grid, and dummy gate electrode insulating layer is usually silicon oxide layer, complete crystal
After pipe other component, dummy gate electrode and its dummy gate electrode insulating layer are removed, forms gate recess, then the shape in gate recess
At high K gate insulation layers and metal gates.It is covered with tensile stress layer 9 on NMOS 2, compressive stress layer 10 is covered on PMOS 3,
Stress layer material is usually silicon nitride.Both stressor layers provide stress to the channel region of NMOS and PMOS respectively, to increase
The mobility of channel region carrier, performance of the guarantee transistor in deep-submicron field.Then, in later steps, join
See attached drawing 2, needs to carry out CMP process, planarize device architecture, open dummy gate electrode.In order to avoid CMP opens dummy gate electrode top
May occur recessed dish (dish) phenomenon when portion's hard mask above source-drain area (if there is recessed dish phenomenon, subsequent deposition high-K metal
Grid and CMP will cause high-K metal gate to remain in recessed dish, to cause device electric property unstable), in device spacing
When larger, step CMP can be made to be performed until polish stop layer, namely be covered in the tensile stress layer right over source and drain areas
9 and compressive stress layer 10 upper surface, referring to the situation in attached drawing 2；When device spacing is smaller, need to deposit one in stressor layers
The TEOS (not shown) for determining thickness, then carries out CMP.In this way, just exposing dummy gate electrode, dummy gate electrode can be successively removed
And its dummy gate electrode insulating layer, form gate recess.Dummy gate electrode insulating layer is usually silica, and removing method is DHF wet methods
Corrosion, specifically, at room temperature (23 degrees Celsius), the rate of 1: 100 DHF corrosion oxidation silicon is 30 ± 1 angstrom mins, but
It is that at the same time, tensile stress silicon nitride corrosion rate in the DHF of this condition is 498 angstrom mins, much larger than silica in DHF
In corrosion rate, therefore, when removing illusory gate insulation layer, tensile stress silicon nitride can also be removed part even it is complete
Portion, referring to attached drawing 3, tensile stress layer 9 is largely consumed in figure, and compressive stress layer 10 is since corrosion rate is very low, in this respect
It is 19 angstrom mins down, loss is seldom.Thus, since stressor layers are lost, result in the integrated failures of DSL.In addition, on device
Deposition has the situation of TEOS, although the TEOS being covered in after CMP in stressor layers can protect stressor layers to avoid corroding, due to
Corrosion rates of the TEOS in DHF is also relatively high, and during removing dummy gate electrode insulating layer, TEOS exists complete by DHF
The danger eroded can thus be such that following tensile stress silicon nitride is exposed in the environment of DHF to cause tensile stress to nitrogenize
The case where silicon is corroded.
Accordingly, it is desirable to provide a kind of new integrated approach applied to double strain stress layers of grid technique after CMOS, it can
Drawbacks described above is overcome, while so that stressor layers is provided enough stress, it is ensured that device architecture it is complete.
Invention content
The present invention provides a kind of manufacturing method of transistor, using nitrogen plasma treatment tensile stress layer, avoids existing
The defect that tensile stress layer loses in technology.
According to an aspect of the present invention, the present invention provides a kind of method, semi-conductor device manufacturing method comprising following steps：
Semiconductor substrate is provided, forms sti structure in the semiconductor substrate, and carry out well region injection, forms NMOS area
Domain and PMOS area；
NMOS transistor and PMOS transistor are formed, the NMOS transistor and the PMOS transistor include dummy gate electrode
With dummy gate electrode insulating layer；
Tensile stress layer is deposited on the NMOS transistor, the tensile stress layer is by nitrogen plasma treatment
Stressor layers；
Compressive stress layer is deposited on the PMOS transistor；
Comprehensive metallization medium layer；
CMP process is carried out, exposes the upper surface of the dummy gate electrode, and on the tensile stress layer and the compressive stress layer
Dielectric layer described in square member-retaining portion；
The dummy gate electrode and the dummy gate electrode insulating layer are removed successively, form gate recess；
In the gate recess, it is respectively formed the NMOS transistor and the high K gate insulation layers of the PMOS transistor
And metal gates.
In the method for the invention, it forms NMOS transistor and PMOS transistor specifically includes：
Form the dummy gate electrode and the dummy gate electrode insulating layer；
Form grid gap wall；
Form the source and drain areas of transistor.
In the method for the invention, tensile stress layer is deposited on the NMOS transistor to specifically include：
Deposition step：The comprehensive certain thickness tensile stress silicon nitride film of deposition；
Processing step：After each deposition step, nitrogenized using the tensile stress that nitrogen plasma treatment deposits
Silicon fiml；
Repeat the deposition step and processing step, until obtaining the tensile stress silicon nitride film of expectation thickness；
The tensile stress silicon nitride film with expectation thickness is patterned, to obtain the tensile stress layer.Wherein, described heavy
In product step, being deposited using pecvd process, the thickness of the certain thickness tensile stress silicon nitride film is 10-1000 angstroms,
Preferably 30 angstroms；Nitrogen plasma treatment in the processing step uses N2Plasma.
In the method for the invention, compressive stress layer is deposited on the PMOS transistor to specifically include：
Deposited overall compression silicon nitride film is located at the protection of patterned photoresist layer described in the PMOS transistor
Then compression silicon nitride film, removal remove photoresist layer positioned at the compression silicon nitride film of the NMOS transistor.
In the method for the invention, the dielectric layer is TEOS layers.
The advantage of the invention is that：In the method for the invention, it is formed by nitrogen plasma treatment in NMOS area
Tensile stress layer, due to more untreated of corrosion rate of the tensile stress silicon nitride in DHF Jing Guo nitrogen plasma treatment
Stress silicon nitride substantially reduces, in this way, in dummy gate electrode removal technique later, the tensile stress silicon nitride of NMOS area only has
Fraction is corroded removal, and it is most of preserved, enough stress can be provided to raceway groove, and avoid subsequent step
The harmful effect that middle device architecture may be subject to realizes rear grid technique and double strains to ensure that the complete of device architecture
The technique of stressor layers is integrated.
Description of the drawings
The integrated approach of the double strain stress layers of grid technique after Fig. 1-3 is existing；
The integrated approach of the double strain stress layers of the rear grid technique of Fig. 4-8 present invention.
Specific implementation mode
Hereinafter, describing the present invention by specific embodiment shown in the accompanying drawings.However, it should be understood that these descriptions are
Illustratively, it is not intended to limit the scope of the present invention.In addition, in the following description, it is omitted to known features and technology
Description, so as not to unnecessarily obscure the concept of the present invention.
The present invention provides a kind of method, semi-conductor device manufacturing method, it is particularly a kind of after the double strain stress layers of grid technique
Method, semi-conductor device manufacturing method provided by the invention will be described in detail referring to attached drawing 4-8 in integrated approach.
First, referring to attached drawing 4, on semiconductor substrate 1, it is formed with NMOS 2 and PMOS3, different MOS transistors are by STI
Structure 4 is kept apart.Wherein, monocrystalline substrate is used in the present embodiment, optionally, germanium substrate can also be used or other are suitable
Semiconductor substrate.The method for forming sti structure 4 on semiconductor substrate 1 specifically includes, and applies on semiconductor substrate 1 first
Cloth photoresist then makes 4 figure of sti structure by lithography, and carries out anisotropic etching to semiconductor substrate 1 and obtain shallow trench,
The filled dielectric material in the shallow trench, such as SiO2, to form sti structure.After forming sti structure 4, well region note is carried out
Enter and (be not shown), forms NMOS area and PMOS area.The well region implanted dopant of PMOS is N-type impurity, and NMOS
Well region implanted dopant is p type impurity.
Then, NMOS dummy gate electrodes 6 are formed and its dummy gate electrode insulating layer 5, PMOS dummy gate electrodes 8 and its dummy gate electrode is exhausted
Edge layer 7.It specifically includes：First one layer of dummy gate electrode insulating layer material, e.g. SiO are deposited on 1 surface of substrate2, thickness is preferred
For 0.5-10nm, depositing operation is, for example, CVD.Later, dummy gate electrode material, after the present invention in grid technique, illusory grid are deposited
Pole material is, for example, polysilicon or non-crystalline silicon.In addition, being also formed with hard mask layer (not shown) on dummy gate electrode material layer.So
Afterwards, photoresist coating is carried out, photoetching defines dummy gate electrode figure, to dummy gate electrode material and dummy gate electrode insulating layer material
Material sequence etches, to be formed simultaneously the dummy gate electrode and its dummy gate electrode insulating layer of NMOS and PMOS.Dummy gate electrode (dummy
Gate) and its dummy gate electrode insulating layer is used for rear grid technique, after completing transistor other component, remove dummy gate electrode and
Its dummy gate electrode insulating layer forms gate recess, then forms high K gate insulation layers and metal gates in gate recess.
After forming dummy gate electrode lines, grid gap wall is formed, by the way of depositing and being etched back to.Later, difference shape
At the source and drain areas of NMOS and PMOS, the mode of ion implanting may be used, can also be carried out first by mask of dummy gate electrode
Self aligned source and drain areas etching, forms source and drain areas groove, source and drain areas epitaxial growth is then carried out, to form transistor
Source and drain areas.
Later, tensile stress layer 9 is deposited on NMOS 2, which is the tensile stress by nitrogen plasma treatment
Layer.It specifically includes deposition step and processing step repeatedly, and deposition step is：The certain thickness tensile stress of deposited overall
Silicon nitride film is deposited optionally with pecvd process, and thickness is 10-1000 angstroms, preferably 30 angstroms；Processing step is：?
After each deposition step, the tensile stress silicon nitride film deposited using nitrogen plasma treatment, optionally with N2Deng
Gas ions.Repeat deposition step and processing step, until obtaining the tensile stress silicon nitride film of expectation thickness.Common opening is answered
Power silicon nitride refers here to the tensile stress silicon nitride without nitrogen plasma treatment, and corrosion rate is in 1: 100 DHF
498 angstrom mins, 30 ± 1 angstrom min of corrosion rate being far longer than under silica above-mentioned condition, still, inventors noted that
By the tensile stress silicon nitride film of plasma pretreatment, corrosion rate is 79 angstrom mins in 1: 100 DHF, compared to without place
The corrosion rate of the tensile stress silicon nitride of reason substantially reduces, and has approached the corrosion rate of silica.On this basis, it invents
People is found that in the removal technique of subsequent dummy gate electrode and (uses DHF), by the tensile stress silicon nitride of plasma pretreatment
Film is only partly corroded, and has no adverse effects to the formation of subsequent device structure.Pass through nitrogen in comprehensive formation expectation thickness
After the tensile stress silicon nitride film of corona treatment, using the tensile stress nitrogen in 2 regions patterned photoresist layer protection NMOS
SiClx film, the tensile stress silicon nitride film in 3 regions removal PMOS, then removes photoresist layer, to obtain by nitrogen plasma
The tensile stress layer 9 of processing.
Then, compressive stress layer 10 is deposited on PMOS 3.It specifically includes：Deposited overall compression silicon nitride film first,
Then with the compression silicon nitride film in 3 regions patterned photoresist layer protection PMOS, the compression nitrogen in 2 regions removal NMOS
SiClx film, then removes photoresist layer.
Both the above stressor layers provide stress to the channel region of NMOS and PMOS respectively, to increase channel region carrier
Mobility, ensure transistor deep-submicron field performance.
Simultaneously, it should be noted that the formation priority of tensile stress layer 9 and compressive stress layer 10 Jing Guo nitrogen plasma treatment
Sequence can be exchanged according to technique concrete condition.
Then, referring to attached drawing 5, comprehensive metallization medium layer 11, specific material is TEOS, and thickness is, for example, 200-
1500nm.Dielectric layer 11 is completely covered on the tensile stress layer 9 by nitrogen plasma treatment and compressive stress layer 10.
Later, CMP process is carried out, device architecture is planarized, opens dummy gate electrode upper surface, and by nitrogen plasma
The tensile stress layer 9 of processing and 10 top member-retaining portion dielectric layer 11 of compressive stress layer, referring to attached drawing 6.Since there are remaining media
The major part of layer 11, tensile stress layer 9 and compressive stress layer 10 is entirely covered, 9 He of tensile stress layer only at grid gap wall
10 part of compressive stress layer exposes, referring to position shown in the virtual coil in attached drawing 6.
Then, referring to attached drawing 7, dummy gate electrode and dummy gate electrode insulating layer are removed successively, form gate recess 12.Specific packet
It includes：First remove dummy gate electrode 6 and 8；Then, removal dummy gate electrode insulating layer 5 and 7, removing method is DHF wet etchings.Due to
Remaining dielectric layer 11 covers most tensile stress layer 9 and compressive stress layer 10, only close to the fraction of grid gap wall
Tensile stress layer 9 and compressive stress layer 10 expose, simultaneously, it is contemplated that and DHF is very small to the corrosion rate of compression silicon nitride, thus
The lateral encroaching meeting very little being open shown in two virtual coils in 3 regions PMOS in attached drawing 6, does not show in the figure 7, and passes through
The tensile stress layer 9 of nitrogen plasma treatment, the corrosion rate in DHF also substantially subtract compared to common tensile stress silicon nitride film
Small, therefore, in the step of removing dummy gate electrode, tensile stress layer 9 is only partly removed, referring to the virtual coil in attached drawing 7, this
The etching extent of sample, tensile stress 9 can be controlled in the range of expectation, it is entirely avoided tensile stress layer 9 is complete in this step
The risk eroded entirely, most tensile stress layer 9 are preserved, and enough stress can be provided to raceway groove, meanwhile, this also keeps away
The generation of recessed dish (dish) phenomenon is exempted from so that in subsequent step, device architecture will not be adversely affected, and ensure that device junction
Structure it is complete.It should be pointed out that the interface of the tensile stress layer 9 in Fig. 7 indicated by virtual coil is only to illustrate, indicate by nitrogen etc.
The tensile stress layer 9 of gas ions processing is only corroded on a small quantity, and imprecise its particular number being corroded that shows.
Later, the high K gate insulation layers 13 and metal gates 14 of NMOS 2 are respectively formed in gate recess 12, PMOS's 3
High K gate insulation layers 15 and metal gates 16, and remaining dielectric layer 11 is removed, referring to attached drawing 8.High K gate insulation layers 13 and high K grid
Insulating layer 15 is selected from one or more layers of one or a combination set of following material composition：Al2O3, HfO2, including HfSiOx、HfSiON、
HfAlOx、HfTaOx、HfLaOx、HfAlSiOxAnd HfLaSiOxAt least one including hafnium base high K dielectric material, including
ZrO2、La2O3、LaAlO3、TiO2Or Y2O3At least one including rare-earth-based high K dielectric material.High K gate insulation layers 13 and high K
The thickness of gate insulation layer 15 is 0.5-100nm, and preferably 1-10nm, depositing operation is, for example, CVD.Metal gates 14 and metal gate
The material of pole 16 is metal or metallic compound, such as TiN, TaN, W.The grid and high-K gate insulating layer of NMOS and PMOS
Formation sequence can exchange according to demand.
In this way, high-K metal gate manufacture is completed, the rear grid technique and double strain stress layers for realizing the present invention integrate work
Skill can carry out the preparation of interlayer dielectric layer and interconnection line later.
So far, the present invention proposes and is described in detail the semiconductor devices manufacture that rear grid technique and double strain stress layers integrate
Method.In the method for the invention, the tensile stress layer Jing Guo nitrogen plasma treatment is formed in NMOS area, due to by nitrogen etc.
Corrosion rate more untreated tensile stress silicon nitride of the tensile stress silicon nitride of gas ions processing in DHF substantially reduces, this
Sample, in dummy gate electrode removal technique later, the tensile stress silicon nitride of NMOS area only has fraction and is corroded removal, and big
Part is preserved, and enough stress can be provided to raceway groove, and avoid what device architecture in subsequent step may be subject to
Harmful effect, to ensure that the complete of device architecture, the technique for realizing rear grid technique and double strain stress layers is integrated.
The present invention is described above by reference to the embodiment of the present invention.But these embodiments are used for the purpose of saying
Bright purpose, and be not intended to limit the scope of the invention.The scope of the present invention is limited by appended claims and its equivalent.
The scope of the present invention is not departed from, those skilled in the art can make a variety of substitutions and modifications, these substitutions and modifications should all be fallen
Within the scope of the present invention.
Claims (6)
1. a kind of method, semi-conductor device manufacturing method, it is characterised in that include the following steps：
There is provided semiconductor substrate, sti structure is formed in the semiconductor substrate, and carry out well region injection, formed NMOS area and
PMOS area；
NMOS transistor and PMOS transistor are formed, the NMOS transistor and the PMOS transistor include dummy gate electrode and void
If gate insulating layer；
Tensile stress layer is deposited on the NMOS transistor, the tensile stress layer is the tensile stress by nitrogen plasma treatment
Layer；Tensile stress layer is deposited on the NMOS transistor to specifically include：
Deposition step：The comprehensive certain thickness tensile stress silicon nitride film of deposition；
Processing step：After each deposition step, the tensile stress silicon nitride film that is deposited using nitrogen plasma treatment；
Repeat the deposition step and processing step, until obtaining the tensile stress silicon nitride film of expectation thickness；
The tensile stress silicon nitride film with expectation thickness is patterned, to obtain the tensile stress layer；
Compressive stress layer is deposited on the PMOS transistor；
Comprehensive metallization medium layer；
CMP process, the upper surface of the exposure dummy gate electrode are carried out, and is protected above the tensile stress layer and the compressive stress layer
Stay the part dielectric layer；
The dummy gate electrode and the dummy gate electrode insulating layer are removed successively, form gate recess；Wherein in the dummy gate electrode
It removes in technique, the tensile stress silicon nitride of NMOS area only has fraction and is corroded removal, and is largely preserved；
In the gate recess, it is respectively formed the NMOS transistor and the high K gate insulation layers and gold of the PMOS transistor
Belong to grid.
2. according to the method described in claim 1, it is characterized in that, formation NMOS transistor and PMOS transistor specifically include：
Form the dummy gate electrode and the dummy gate electrode insulating layer；
Form grid gap wall；
Form the source and drain areas of transistor.
3. according to the method described in claim 1, it is characterized in that, in the deposition step, sunk using pecvd process
The thickness of product, the certain thickness tensile stress silicon nitride film is 10-1000 angstroms, preferably 30 angstroms.
4. according to the method described in claim 1, it is characterized in that, the nitrogen plasma treatment in the processing step uses N2
Plasma.
5. according to the method described in claim 1, it is characterized in that, deposition compressive stress layer is specific on the PMOS transistor
Including：
Deposited overall compression silicon nitride film is answered with the protection of patterned photoresist layer positioned at the pressure of the PMOS transistor
Then power silicon nitride film, removal remove photoresist layer positioned at the compression silicon nitride film of the NMOS transistor.
6. according to the method described in claim 1, it is characterized in that, the dielectric layer is TEOS layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210497474.2A CN103855092B (en) | 2012-11-28 | 2012-11-28 | Semiconductor device manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210497474.2A CN103855092B (en) | 2012-11-28 | 2012-11-28 | Semiconductor device manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103855092A CN103855092A (en) | 2014-06-11 |
| CN103855092B true CN103855092B (en) | 2018-11-06 |
Family
ID=50862570
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210497474.2A Active CN103855092B (en) | 2012-11-28 | 2012-11-28 | Semiconductor device manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103855092B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101305457A (en) * | 2005-11-08 | 2008-11-12 | 飞思卡尔半导体公司 | Electronic device including a transistor structure having an active region adjacent to a stressor layer and process for forming the electronic device |
| CN101496145A (en) * | 2006-06-20 | 2009-07-29 | 应用材料股份有限公司 | Method for increasing silicon nitride tensile stress by using in-situ nitrogen plasma treatment and ex-situ ultraviolet light curing |
| CN101850944A (en) * | 2009-03-30 | 2010-10-06 | 中国科学院半导体研究所 | Method for Depositing Silicon Nitride Film Using 13.56MHz RF Power Source |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102007046849B4 (en) * | 2007-09-29 | 2014-11-06 | Advanced Micro Devices, Inc. | Method of making large-gate-gate structures after transistor fabrication |
-
2012
- 2012-11-28 CN CN201210497474.2A patent/CN103855092B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101305457A (en) * | 2005-11-08 | 2008-11-12 | 飞思卡尔半导体公司 | Electronic device including a transistor structure having an active region adjacent to a stressor layer and process for forming the electronic device |
| CN101496145A (en) * | 2006-06-20 | 2009-07-29 | 应用材料股份有限公司 | Method for increasing silicon nitride tensile stress by using in-situ nitrogen plasma treatment and ex-situ ultraviolet light curing |
| CN101850944A (en) * | 2009-03-30 | 2010-10-06 | 中国科学院半导体研究所 | Method for Depositing Silicon Nitride Film Using 13.56MHz RF Power Source |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103855092A (en) | 2014-06-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9368497B2 (en) | Fin field-effect transistors and fabrication method thereof | |
| US11049970B2 (en) | Semiconductor device and manufacturing method thereof | |
| US7939392B2 (en) | Method for gate height control in a gate last process | |
| US8368147B2 (en) | Strained semiconductor device with recessed channel | |
| CN102194680B (en) | Fabrication method of gate structure | |
| US9269786B2 (en) | Silicon nitride layer deposited at low temperature to prevent gate dielectric regrowth high-K metal gate field effect transistors | |
| US20150243746A1 (en) | Semiconductor device and fabricating method thereof | |
| CN102543696B (en) | A method of manufacturing a semiconductor device | |
| KR101946765B1 (en) | Semiconductor device and manufacturing method thereof | |
| CN103000572A (en) | Contact for high-K metal gate device | |
| CN102244098A (en) | Semiconductor device and method for manufacturing the same | |
| KR20130091625A (en) | A semiconductor device and method of forming the same | |
| CN105225960A (en) | The method of semiconductor device and formation vertical stratification | |
| US9853128B2 (en) | Devices and methods of forming unmerged epitaxy for FinFET device | |
| CN104217954A (en) | Formation method of transistors | |
| US8030214B2 (en) | Method of fabricating gate structures | |
| CN102299092B (en) | Semiconductor device and forming method thereof | |
| US9159567B1 (en) | Replacement low-K spacer | |
| WO2012027988A1 (en) | Hybrid channel semiconductor device and manufacturing method thereof | |
| CN109087892B (en) | Semiconductor structure, forming method thereof and forming method of fin field effect transistor | |
| CN106653693A (en) | Method for improving performance of core device and input-output device | |
| CN103855092B (en) | Semiconductor device manufacturing method | |
| CN103681503B (en) | Semiconductor device manufacturing method | |
| CN104253049B (en) | Semiconductor device manufacturing method | |
| CN103730422B (en) | Semiconductor device manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| EXSB | Decision made by sipo to initiate substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20201215 Address after: 510000 601, building a, 136 Kaiyuan Avenue, Huangpu District, Guangzhou City, Guangdong Province Patentee after: AoXin integrated circuit technology (Guangdong) Co.,Ltd. Address before: 100029 No. 3 Beitucheng West Road, Chaoyang District, Beijing Patentee before: Institute of Microelectronics of the Chinese Academy of Sciences |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220425 Address after: 510000 room 710, Jianshe building, No. 348, Kaifa Avenue, Huangpu District, Guangzhou, Guangdong Patentee after: Ruili flat core Microelectronics (Guangzhou) Co.,Ltd. Address before: 510000 601, building a, 136 Kaiyuan Avenue, Huangpu District, Guangzhou City, Guangdong Province Patentee before: AoXin integrated circuit technology (Guangdong) Co.,Ltd. |