CN103855071B - A kind of preparation method of semiconductor device - Google Patents

Abstract

The invention relates to a method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate, the substrate at least including a core active region and a surrounding active region; sequentially forming a gate dielectric layer, a gate a material layer and a hard mask layer; patterning the hard mask layer and the gate material layer to form openings on the core active area and the surrounding active area; depositing a sacrificial material layer to fill the core active area an opening formed in the source region; etching removes the sacrificial material layer in the opening of the surrounding active region; performing a first shallow trench etch to form a first shallow trench in the surrounding active region; removing the core active a layer of sacrificial material in the region opening; performing a second shallow trench etch to form a core active region shallow trench in the substrate, forming a shallow trench deeper than the core active region in the surrounding active region The trench isolates the surrounding active area with a shallow trench. Compared with the prior art, the method of the invention is easier to control and more accurate.

Description

A kind of preparation method of semiconductor device

technical field

The invention relates to the field of semiconductors, and in particular, the invention relates to a method for preparing a semiconductor device.

Background technique

The improvement of integrated circuit performance is mainly achieved by continuously shrinking the size of integrated circuit devices to increase its speed. At present, due to the pursuit of high device density, high performance and low cost, the semiconductor industry has advanced to the nanotechnology process node, especially when the size of the semiconductor device is reduced to 32nm or below, it brings a series of challenges to the manufacture of the device.

As the device size decreases, it is difficult to control the aspect ratio when fabricating 32nm and below devices, especially in dense areas, such as the active area in 32nm flash memory devices, due to the limitation of void filling in the fabrication process And the surrounding area needs to prepare shallow trench isolation (shallow trench isolation, STI) with different depths, the STI with a depth of 1800 angstroms is prepared in the active area, and the STI with a depth of 3000 angstroms is prepared around the active area, but now It is difficult to achieve this purpose in existing technologies.

In the current prior art, the etching process is usually stopped at 1800 angstroms by precisely controlling the angle of the STI, but this depth has a close relationship with the critical dimension and angle of the STI. The offset makes the depth of the STI non-uniform, as shown in FIG. 1 .

The current method for preparing shallow trench isolations with different depths is shown in FIGS. a second advanced pattern film, an oxynitride layer, an oxide layer, and a first advanced pattern film 106, wherein the hard mask layer 104 may be a composite stack of oxide and nitride , form a patterned photoresist layer on the substrate as shown in Figure 2, with reference to Figure 3, use the photoresist as a mask layer to pattern the first advanced pattern layer 106, and then form the A spacer material layer 107 is deposited on the pattern, referring to FIG. 4, patterning the spacer material layer to form a spacer on the first advanced pattern layer, and then removing the remaining first advanced pattern layer, referring to FIG. 5. First, form a patterned photoresist layer on the surrounding active area, pattern the oxide layer, oxynitride layer, and the second advanced pattern layer, and finally refer to FIG. The pattern is etched as a mask, and etched to the semiconductor substrate 101 to form shallow trench isolations with different depths in the active area and the surrounding areas.

Although the prior art discloses the formation of shallow trench isolations with different depths in and around the active region, the existing methods are too dependent on the critical dimensions and angles of the shallow trench isolations, the critical dimensions and A slight deviation of the angle will cause uneven depth, the whole process is very cumbersome and difficult to control, and the yield rate of the product is very low.

Contents of the invention

A series of concepts in simplified form are introduced in the Summary of the Invention, which will be further detailed in the Detailed Description. The summary of the invention in the present invention does not mean to limit the key features and essential technical features of the claimed technical solution, nor does it mean to try to determine the protection scope of the claimed technical solution.

The invention provides a method for preparing a semiconductor device, comprising:

providing a semiconductor substrate comprising at least a core active region and a surrounding active region;

sequentially forming a gate dielectric layer, a gate material layer and a hard mask layer on the substrate;

patterning the hard mask layer and the gate material layer to form openings in the core active area and the surrounding active area;

depositing a layer of sacrificial material to fill the opening formed in the core active region;

etching away the layer of sacrificial material in the surrounding active area opening;

performing a first shallow trench etch to form a first shallow trench in the surrounding active region;

removing the layer of sacrificial material in the core active area opening;

performing a second shallow trench etching to form a core active area shallow trench in the substrate, and forming a surrounding active area shallow trench with a depth greater than that of the core active area shallow trench in the surrounding active area groove.

Advantageously, a layer of sacrificial material is conformally deposited to fill the opening formed in said core active region.

Preferably, the hard mask layer is silicon nitride and oxide deposited sequentially.

Preferably, the sacrificial material layer is one or more of dielectric, inorganic, amorphous carbon and metal material layers.

Preferably, the deposition method of the sacrificial material layer is CVD, PVD, ALD or controlled spin coating.

Preferably, the sacrificial material layer is etched by dry method or wet method, so as to remove the sacrificial material layer in the opening of the surrounding active region.

Preferably, the dry etching is isotropic etching.

Preferably, the first shallow trench etching is selected from one or more of HBr, Cl ₂ , O ₂ , N ₂ , NF ₃ , Ar, He and CF ₄ .

Preferably, the second shallow trench etching is selected from one or more of HBr, Cl ₂ , O ₂ , N ₂ , NF ₃ , Ar, He and CF ₄ .

Preferably, the gate material layer is a polysilicon layer.

Preferably, the method further includes the step of further forming shallow trench isolation in the core active area and shallow trench isolation in the surrounding active area.

Preferably, a silicon oxide layer is formed in the shallow trenches in the core active region and in the shallow trenches in the peripheral active region, the silicon oxide layer covers the substrate, and the silicon oxide layer is planarized to the the substrate.

In the present invention, through two shallow trench etching steps, shallow trench isolations with different depths are formed in the core active region and the surrounding active region respectively, wherein only the surrounding A shallow trench is formed in the active area, and the etching stops on the sacrificial material layer in the active area, and the depth of the shallow trench in the surrounding active area is the active area shallow trench isolation and the surrounding area. The depth difference between the shallow trench isolations in the active area, and then perform the second shallow trench etching to the target depth. By controlling the etching process, different regions have different shallow trench isolations with different depths, which is more accurate than the existing technology. Easy to control and more accurate.

Description of drawings

The following drawings of the invention are hereby included as part of the invention for understanding the invention. Embodiments of the present invention and their descriptions are shown in the drawings to explain the device and principle of the present invention. In the attached picture,

Fig. 1 is a schematic diagram of a device with non-uniform depth of shallow trench isolation prepared in the prior art;

2-6 are schematic diagrams of the fabrication process of devices with different depths of shallow trench isolation in the prior art;

7-12 are schematic diagrams of the preparation process of devices with different depths of shallow trench isolation in the present invention;

Fig. 13 is a flow chart of the process for preparing shallow trench isolation devices with different depths in the present invention.

detailed description

In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.

In order to thoroughly understand the present invention, a detailed description will be provided in the following description to illustrate the semiconductor device with controllable height fins and the manufacturing method thereof of the present invention. Obviously, the practice of the invention is not limited to specific details familiar to those skilled in the semiconductor arts. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments besides these detailed descriptions.

It should be noted that the terms used herein are for the purpose of describing specific embodiments only, and are not intended to limit exemplary embodiments according to the present invention. As used herein, singular forms are intended to include plural forms unless the context clearly dictates otherwise. In addition, it should also be understood that when the terms "comprising" and/or "comprising" are used in this specification, it indicates the presence of the features, integers, steps, operations, elements and/or components, but does not exclude the presence or One or more other features, integers, steps, operations, elements, components and/or combinations thereof are added.

Now, exemplary embodiments according to the present invention will be described in more detail with reference to the accompanying drawings. These example embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of these exemplary embodiments to those of ordinary skill in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity, and the same reference numerals are used to designate the same elements, and thus their descriptions will be omitted.

The method for preparing a semiconductor device with shallow trench isolation with different depths according to the present invention will be further described below in conjunction with FIGS. 7-12 :

Referring to FIG. 7, a semiconductor substrate 201 is first provided, the substrate at least includes a core active area (Core Active Area, AA) and a peripheral active area (Periphery Active Area, PAA), and the semiconductor substrate may be as mentioned below At least one of the available materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc., other active devices can also be formed in the semiconductor substrate. In the present invention, silicon-on-insulator (SOI) is preferred, and the silicon-on-insulator (SOI) includes a support substrate, an oxide insulating layer, and a semiconductor material layer from bottom to top, wherein the top semiconductor material layer is a single Crystalline silicon layer, polysilicon layer, SiC or SiGe.

A gate dielectric layer 202 is sequentially deposited on the semiconductor substrate, wherein the gate material layer may be silicon oxide (SiO2) or silicon oxynitride (SiON). The gate dielectric layer made of silicon oxide can be formed by an oxidation process known to those skilled in the art, such as furnace tube oxidation, rapid thermal annealing oxidation (RTO), in-situ steam oxidation (ISSG), and the like. Performing a nitriding process on silicon oxide can form silicon oxynitride, wherein the nitriding process can be high temperature furnace tube nitriding, rapid thermal annealing nitriding or plasma nitriding, of course, other nitriding processes can also be used, I won't go into details here. The gate dielectric layer can be formed by thermal oxidation, nitridation or oxynitride process. When forming the gate dielectric layer, the above processes may also be used in combination. The gate dielectric layer may comprise any conventional dielectric such as SiO ₂ , Si ₃ N ₄ , SiON, SiON ₂ , such as TiO ₂ , Al ₂ O ₃ , ZrO ₂ , HfO ₂ , Ta ₂ O ₅ , La ₂ O ₃ high-k dielectrics and other similar oxides including, but not limited to, perovskite-type oxides. Typically, high-k dielectrics can withstand high temperature (900°C) annealing. The gate dielectric layer may also include any combination of the above dielectric materials.

The gate dielectric layer may include conventional dielectric materials such as oxides, nitrides and oxynitrides of silicon having a dielectric constant from about 4 to about 20 (measured in vacuum). Alternatively, the gate dielectric layer may comprise a generally higher dielectric constant dielectric material having a dielectric constant of from about 20 to at least about 100. The gate dielectric layer is preferably a high dielectric constant (high K) material. The high-K materials include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, etc. . Particularly preferred are hafnium oxide, zirconium oxide and aluminum oxide. The formation process of the gate dielectric layer can adopt any existing technology known to those skilled in the art, and chemical vapor deposition is preferred, and the thickness of the gate dielectric layer is 15 to 60 angstroms.

A gate material layer 203 is deposited on the gate dielectric layer, the gate material layer is preferably Si, polysilicon, SiGe, Ge or III-V material, preferably a polysilicon layer in the present invention.

Then deposit a hard mask layer on the gate material layer, the hard mask layer can be a nitride, oxide and/or metal hard mask layer, such as SiN, AC, SiO ₂ , BN, SiON, TiN and one or more of Cu ₃ N. In a specific embodiment of the present invention, the hard mask layer is preferably a combination of a nitride layer 204 and an oxide layer 205, wherein the nitride layer can be SiN, and the oxide layer can be SiON or SiO ₂ , but not limited to this example.

The method for forming the gate material layer 203 and the hard mask layers 204 and 205 can be a low-pressure method formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD). One of chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and selective epitaxial growth (SEG).

Referring to FIG. 8 , patterning the hard mask layer and the gate material layer to form openings on the core active region and the surrounding active region;

Specifically, firstly, a patterned photoresist layer (not shown in the figure) is formed on the substrate, wherein the photoresist layer defines the critical dimensions and number of shallow trench isolations to be formed, and then The photoresist layer is a mask, and the hard mask layer and the gate material layer are etched to stop at the gate dielectric layer to protect the substrate, and the core active A plurality of openings are formed in the surrounding active region and the surrounding active region, as preferably the critical dimensions of the openings in the surrounding active region are larger than the openings in the core active region.

Referring to FIG. 9, depositing a sacrificial material layer to fill the opening formed in the core active region;

Specifically, a layer of sacrificial material is conformally deposited on the substrate to completely fill the opening formed in the core active region, and in the surrounding active region, on the sidewalls of the opening and the A sacrificial material layer is formed on the gate dielectric layer, which does not completely seal the opening, as shown in FIG. 9 .

Preferably, the sacrificial material layer is one or more of dielectric layer, inorganic material layer, amorphous carbon or metal material layer, and the formation method of the sacrificial material layer is chemical vapor deposition (CVD), physical One of low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) or controlled spin-on formed by vapor phase deposition (PVD) or atomic layer deposition (ALD).

Referring to FIG. 10 , etching removes the sacrificial material layer in the opening of the surrounding active region;

Specifically, etching the sacrificial material layer to remove all the sacrificial material layer in the surrounding active area to open the surrounding active area, while only part of the sacrificial material layer is removed in the core active area, Preferably, dry etching or wet etching can be selected in this step to achieve the above purpose, wherein when dry etching is selected, the dry etching is controlled to be isotropic etching.

Referring to FIG. 11 , performing a first shallow trench etch to form a first shallow trench in the surrounding active region;

Specifically, in this step, a conventional etching method can be selected to etch and remove part of the sacrificial material layer and the hard mask layer in the core active area, and first etch in the surrounding active area to open the gate dielectric layer, and then etch the semiconductor material layer to form a first shallow trench.

In a specific embodiment of the present invention, one or more of HBr, Cl ₂ , O ₂ , N ₂ , NF ₃ , Ar, He and CF ₄ can be selected as the etching gas. CF ₄ , NF ₃ gas, and one of N ₂ and O ₂ can also be added as an etching atmosphere, wherein the flow rate of the gas is 20-100 sccm, preferably 50-80 sccm, and the etching pressure is 30-150 mTorr , the etching time is 5-120s, preferably 5-60s, more preferably 5-30s, in addition, Ar is selected as the diluent gas for the dry etching.

In this step, the etching stops on the layer of sacrificial material in the core active area, and a first shallow trench with a certain depth is formed in the substrate in the surrounding active area, the shallow The depth of the trench is the depth difference between the shallow trench isolation in the core active area and the shallow trench isolation in the surrounding active area. Therefore, the shallow trench isolation with different depths in different regions can be realized by controlling the etching process in this step. This step is easier to control and more accurate than the prior art.

Referring to FIG. 12 , the sacrificial material layer in the opening of the core active area is removed, and a second shallow trench etch is performed to form a shallow trench in the core active area in the substrate, and a shallow trench in the surrounding active area is formed. The surrounding active area shallow trench is deeper than the core active area shallow trench isolation.

Specifically, in this step, the core active area and the surrounding active area are etched simultaneously, the remaining sacrificial material layer is removed in the core active area, and then etched to a target depth, while the surrounding area Continue etching in the active region on the basis of the first shallow trench isolation to obtain deeper shallow trenches around the active region to a desired target depth.

In this step, one or more of HBr, Cl ₂ , O ₂ , N ₂ , NF ₃ , Ar, He, and CF ₄ can be selected as the etching gas, and the specific etching conditions can refer to the first shallow trench isolation etching , and can also be adjusted as needed, and will not be repeated here.

After forming the shallow trenches, the method further includes the step of further forming shallow trench isolations in the core active area and shallow trench isolations in the surrounding active areas, specifically, in the shallow trenches in the core active area forming a silicon oxide layer in the shallow trenches of the surrounding active region, the silicon oxide layer covering the substrate; and planarizing the silicon oxide layer to the substrate.

In the present invention, through two shallow trench etching steps, shallow trench isolations with different depths are formed in the core active region and the surrounding active region respectively, wherein only the surrounding A shallow trench is formed in the active area, and the etching stops on the sacrificial material layer in the core active area, and the depth of the shallow trench in the surrounding active area is the core active area shallow trench isolation The depth difference between the shallow trench isolation and the surrounding active area, and then perform the second shallow trench etching to the target depth. By controlling the etching process, different regions have different shallow trench isolations with different depths. Compared with the existing Technology is easier to control and more accurate.

Figure 13 is a process flow chart for preparing the semiconductor device of the present invention, comprising the following steps:

Step 201 provides a semiconductor substrate, the substrate includes at least a core active region and a surrounding active region;

Step 202 sequentially forming a gate dielectric layer, a gate material layer and a hard mask layer on the substrate;

Step 203 patterning the hard mask layer and the gate material layer to form openings on the core active region and the surrounding active region;

Step 204 depositing a layer of sacrificial material to fill the opening formed in the core active region;

Step 205 etching and removing the sacrificial material layer in the opening of the surrounding active region;

Step 206 performing a first shallow trench etch to form a first shallow trench in the surrounding active region;

Step 207 removing the sacrificial material layer in the opening of the core active region;

Step 208 performs second shallow trench etching to form core active area shallow trenches in the substrate, and forms surrounding active area in the surrounding active area with a depth greater than that of the core active area shallow trench isolation. shallow grooves.

The present invention has been described through the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of illustration and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above-mentioned embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the claimed scope of the present invention. within the range. The protection scope of the present invention is defined by the appended claims and their equivalent scope.

Claims (12)

1. a preparation method for semiconductor device, including:

Thering is provided Semiconductor substrate, described substrate is including at least core active district and surrounding active area；

Sequentially form gate dielectric, gate material layers and hard mask layer over the substrate；

Pattern described hard mask layer and described gate material layers, with in described core active district and described week It is with in source region formation opening；

Sacrificial material layer, to fill the opening formed in described core active district；

Described sacrificial material layer in etching removal active area opening around；

Perform the first shallow trench etching, to form the first shallow trench in active area around described, described the One shallow trench stops in being etched in described active area in described sacrificial material layer, in described surrounding active area The degree of depth of described first shallow trench is the isolation of described active area shallow trench and surrounding active area shallow trench is isolated Between depth difference；

Remove the sacrificial material layer in described core active district opening；

Perform the second shallow trench etching, to form core active district shallow trench in described substrate, described Around active area forms degree of depth surrounding's active area shallow trench more than described core active district shallow trench.

Method the most according to claim 1, it is characterised in that conformal deposited sacrificial material layer, with Fill the opening formed in described core active district.

Method the most according to claim 1, it is characterised in that described hard mask layer is for being sequentially depositing Silicon nitride and oxide.

Method the most according to claim 1, it is characterised in that described sacrificial material layer be dielectric medium, One or more in inorganic matter, amorphous carbon and metal material layer.

Method the most according to claim 1, it is characterised in that the deposition side of described sacrificial material layer Method is CVD, PVD, ALD or controls spin coating.

Method the most according to claim 1, it is characterised in that select dry method or wet etching institute State sacrificial material layer, to remove the described sacrificial material layer in described surrounding active area opening.

Method the most according to claim 6, it is characterised in that described dry etching is isotropism Etching.

Method the most according to claim 1, it is characterised in that described first shallow trench etching is selected HBr、Cl₂、O₂、N₂、NF₃, Ar, He and CF₄In one or more.

Method the most according to claim 1, it is characterised in that described second shallow trench etching is selected HBr、Cl₂、O₂、N₂、NF₃, Ar, He and CF₄In one or more.

Method the most according to claim 1, it is characterised in that described gate material layers is polycrystalline Silicon layer.

11. methods according to claim 1, it is characterised in that described method also includes further Form the shallow trench isolation of core active district and the step of surrounding active area shallow trench isolation.

12. according to the method described in claim 1 or 11, it is characterised in that in described core active district Forming silicon oxide layer in shallow trench and in described surrounding active area shallow trench, described silicon oxide layer covers described Substrate, planarizes described silicon oxide layer to described substrate.