CN103855024A - NMOS transistor, CMOS transistor and manufacturing method of NMOS transistor and CMOS transistor - Google Patents
NMOS transistor, CMOS transistor and manufacturing method of NMOS transistor and CMOS transistor Download PDFInfo
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- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
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- H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
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- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
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- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
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Abstract
本发明公开了一种NMOS晶体管、CMOS晶体管及两者的制作方法。其中，所述NMOS晶体管的制作方法包括：提供半导体衬底；在所述半导体衬底上形成栅极结构，以及在栅极结构两侧形成源极和漏极；形成张应力层，所述张应力层覆盖所述栅极结构和所述半导体衬底；去除覆盖在所述栅极结构上方和栅极结构两侧的至少部分的张应力层；在栅极结构两侧被去除所述张应力层处形成压应力层。通过把NMOS晶体管侧墙位置处的张应力层换成压应力层，除去了侧墙位置处的张应力层对NMOS晶体管的带来的负面影响，并且侧墙位置处的压应力层可以对衬底产生直接的压力，迫使沟道产生与受到的压力方向垂直的张力，进一步提高NMOS晶体管中电子的迁移率。
The invention discloses an NMOS transistor, a CMOS transistor and their manufacturing methods. Wherein, the manufacturing method of the NMOS transistor includes: providing a semiconductor substrate; forming a gate structure on the semiconductor substrate, and forming a source and a drain on both sides of the gate structure; forming a tensile stress layer, the tension The stress layer covers the gate structure and the semiconductor substrate; removing at least part of the tensile stress layer covering the gate structure and on both sides of the gate structure; removing the tensile stress on both sides of the gate structure A compressive stress layer is formed at the layer. By replacing the tensile stress layer at the sidewall position of the NMOS transistor with a compressive stress layer, the negative impact of the tensile stress layer at the sidewall position on the NMOS transistor is removed, and the compressive stress layer at the sidewall position can protect the substrate The bottom generates direct pressure, forcing the channel to generate tension perpendicular to the direction of the pressure, which further improves the mobility of electrons in the NMOS transistor.
Description
Technical field
The present invention relates to field of semiconductor fabrication, relate in particular to a kind of nmos pass transistor and preparation method thereof, CMOS transistor and preparation method thereof.
Background technology
Along with the development of ic manufacturing technology, the characteristic size of integrated circuit constantly reduces; In this development process, in order semiconductor device not to be caused damage, certainly will the operating voltage of integrated circuit also constantly to be reduced accordingly.But in order to guarantee that integrated circuit can keep good performance under less operating voltage, the way conventionally adopting is at present that stress is put in MOS transistor, thereby causes lattice strain, to improve the mobility in charge carrier (electronics or hole).Have a variety of to the technology of MOS transistor stress application, such as: stress memory technique (Stress memorization technique, SMT), dual stressed layers (Dual stress liners, DSL), stress approaches technology (Stress proximity technique, SPT), implant SiGe or SiC(eSiGe/eSiC) form stress liner layer etc., the relevant Chinese patent application that can be CN101924107A with reference to publication No. to the information of CMOS transistor stress application.
But, in existing mode, still can not meet the demand for the higher running speed of transistor to the improvement of MOS transistor performance.Therefore, be necessary to provide a kind of MOS transistor that can further increase the charge carrier mobility of raceway groove.
Summary of the invention
The problem that the present invention solves is in prior art, still can not meet transistor needs to the technology of MOS transistor stress application to have the demand of higher running speed.
For addressing the above problem, technical scheme of the present invention provides a kind of manufacture method of nmos pass transistor, comprising:
Semiconductor substrate is provided;
In described Semiconductor substrate, form grid structure, in the Semiconductor substrate of grid structure both sides, form source electrode and drain electrode;
Form tensile stress layer, described tensile stress layer covers side, upper surface and the described Semiconductor substrate of described grid structure;
Removal covers the tensile stress layer of described grid structure upper surface;
At least part of tensile stress layer of removing grid structure side, the tensile stress layer of grid structure side is removed to the height of the tensile stress layer in the Semiconductor substrate that is not less than grid structure both sides;
Be removed described tensile stress layer place in grid structure side and form compressive stress layer.
Optionally, before source electrode and drain electrode form, the described grid structure forming is dummy gate, and it comprises high K medium layer and pseudo-gate material layer; After removal covers the tensile stress layer of described grid structure upper surface, also comprise and remove described pseudo-gate material layer to form breach, in described breach, fill workfunction layers, to form the step of high-k/metal gate.
Optionally, described grid structure is multiple; After formation tensile stress layer covers described grid, removal is also included on described tensile stress layer and forms dielectric layer, to fill up the space between described multiple grid structure before covering the tensile stress layer of side of described grid structure upper surface and grid structure.
Optionally, adopt the mode of cmp to carry out overall planarization after forming dielectric layer on described tensile stress layer, described cmp proceeds to and exposes described grid structure to remove the tensile stress layer of grid structure upper surface.
Optionally, after described cmp proceeds to and exposes described grid structure, utilize etching technics to remove at least part of tensile stress layer of grid structure side.
Optionally, described grid structure comprises gate insulator and gate material layer, and wherein, described gate insulator is silica, and described gate material layer is polysilicon.
Optionally, before the step of described formation tensile stress layer, be also formed with self-aligned metal silicate on the surface of described source electrode and drain electrode.
Technical scheme of the present invention also provides the transistorized manufacture method of a kind of CMOS, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, there are at least two grid structures, be distributed in nmos transistor region and PMOS transistor area;
Upper surface and side at described semiconductor substrate surface and grid structure form tensile stress layer;
Remove the tensile stress layer of described grid structure upper surface;
Remove the tensile stress layer at the grid structure side place part tensile stress layer of nmos transistor region and the grid structure side place of PMOS transistor area; Wherein, at nmos transistor region, tensile stress layer is removed to the height of the tensile stress layer in the Semiconductor substrate that is not less than grid structure both sides; In PMOS transistor area, tensile stress layer is removed to the Semiconductor substrate of the grid structure both sides of exposing PMOS transistor area;
Remove tensile stress layer place in the grid structure side of nmos transistor region and PMOS transistor area and fill compressive stress layer.
Optionally, before tensile stress layer forms, the described grid structure forming is dummy gate, comprises high K medium layer and pseudo-gate material layer; After removal covers the tensile stress layer of described grid structure upper surface, also comprise and remove described pseudo-gate material layer to form breach, in described breach, fill workfunction layers, to form the step of high-k/metal gate.
Optionally, described grid structure is multiple; After described formation tensile stress layer, before removing the tensile stress layer of described grid structure upper surface and grid structure side, be also included on described tensile stress layer and form dielectric layer, to fill up the space between described multiple grid structure.
Optionally, adopt the mode of cmp to carry out overall planarization after forming dielectric layer on described tensile stress layer, described cmp proceeds to and exposes described grid structure to remove the tensile stress layer of grid structure upper surface.
Optionally, described grid structure comprises gate insulator and gate material layer, and wherein, described gate insulator is silica, and described gate material layer is polysilicon.
Optionally, before the step of described formation tensile stress layer, the surface that is also included in described source electrode and drain electrode is formed with self-aligned metal silicate.
Technical scheme of the present invention also provides a kind of nmos pass transistor, comprising:
Be formed on grid structure in Semiconductor substrate and be arranged in the source-drain area of the Semiconductor substrate of described grid structure both sides;
Cover compressive stress layer and the tensile stress layer of the Semiconductor substrate of described grid structure and grid structure both sides, wherein, the Semiconductor substrate of described tensile stress layer overlies gate structure both sides, and one section of height starting from bottom of grid structure side, described compressive stress layer covers the described grid structure side of residual altitude, and higher than the height of the tensile stress layer in the Semiconductor substrate of grid structure both sides.
Technical scheme of the present invention also provides a kind of CMOS transistor, comprising:
Be formed on grid structure in Semiconductor substrate and be arranged in the source-drain area of the Semiconductor substrate of described grid structure both sides, described Semiconductor substrate comprises nmos transistor region and PMOS transistor area;
Cover compressive stress layer and the tensile stress layer of the Semiconductor substrate of described grid structure and grid structure both sides, wherein, at nmos transistor region, the Semiconductor substrate of described tensile stress layer overlies gate structure both sides, and one section of height starting from bottom of grid structure side, described compressive stress layer covers the described grid structure side of residual altitude; In PMOS transistor area, the Semiconductor substrate of described tensile stress layer overlies gate structure both sides, described compressive stress layer covers the side of described grid structure, and covers the surface of described Semiconductor substrate.
Compared with prior art, technical solution of the present invention has the following advantages:
Technical solution of the present invention changes compressive stress layer into the tensile stress layer of nmos pass transistor side wall position, remove the negative effect bringing of the tensile stress layer pair nmos transistor of side wall position, and the compressive stress layer of side wall position can produce direct pressure to substrate, force raceway groove to produce the tension force vertical with the pressure direction being subject to, further improve the mobility of electronics in nmos pass transistor.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing a kind of nmos pass transistor with high-K metal gate;
Fig. 2 to Figure 10 is the schematic diagram of the manufacturing process of the nmos pass transistor with high-k/metal gate that provides of embodiments of the invention one.
Figure 11 is the schematic diagram of the transistorized manufacturing process of CMOS with high-k/metal gate that provides of embodiments of the invention three.
Embodiment
In the manufacturing process of the MOS transistor of high-K metal grid (HKMG), a kind of mode of the raceway groove stress application to MOS transistor is as follows: first in semiconductor device, form high-K gate dielectric layer, be positioned at the polysilicon dummy gate (dummy poly gate) on high-K gate dielectric layer; Then deposit one or more layers dielectric layer and cover described polysilicon dummy gate, utilize chemico-mechanical polishing (CMP) technique to carry out planarization until expose polysilicon dummy gate; Remove polysilicon dummy gate, form groove in polysilicon dummy gate position simultaneously, depositing metal layers is so that metal level is filled described groove again, and the metal gates being made up of metal level like this can substitute polysilicon dummy gate, and high-K gate dielectric layer forms metal gate together with metal level.Wherein, the multilayer dielectricity layer depositing before planarization comprises contact hole etching stop-layer (Contact etch stop layers, CESL) and interlayer dielectric layer, etching stop layer when described CESL forms contact hole as etching interlayer dielectric layer.The material of CESL is generally silicon nitride, and quality is harder.It can produce tensile stress or compression to the semiconductor device of its covering, and the type that produces stress is specifically determined by the process conditions that form in the depositing operation of silicon nitride.So this one deck silicon nitride is except as CESL, general also as the stressor layers to MOS transistor stress application.General, CESL described in nmos pass transistor is tensile stress layer, CESL described in PMOS transistor is compressive stress layer.
Similarly, also can the MOS transistor of general polysilicon gate be taked in grid and Semiconductor substrate, to deposit stressor layers raceway groove stress application is improved the usefulness of MOS transistor.Wherein, CESL described in nmos pass transistor is tensile stress layer, and CESL described in PMOS transistor is compressive stress layer.
MOS transistor 3 as shown in Figure 1, it has source S, drain D and the grid G in the Semiconductor substrate 200 between source S and drain D in Semiconductor substrate 200, in Semiconductor substrate 200 and grid G, be coated with the stressor layers 300 that can be used as CESL, for nmos pass transistor, described stressor layers 300 is tensile stress layer, for PMOS transistor, described stressor layers 300 is compressive stress layer.And inventor finds, the device of the short channel that is 20nm ~ 100nm for channel length, the effect that described stressor layers 300 is positioned at base section 301 in Semiconductor substrate 200, be positioned at the sidewall sections 302 of grid G side wall position and be positioned at the stress that top section 303 these three parts of top portions of gates produce raceway groove is different separately.Wherein, in nmos pass transistor, the tensile stress layer of base section 301 directly plays the effect of tensile stress to raceway groove, can improve the carrier mobility of electronics in nmos pass transistor raceway groove, the tensile stress layer of top section 303 does not have direct effect to raceway groove, even there is part reverse effect, and the tensile stress layer of sidewall sections 302 is effects of raceway groove being played to compression, can weaken the carrier mobility of electronics in nmos pass transistor raceway groove.In PMOS transistor, the compressive stress layer of the compressive stress layer of base section 301 and top section 303 does not have direct effect to raceway groove, even there is reverse effect, the compressive stress layer of side wall position directly plays the effect of compression to raceway groove, can significantly improve the carrier mobility in hole in PMOS transistor channel.Thus, inventor recognizes: for nmos pass transistor, the tensile stress layer of the sidewall sections 302 in grid G side wall position not only can not play the effect that improves nmos pass transistor channel performance, has also produced minus effect; And the tensile stress layer of top section 303 in top portions of gates does not have any impact for the usefulness that improves nmos pass transistor.And for PMOS transistor, thering is appreciable impact except the usefulness of the compressive stress layer pair pmos transistor of the sidewall sections 302 in grid G side wall position improves, the usefulness of the compressive stress layer pair pmos transistor of two other position does not have a direct impact.
Based on above-mentioned cognition, the present inventor proposes the tensile stress layer of nmos pass transistor top portions of gates to remove, change the part tensile stress layer of side wall position into compressive stress layer again, the compressive stress layer at side wall place can produce direct pressure to substrate like this, forces raceway groove to produce the tension force vertical with the pressure direction being subject to.
For making CMOS transistor, can all deposit tensile stress layer at nmos pass transistor and PMOS transistor area, then remove the tensile stress layer at nmos pass transistor and PMOS transistor gate top, again the part tensile stress layer of nmos pass transistor side wall position is changed into compressive stress layer, all tensile stress layers at PMOS transistor side wall displacement place are changed into compressive stress layer.Like this, form tensile stress layer and compare in the transistorized technique of making CMOS of PMOS transistor formation compressive stress layer at nmos pass transistor respectively with script, scheme provided by the invention not only can improve transistorized usefulness, can also simplify and make the transistorized technological process of CMOS with stressor layers, save cost.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
A lot of details are set forth in the following description so that fully understand the present invention.But the present invention can implement to be much different from alternate manner described here, and those skilled in the art can do similar popularization without prejudice to intension of the present invention in the situation that, and therefore the present invention is not subject to the restriction of following public concrete enforcement.
Embodiment mono-
In the present embodiment, take the nmos pass transistor with high-k/metal gate as example, elaborate design of the present invention.
As shown in Figure 2, provide Semiconductor substrate 100, in described Semiconductor substrate 100, form source S, drain D and the grid structure of nmos pass transistor, and cover the tensile stress layer 103 in grid structure and described Semiconductor substrate 100.
In the present embodiment, described Semiconductor substrate can be the lightly doped Semiconductor substrate of P type, or has the Semiconductor substrate of P trap.Described source S, drain D and grid structure are formed in P trap or the lightly doped region of P type.
In this step of the present embodiment, described grid structure is dummy gate, and wherein, described gate insulator 101 is high K medium layer, and described pseudo-gate material layer 104 is polysilicon.Described pseudo-gate material layer is according to the preformed polysilicon layer of needs of the rear grid technique of formation high-K metal gate in this step, it can be removed in subsequent technique, and then fill out new workfunction layers as grid material, form the real grid of nmos pass transistor.
Described source S, drain D are the N-type high-concentration dopant district that is arranged in the Semiconductor substrate 100 of described grid structure both sides.
The material of described tensile stress layer 103 is silicon nitride, and its effect has two kinds: the one, when in subsequent technique, etching interlayer dielectric layer forms contact hole, as contact hole etching stop-layer (Contact etch stoplayers, CESL); Another effect is that the raceway groove of pair nmos transistor provides tensile stress.
Wherein, also have the metal silicide (not shown) that adopts self-registered technology to form in source S, drain D, described metal silicide is NiSi or NiPtSi, and in metal silicide NiPtSi, the shared mass percent of Pt is 5 ~ 10%.The effect of described metal silicide is to reduce in the nmos pass transistor finally having formed, the contact resistance between source S, drain D and contact hole.In the present embodiment, before described self-aligned metal silicate is formed on 103 covering of tensile stress layer.Like this, can make the stressor layers of tensile stress layer 103 and follow-up formation be retained in nmos pass transistor surface, maintain transistorized raceway groove stress application.In the present embodiment, provide the mode of stressor layers to be different from stress memory technique of the prior art, stress memory technique is that the mode by having annealed after having formed stressor layers is remembered in substrate stress, in the process of annealing, silicon in substrate etc. can expand, and stressor layers can fetter the expansion of the silicon of substrate surface, keep the lattice structure similar with stressor layers, the stress in stressor layers is remembered in substrate like this, and raceway groove is produced to stress.Then, then stressor layers remove.Stressor layers just can form the processing step that self-aligned metal silicate, formation inter-level dielectric etc. need to directly be processed substrate after removing.And in the present embodiment, can come raceway groove stress application by retaining stressor layers, so just do not need just can make stress can be applied on raceway groove by this step of annealing, can avoid like this annealing to make the Impurity Diffusion in the ion doped region in the substrate such as source S, drain D and the bad impact bringing and the impact bringing on metal silicide of avoiding annealing to bring.Meanwhile, owing to not needing to remove stressor layers, the impact on metal silicide surface resistance can also avoid removing stressor layers time.
Next, as shown in Figure 3, form interlayer dielectric layer 105 on the surface of tensile stress layer 103.
Shown in figure, be only a grid structure, but those skilled in the art can imagine, in the process of whole semiconductor technology, relate to several grid structures that are positioned on same semiconductor base.Form tensile stress layer 103 in process previous step after, the tensile stress layer 103 between grid structure and grid structure can be formed with depression.In order to make overall planarization, form again one deck interlayer dielectric layer 105 on described tensile stress layer 103 surface, to fill up the space between grid structure and grid structure, until the surface of described interlayer dielectric layer 105 at least exceedes grid structure surface.
Described interlayer dielectric layer 105 is the conventional materials of interlayer dielectric layer such as silica or advanced low-k materials, and generation type can be deposition or spin coating.
Next, as shown in Figure 4, remove interlayer dielectric layer 105 and the tensile stress layer 103 on grid structure surface.
In the present embodiment, removing the interlayer dielectric layer 105 of gate surface and the mode of tensile stress layer 103 is cmp, and described cmp proceeds to and exposes pseudo-gate material layer 104 and stop.Like this, interlayer dielectric layer 105 and tensile stress layer 103 on grid structure have been removed, but the interlayer dielectric layer in other region 105 and tensile stress layer 103 are still withed a hook at the end.
Next, as shown in Figure 5, remove pseudo-gate material layer 104 as shown in Figure 4 in grid structure, form breach 20 in the position at its original place.
In previous step, removed dielectric layer 104 and the tensile stress layer 103 on grid structure surface by cmp, expose pseudo-gate material layer 104.In this step, can directly remove by wet etching the pseudo-gate material layer 104 coming out.In the present embodiment, aforementioned grid structure is dummy gate, in order that form high-k/metal gate according to rear grid technique.The object of removing pseudo-gate material layer 104 in this step is for forming metal gate at pseudo-gate material layer 104 places in subsequent technique.
Next, as shown in Figure 6, deposition one NMOS workfunction layers 106, in the interior formation one NMOS workfunction layers 106 of breach 20, to form metal gates.The formation method of described NMOS workfunction layers 106 is deposition or plating.
Next, as shown in Figure 7, remove the part tensile stress layer 103 at metal gates side wall place, form respectively groove 7 in metal gates both sides.The method of removing is etching, and described etching maintains the level height that makes the bottom of groove 7 be not less than the tensile stress layer 103 being positioned in Semiconductor substrate.In subsequent technique, described groove 7 is interior can fill the compressive stress layer different from tensile stress layer 103 stress types, if etching proceeds to the level height lower than the tensile stress layer 103 in Semiconductor substrate, can make the compressive stress layer of follow-up filling can apply the pressure not expecting to have to raceway groove.
Next, as shown in Figure 8, at groove 7(referring to Fig. 7) in fill compressive stress layer 107, the material of described compressive stress layer 107 can be silicon nitride, the stress types of its generation can be controlled by the parameter and the means that form technique.Described generation type can be deposition.Those skilled in the art can imagine, after described deposition finishes, not only in groove 7, fill and have expired compressive stress layer 107, also have the compressive stress layer 107 of formation on the surface of interlayer dielectric layer 105.For fear of the compressive stress layer 107 that is formed on interlayer dielectric layer 105 surfaces, interlayer dielectric layer 105 is below applied to compression, pair nmos transistor produces unnecessary impact, also need to remove by cmp the compressive stress layer on described interlayer dielectric layer 105 surfaces, only leave the compressive stress layer 107 of just filling and leading up groove 7.
Next, as shown in Figure 9, then deposition form interlayer dielectric layer 108, then in source S or/and drain D and metal gates above form contact hole 22,23, fill metal with form metal connect 220,230, the structure of formation is as shown in figure 10.The said structure forming comprises:
Be formed on grid structure in Semiconductor substrate 100 and be arranged in source region S and the drain region D of the Semiconductor substrate of described grid structure both sides, described grid structure is made up of gate dielectric layer 101 and gate material layers 106;
Cover the stressor layers 103 and 107 of the Semiconductor substrate of described grid structure and grid structure both sides, wherein, compressive stress layer 107 is positioned at the both sides of described grid structure, in the Semiconductor substrate of grid structure both sides, be tensile stress layer 103, described compressive stress layer 107 is not less than the level height of the tensile stress layer in the Semiconductor substrate of grid structure both sides.
Between described grid structure, there is interlayer dielectric layer 105, and on grid structure, there is interlayer dielectric layer 108.
On the source region S of described nmos pass transistor or drain region D, grid structure, also can also lead to the metal of realizing with other semiconductor device realization electrical connection and be connected 230 or 220.
Embodiment bis-
In the present embodiment, take common nmos pass transistor as example.Wherein, in the present embodiment, the grid that described grid structure is MOS transistor, comprises gate insulator and gate material layer, and described gate insulator is silica, and described gate material layer is polysilicon.In subsequent technique, do not need to remove gate material layer and insert again the step of metal gate.Other technological operation and step and embodiment mono-are similar.
Concrete, the method for making nmos pass transistor in the present embodiment comprises:
Semiconductor substrate is provided, in described Semiconductor substrate, forms source electrode, the drain electrode of nmos pass transistor, in described Semiconductor substrate, form grid structure, and cover the tensile stress layer in grid structure and described Semiconductor substrate;
Surface at tensile stress layer forms interlayer dielectric layer, to fill the space between grid structure;
Remove interlayer dielectric layer and the tensile stress layer of grid structure top;
The part tensile stress layer of removing grid structure both walls surface, forms respectively groove in grid structure both sides;
In groove, fill compressive stress layer, the material of described compressive stress layer can be silicon nitride, and the stress types of its generation can be controlled by the parameter and the means that form technique;
Deposition forms interlayer dielectric layer again, then at source electrode or/and drain electrode and metal gates above form contact hole, fill metal to form metal connection.
Embodiment tri-
In the present embodiment, to form CMOS transistor as example, wherein, described CMOS transistor is that nmos pass transistor and PMOS transistor form, and described nmos pass transistor and PMOS transistor can be high-k/metal gate transistor, can be also the transistor of conventional polysilicon gate.In manufacturing process, can be after nmos pass transistor and the transistorized grid of PMOS form, unified deposition of carrying out tensile stress layer; Then similar embodiment one or embodiment bis-, carries out cmp the tensile stress layer of gate surface is removed; Then make respectively nmos pass transistor and PMOS transistor, making when nmos pass transistor, with the same in the mode of embodiment mono-or embodiment bis-, part is removed the tensile stress layer of described gate side, and the while forms respectively groove in grid structure both sides; In the time making PMOS transistor, remove all tensile stress layers of described gate side, form respectively the groove of bottom-exposed Semiconductor substrate simultaneously in grid structure both sides; Then in the groove of nmos pass transistor and the transistorized grid structure of PMOS both sides, be packed into compressive stress layer together.The structure of final formation CMOS as shown in figure 11, comprising:
Be formed on grid structure in Semiconductor substrate 100 and be arranged in source region S and the drain region D of the Semiconductor substrate of described grid structure both sides, described Semiconductor substrate 100 comprises nmos transistor region and PMOS transistor area, and described grid structure is made up of gate dielectric layer 101 and gate material layers 106;
Cover the stressor layers 103 and 107 of the Semiconductor substrate of described grid structure and grid structure both sides, wherein, at nmos transistor region, compressive stress layer 107 is positioned at the two sides of described grid structure, in the Semiconductor substrate of grid structure both sides, be tensile stress layer 103, described compressive stress layer 107 is not less than the level height of the tensile stress layer in the Semiconductor substrate of grid structure both sides; In PMOS transistor area, compressive stress layer 107 covers the side of described grid structure, and covers described Semiconductor substrate 100 surfaces, in the Semiconductor substrate 100 except compressive stress layer 107 place places, is tensile stress layer 103.
Between described grid structure, there is interlayer dielectric layer 105, and on grid structure, there is interlayer dielectric layer 108.
On the source region S of described nmos pass transistor or drain region D, grid structure, also can also lead to realize and realize with other semiconductor device the contact hole 230 or 220 being electrically connected.
The above, be only preferred embodiment of the present invention, not the present invention done to any pro forma restriction.
Although the present invention discloses as above with preferred embodiment, but not in order to limit the present invention.Any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible variations and modification to technical solution of the present invention, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (15)
1. a manufacture method for nmos pass transistor, is characterized in that, comprising:
Semiconductor substrate is provided;
In described Semiconductor substrate, form grid structure, in the Semiconductor substrate of grid structure both sides, form source electrode and drain electrode;
Form tensile stress layer, described tensile stress layer covers side, upper surface and the described Semiconductor substrate of described grid structure;
Removal covers the tensile stress layer of described grid structure upper surface;
At least part of tensile stress layer of removing grid structure side, the tensile stress layer of grid structure side is removed to the height of the tensile stress layer in the Semiconductor substrate that is not less than grid structure both sides;
Be removed described tensile stress layer place in grid structure side and form compressive stress layer.
2. manufacture method as claimed in claim 1, is characterized in that, before source electrode and drain electrode form, the described grid structure forming is dummy gate, and it comprises high K medium layer and pseudo-gate material layer; After removal covers the tensile stress layer of described grid structure upper surface, also comprise and remove described pseudo-gate material layer to form breach, in described breach, fill workfunction layers, to form the step of high-k/metal gate.
3. manufacture method as claimed in claim 1, is characterized in that, described grid structure is multiple; After formation tensile stress layer covers described grid structure, before removal covers the tensile stress layer of described grid structure upper surface and grid structure side, also be included on described tensile stress layer and form dielectric layer, to fill up the step in the space between described multiple grid structure.
4. manufacture method as claimed in claim 3, it is characterized in that, form dielectric layer on described tensile stress layer after, adopt the mode of cmp to carry out overall planarization, described cmp proceeds to and exposes described grid structure to remove the tensile stress layer of grid structure upper surface.
5. manufacture method as claimed in claim 4, is characterized in that, after described cmp proceeds to and exposes described grid structure, utilizes etching technics to remove at least part of tensile stress layer of grid structure side.
6. manufacture method as claimed in claim 1, is characterized in that, described grid structure comprises gate insulator and gate material layer, and wherein, described gate insulator is silica, and described gate material layer is polysilicon.
7. manufacture method as claimed in claim 1, is characterized in that, before the step of described formation tensile stress layer, forms self-aligned metal silicate on the surface of described source electrode and drain electrode.
8. the transistorized manufacture method of CMOS, is characterized in that, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, there are at least two grid structures, be distributed in nmos transistor region and PMOS transistor area;
Upper surface and side at described semiconductor substrate surface and grid structure form tensile stress layer;
Remove the tensile stress layer of described grid structure upper surface;
Remove the part tensile stress layer at grid structure side place of nmos transistor region and the tensile stress layer at the grid structure side place of PMOS transistor area; Wherein, at nmos transistor region, tensile stress layer is removed to the height of the tensile stress layer in the Semiconductor substrate that is not less than grid structure both sides; In PMOS transistor area, tensile stress layer is removed to the Semiconductor substrate of the grid structure both sides of exposing PMOS transistor area;
Remove tensile stress layer place in the grid structure side of nmos transistor region and PMOS transistor area and fill compressive stress layer.
9. manufacture method as claimed in claim 8, is characterized in that, before tensile stress layer forms, the described grid structure forming is dummy gate, comprises high K medium layer and pseudo-gate material layer; After removal covers the tensile stress layer of described grid structure upper surface, also comprise and remove described pseudo-gate material layer to form breach, in described breach, fill workfunction layers, to form the step of high-k/metal gate.
10. manufacture method as claimed in claim 8, is characterized in that, described grid structure is multiple; After described formation tensile stress layer, before removing the tensile stress layer of described grid structure upper surface and grid structure side, be also included on described tensile stress layer and form dielectric layer, to fill up the space between described multiple grid structure.
11. manufacture methods as claimed in claim 10, it is characterized in that, form dielectric layer on described tensile stress layer after, adopt the mode of cmp to carry out overall planarization, described cmp proceeds to and exposes described grid structure to remove the tensile stress layer of grid structure upper surface.
12. manufacture methods as claimed in claim 11, is characterized in that, described grid structure comprises gate insulator and gate material layer, and wherein, described gate insulator is silica, and described gate material layer is polysilicon.
13. manufacture methods as claimed in claim 11, is characterized in that, before the step of described formation tensile stress layer, are formed with self-aligned metal silicate on the surface of described source electrode and drain electrode.
14. 1 kinds of nmos pass transistors, is characterized in that, comprising:
Be formed on grid structure in Semiconductor substrate and be positioned at the source-drain area of the Semiconductor substrate of described grid structure both sides;
Cover compressive stress layer and the tensile stress layer of the Semiconductor substrate of described grid structure and grid structure both sides, wherein, the Semiconductor substrate of described tensile stress layer overlies gate structure both sides, and one section of height starting from bottom of grid structure side, described compressive stress layer covers the described grid structure side of residual altitude, and higher than the height of the tensile stress layer in the Semiconductor substrate of grid structure both sides.
15. 1 kinds of CMOS transistors, is characterized in that, comprising:
Be formed on grid structure in Semiconductor substrate and be arranged in the source-drain area of the Semiconductor substrate of described grid structure both sides, described Semiconductor substrate comprises nmos transistor region and PMOS transistor area;
Cover compressive stress layer and the tensile stress layer of the Semiconductor substrate of described grid structure and grid structure both sides, wherein, at nmos transistor region, the Semiconductor substrate of described tensile stress layer overlies gate structure both sides, and one section of height starting from bottom of grid structure side, described compressive stress layer covers the described grid structure side of residual altitude; In PMOS transistor area, the Semiconductor substrate of described tensile stress layer overlies gate structure both sides, described compressive stress layer covers the side of described grid structure, and covers the surface of described Semiconductor substrate.
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