CN103853692B - A kind of multiprocessor data means of communication based on interruption judgment mechanism - Google Patents
A kind of multiprocessor data means of communication based on interruption judgment mechanism Download PDFInfo
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- CN103853692B CN103853692B CN201410088763.6A CN201410088763A CN103853692B CN 103853692 B CN103853692 B CN 103853692B CN 201410088763 A CN201410088763 A CN 201410088763A CN 103853692 B CN103853692 B CN 103853692B
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Abstract
The present invention relates to Embedded Application and data communication field, more particularly, to a kind of based on the multiprocessor data means of communication for interrupting judgment mechanism.The present invention is for prior art data storage and the problem of communication, there is provided a kind of based on the multiprocessor data means of communication for interrupting judgment mechanism, solves the problems, such as that abnormal interruption causes data-bag lost, realizes high real-time and highly reliable data interaction.The interrupt signal that the present invention is sent according to n ports random register by data receiver, receives corresponding data, while changing the state value of reception state depositor in the random register of n ports；Data sender before next write operation reads the state value of reception state depositor, and the history value that the data were operated with last time is compared, judge remaining（n‑1）Whether individual data receiver is properly received the data of data sender's transmission, enters line delay and waits or write again.
Description
Technical field
The present invention relates to Embedded Application and data communication field, more particularly, to a kind of based on many of interruption judgment mechanism
The processor data means of communication.
Background technology
In wide variety of today of embedded system, with level of integrated system, complexity and synthesization degree increasingly
Improve, be frequently necessary to design the complication system that multiprocessor collaboration completes signal processing and control.Multicomputer system designs skill
The advantage of art is, can pass through being uniformly distributed for computing capability, make system that there is preferable redundant ability, processes faster fast
Degree, modular architecture, and simplify programming difficulty.Just because of the application of multicomputer system is more and more extensive, how
Resolving multiprocessor data and sharing also becomes more and more important with interaction problems.Communication party between common different processor
Formula includes by communication register communication mode, by fifo device (FIFO) communication mode, deposits by double-port random
Reservoir communication mode, serial communication mode etc. communication.If necessary to be counted in a large number between two processors
According to transmission, it is then optimal selection scheme by double-port RAM (DPRAM).Double-port RAM
DPRAM is different from common single port RAM, and DPRAM chips have two groups of data/address bus, two group address buses, two groups of controlling bus, only
If it were not for same memory element is accessed simultaneously, two ports are allowed for any unit in piece while carrying out independent read/write behaviour
Make, and do not interfere with each other.
Data communication is realized by double-port RAM DPRAM, is divided into inquiry when implementing again and is interrupted two
The mechanism of kind, the former is host computer（One side of acquisition information）Timing is periodically read DPRAM contents and is processed, this
Mechanism Design is simple, has the disadvantage that real-time is poor, it is adaptable to the not high application of requirement of real-time；The latter is based on interrupt mechanism, real
When property is higher, has the disadvantage to rely on and interrupts producing and response mechanism, under the conditions of complicated applications, sporadic lose disruption and can make
Into data-bag lost.It is that data sender writes data based on the generalized flowsheet of interrupt mechanism, then connects to data receiver's triggering
Receive data interruption.Data receiver's respective interrupt, and reading operation is executed, simply " reception state depositor " is set to afterwards
" reception state depositor " data are judged when sender writes several again, and enter line delay etc. according to its result by one constant
Treat or write again, but the normal operation of above flow process depends on the correct response of interrupt mechanism.But, case above is only
Apply under reduced condition（Including：The electromagnetic environment interference of optimization, host computer is without interrupt nesting mechanism）, data transmit-receive both sides
Can normally send, respond and interrupt and complete data communication, then the communication mechanism for simplifying can achieve reliable communication.Practical engineering application
In truth be, due to electromagnetic interference, interrupt nesting, software scheduling, resource contention many reasons, objective reality sender
Fail correct to interrupting or recipient is unable to normal response interruption, i.e., phenomenon of " losing interruption ", so as to cause data-bag lost.
Content of the invention
The technical problem to be solved is：In for multi-processor Embedded System, based on DPRAM and middle off line
Disruption is lost in the communication means of system, there is provided a kind of based on the multiprocessor data means of communication for interrupting judgment mechanism, in this
Disconnected response is adjudicated and reissues mechanism, is to solve the problems, such as that abnormal interruption causes data-bag lost, is being based on n ports random access memory
（DPRAM）" interrupt do not respond " concept is introduced in communication mechanism, can effectively solving different due to communicating caused by interrupt response problem
Often, high real-time and highly reliable data interaction are realized.
The technical solution used in the present invention is as follows：
A kind of multiprocessor data means of communication based on interruption judgment mechanism include：N processor passes through n ports respectively
Random access memory carries out data transmission, wherein any one processor as data sender, remaining（n-1）Individual processor conduct
（n-1）Data receiver, n ports random access memory include n data length register, n reception state depositor with
And n down trigger depositor, each processor described correspond to respectively data length register, reception state depositor with
And down trigger depositor, which concretely comprises the following steps：
Step 1：Data sender passes through n ports random access memory, to remaining（n-1）Individual data debit is sent out with interrupt mode
Send data；
Step 2：The interrupt signal that data receiver is sent according to n ports random register, receives corresponding data, while repairing
Change the state value of reception state depositor in the random register of n ports；
Step 3：Data sender reads the state value of reception state depositor before next write operation, and by the data
The history value of operation was compared with last time, judged remaining（n-1）Receiving data sender sends individual data receiver
Data, enter line delay and wait or write again；
Step 4：Repeat step 3, realizes the transmission of data sender and data receiver's data.
Step 1 concrete steps include：Any one data sender sends data to（n-1）Individual data receiver
When, n ports random access memory is corresponding（n-1）Individual reception state depositor storage state variable is respectively Xi, n deposited port at random
Reservoir is corresponding（n-1）Individual data length register difference record data sender sends the length of data, while n ports are random
In memorizer（n-1）Individual down trigger depositor is written into interrupt signal value, and then n ports random register is to remaining（n-1）
Individual data receiver sends interrupt signal, Xi>1, the XiIt is a cycle values.
Shown step 2 concrete steps include：
Step 21：（n-1）When individual data receiver receives interrupt signal, will be corresponding for n ports random access memory（n-1）
Individual reception state depositor storage state variable XiBusy condition flag bit is changed to, according to data length in the random access memory of n ports
Numerical value in depositor, data receiver read the data stored in the random access memory of n ports；
Step 22：（n-1）After the completion of individual data receiver reads n ports random access memory data, by n ports random storage
In device（n-1）Busy condition flag bit in individual reception state memorizer is changed to Xi+1= Xi+ 1, will be in the random access memory of n ports
（n-1）Individual reception state buffer status are changed to responsive state；If data receiver does not receive interrupt signal, reception state is posted
Storage Xi+1= XiIdentical, i.e., in the random access memory of n ports, reception state depositor is non-responsive state.
Step 3 concrete steps：
When data sender sends data to n ports random access memory again, judge in the random access memory of n ports（n-
1）Individual reception state depositor storage state variable Xi+1The state variable of storage during transmission data last with data sender
XiRelation：If Xi+1=Xi+ 1, then it represents that data receiver's response have received the data of data sender；If Xi+1=Xi, represent number
According to the data that recipient does not respond receiving data sender, Xi+1=busy condition, illustrates that recipient is reading data.
The multiport random access memory is double-port RAM, and data communication method is specifically included：
Step 111：Reception state deposit when data sender sends data to data receiver, in dual-ported memory
Device storage state variable is Xi, in dual-ported memory, data length register records data sender sends the length of data,
Down trigger depositor in dual-ported memory is written into interrupt signal value simultaneously, and then dual ported register is to data receiver
Side sends interrupt signal, when data sender for the first time sends data to dual-ported memory, now Xi>1, the XiIt is individual
Cycle values (now i>0)；
Step 112：When data receiver receives interrupt signal, the reception state depositor in dual-ported memory is deposited
Storage state variable XiBusy condition flag bit is changed to, according to the numerical value in data length depositor in dual-ported memory, data connect
Debit reads the data stored in dual-ported memory；
Step 113：After the completion of data receiver reads dual-ported memory data, by reception state in dual-ported memory
Busy condition flag bit in memorizer is changed to Xi+1=Xi+ 1, reception state buffer status will be changed in dual-ported memory
Responsive state；If data receiver does not receive interrupt signal, reception state depositor Xi+1=XiValue is identical, i.e., at dual-port
In reason device, reception state depositor is non-responsive state；
Step 114：When data sender sends data to dual-ported memory again, judge to connect in dual-ported memory
Receive the storage state variable X now of status registeri+1The secondary numerical value X of data is sent with data senderiWhether consistent, if
Inconsistent, then it represents that data receiver's response have received the data of data sender；Otherwise, represent that data receiver does not respond to connect
Receive the data of data sender；
Step 115：Repeat step 114, realizes the transmission of data sender and data receiver's data.
In sum, as a result of above-mentioned technical proposal, the invention has the beneficial effects as follows：
1）After the completion of data receiver's reading, one " variable " is write at " in reception state depositor " and replace constant, this
In arrange variable be " 1～Xi" between loop count.Data sender reads reception state deposit before next write operation
The variate-value of device, and the history value that the data were operated with last time is compared, and take respective operations.
2）Data interaction is completed based on interrupt mechanism；By data length depositor, down trigger depositor, reception state
The special function registers such as depositor, the interaction mode of characterize data communication process；There is busy mark, interrupt carrying out when not responding
Wait, interrupt losing judgement and the mechanism such as reissue, it is ensured that while data logical real-time, effectively improve the reliability of data communication
Property.
Description of the drawings
Examples of the present invention will be described by way of reference to the accompanying drawings, wherein：
Fig. 1 dual processor data communication theory diagrams.
Fig. 2 double-port RAM depositor schematic diagrams.
Fig. 3 is three port random access memory Principle of Communication block diagrams.
Specific embodiment
All features disclosed in this specification, or disclosed all methods or during the step of, except mutually exclusive
Feature and/or step beyond, can combine by any way.
This specification（Including any accessory claim, summary and accompanying drawing）Disclosed in any feature, except non-specifically is chatted
State, can equivalent by other or with similar purpose alternative features replaced.I.e., unless specifically stated otherwise, each feature
It is an example in a series of equivalent or similar characteristics.
Data sender：By the place with down trigger depositor, data length depositor, reception state depositor etc.
Reason device is realized.Before data sender carries out data transmission starting with dual-ported memory, data sender is met with address first
Connection set up by the dual-ported memory of requirement, and then data sender passes through data line transfer data to dual-ported memory.So
Afterwards the down trigger depositor of n ports random access memory, data length depositor, reception state depositor are operated.
Data receiver：By the place with down trigger depositor, data length depositor, reception state depositor etc.
Reason device is realized.Data receiver is carried out data transmission before beginning with dual-ported memory, first data receiver side and address character
Close the dual-ported memory for requiring and set up connection, then data receiver passes through the interruption letter for responding double-port RAM
Number, then the data for receiving double-port RAM by data/address bus are deposited to the down trigger of n ports random access memory
Device, data length depositor, reception state depositor are operated.
N is the integer more than or equal to 2.N ports random access memory can realize the two-way between any 2 processors
Letter.The n ports random access memory can pass through programmable gate array（FPGA）Realize or special IC（ASIC）Realize.
Which has n group depositors（Including triggering interrupt storage, data length depositor and reception state depositor）, any 2
Processor two-way communication so that n ports random access memory divides 2 sections of independent address spaces, two-way two-by-two between n processor
Letter needs 2n section independent address spaces altogether.
Data sender can be data sender or data receiver, and corresponding data receiver can be that data connect
Debit or data sender.In as shown in Figure 1, Figure 2, double-port random depositor includes the data/address bus/ground of A ports and B ports
Location bus, Read-write Catrol and interrupt signal etc..DPRAM address spaces distribute：There is two ports of A/B independent specific function to post
Storage.In processor, AB represents that address bus, DB represent that data/address bus, CB represent controlling bus（Refer generally to read-write）.Double
In the random access memory of port, A0L to A14L is address bus, and A0R to A14R is address bus.D0L to D15L represents that data are total
Line, D0R to D15R represent data/address bus.RD-L, RD-R represent read signal.WR-LWR-R represents write signal.INT-L, INT-R table
Show interrupt signal.
Table 1：The one group of special function register list of n ports random access memory:
Embodiment one：This method can be used for the data transfer between 3 processors, between wherein any 2 processors
Achievable two-way communication.Its feature is that based on three port random access memory the three ports random access memory can pass through programmable
Logic gate array（FPGA）Realize or special IC（ASIC）Realize, which has three groups of depositors（At least include in triggering
Disconnected memorizer, data length depositor and reception state depositor）.The two-way communication of any two processor so that three ends
Mouth random access memory divides 2 sections of independent address spaces, realizes that the two-way communication arbitrarily between any two in three processors is needed altogether
6 sections of independent address spaces are wanted, the communication process of any two processor is similar with above-mentioned communication process.Theory diagram is as follows, note
3 processor two-way communications two-by-two of meaning, need 6 interrupt signals altogether, and in figure, INT-itoj represents the i-th processor（CPUi）To
J processors（CPUj）The interrupt signal (i, j=1,2,3, and i ≠ j) during data is sent, as shown in Figure 3.AB, AB-1, AB-2 with
And AB-3 shows data/address bus.DB, DB-1, DB-2 and DB-3 represent address bus.CB represents controlling bus, is often referred to read signal
And write signal.
Embodiment two：This method can be used for the data transfer between 4 processors, between wherein any 2 processors
Achievable two-way communication.Its feature is based on four port stores, can pass through programmable gate array（FPGA）Realize or
Special IC（ASIC）Realize, which has four groups of depositors.The two-way communication process of any two processor is logical with above-mentioned
Letter flow journey is similar to, and any one processor can receive the information of other three processors, during a processor needs three
Break signal, thus four port stores have 12 interrupt signal pins.
The invention is not limited in aforesaid specific embodiment.The present invention is expanded to and any is disclosed in this manual
New feature or any new combination, and the arbitrary new method that discloses or the step of process or any new combination.
Claims (3)
1. a kind of based on the multiprocessor data means of communication for interrupting judgment mechanism, it is characterised in that to include：N processor difference
Carried out data transmission by n ports random access memory, wherein any one processor as data sender, at remaining n-1
Used as n-1 data receivers, n ports random access memory includes that n data length register, n reception state are posted to reason device
Storage and n down trigger depositor, each processor correspond to data length register, a reception state depositor respectively
And down trigger depositor, which concretely comprises the following steps：
Step 1：Data sender sends number to remaining n-1 data debit with interrupt mode by n ports random access memory
According to；
Step 2：The interrupt signal that data receiver is sent according to n ports random register, receives corresponding data, while changing n
The state value of reception state depositor in the random register of port；
Step 3：Data sender before next write operation reads the state value of reception state depositor, and posts state is received
The history value that the state value of storage was operated with last time is compared, and judges remaining n-1 data receiver whether send out by receiving data
The data that the side of sending sends, enter line delay and wait or write again；
Step 4：Repeat step 3, realizes the transmission of data sender and data receiver's data；
Step 2 concrete steps include：
Step 21：When n-1 data receiver receives interrupt signal, shape is received by corresponding for n ports random access memory n-1
State depositor storage state variable Xi" busy condition " flag bit is changed to, according to data length depositor in the random access memory of n ports
In numerical value, data receiver reads the data stored in the random access memory of n ports；
Step 22：After the completion of n-1 data receiver reads n ports random access memory data, by n- in the random access memory of n ports
Busy condition flag bit in 1 reception state memorizer is changed to Xi+1= Xi+ 1, will n-1 reception in the random access memory of n ports
Status register state is changed to responsive state；If data receiver does not receive interrupt signal, reception state depositor Xi+1= Xi
Identical, i.e., in the random access memory of n ports, reception state depositor is non-responsive state；
Step 3 concrete steps：
When data sender sends data to n ports random access memory again, judge that n-1 connects in the random access memory of n ports
Receive status register storage state variable XiState variable X of storage during transmission data last with data senderiPass
System：If Xi+1=Xi+ 1, then it represents that data receiver's response have received the data of data sender；If Xi+1=Xi, represent data receiver
Side does not respond the data of receiving data sender, Xi+1Represent " busy condition ", illustrate that recipient is reading data.
2. according to claim 1 a kind of based on the multiprocessor data means of communication for interrupting judgment mechanism, its feature exists
Include in step 1 concrete steps：When any one data sender sends data to n-1 data receiver, n ports with
The corresponding n-1 reception state depositor storage state variable of machine memorizer is respectively Xi, the corresponding n- of n ports random access memory
1 data length register difference record data sender sends the length of data, while n-1 in the random access memory of n ports
Down trigger depositor is written into interrupt signal value, during then n ports random register is sent to remaining n-1 data receiver
Break signal, Xi>1, the XiIt is a cycle values.
3. according to claim 1 a kind of based on the multiprocessor data means of communication for interrupting judgment mechanism, its feature exists
It is double-port RAM in n ports random access memory, data communication method is specifically included：
Step 111：Reception state deposit when data sender sends data to data receiver, in double-port RAM
Device storage state variable is Xi, in double-port RAM, data length register records data sender sends the length of data
Degree, while the down trigger depositor in double-port RAM is written into interrupt signal value, then dual ported register to
Data receiver sends interrupt signal, when data sender for the first time sends data to double-port RAM, now Xi
>1, the XiIt is a cycle values；
Step 112：When data receiver receives interrupt signal, the reception state depositor in double-port RAM is deposited
Storage state variable XiBusy condition flag bit is changed to, according to the numerical value in data length depositor in double-port RAM, number
The data stored in double-port RAM are read according to recipient；
Step 113：After the completion of data receiver reads double-port RAM data, will receive in double-port RAM
Busy condition flag bit in status register is changed to Xi+1=Xi+ 1, will reception state depositor in double-port RAM
State is changed to responsive state；If data receiver does not receive interrupt signal, reception state depositor Xi+1=XiValue is identical, i.e.,
In dual-port processor, reception state depositor is non-responsive state；
Step 114：When data sender sends data to double-port RAM again, double-port RAM is judged
The storage state variable X now of middle reception state depositori+1Receive status register storage state variable with data sender
XiWhether consistent, if inconsistent, then it represents that data receiver's response have received the data of data sender；Otherwise, data are represented
Recipient does not respond the data of receiving data sender；
Step 115：Repeat step 114, realizes the transmission of data sender and data receiver's data.
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| CN111679945A (en) | 2020-06-12 | 2020-09-18 | 地平线(上海)人工智能技术有限公司 | Processor detection method, device and computer readable storage medium |
| CN114691595B (en) * | 2022-04-06 | 2023-03-28 | 北京百度网讯科技有限公司 | Multi-core circuit, data exchange method, electronic device, and storage medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1512373A (en) * | 2002-12-26 | 2004-07-14 | 华为技术有限公司 | A Method for Multi-CPU Communication |
| CN101013414A (en) * | 2007-02-14 | 2007-08-08 | 中兴通讯股份有限公司 | Communication method between two processors |
| CN101689158A (en) * | 2007-07-09 | 2010-03-31 | 惠普发展公司，有限责任合伙企业 | Data packet processing method for a multi core processor |
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| CA2126174C (en) * | 1993-06-30 | 2003-01-21 | David Thielen | Method and system for interrupt-responsive execution of communications protocols |
| JPH0816535A (en) * | 1994-06-24 | 1996-01-19 | Toshiba Corp | Cpu system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1512373A (en) * | 2002-12-26 | 2004-07-14 | 华为技术有限公司 | A Method for Multi-CPU Communication |
| CN101013414A (en) * | 2007-02-14 | 2007-08-08 | 中兴通讯股份有限公司 | Communication method between two processors |
| CN101689158A (en) * | 2007-07-09 | 2010-03-31 | 惠普发展公司，有限责任合伙企业 | Data packet processing method for a multi core processor |
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