CN103839891A - Semiconductor structure and manufacturing method thereof - Google Patents

Abstract

The invention provides a method for manufacturing a semiconductor structure. The method includes the following steps: providing an SOI substrate, forming a gate stack on the SOI substrate, and forming sidewalls on the side walls of the gate stack; Forming a polycrystalline Si _1-x Ge _x layer on the SOI substrate; annealing to form source/drain regions. Correspondingly, the present invention also provides a semiconductor structure. The invention reduces the influence on the doping distribution of the channel and the source/drain extension region by forming the source/drain region of polycrystalline Si _{1-x Gex} at a relatively low temperature, and improves device performance and reliability.

Description

A kind of semiconductor structure and its manufacturing method

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a manufacturing method thereof.

Background technique

In order to improve the performance and integration of integrated circuit chips, the feature size of devices has been continuously reduced according to Moore's law, and has now entered the nanometer scale. As the size of devices shrinks, power consumption and leakage current become the most concerned issues. CMOS devices prepared by silicon on insulator SOI (Silicon on Insulator) have many advantages such as high speed, low power consumption, high integration, radiation resistance and no self-locking effect, and have become the preferred structure of deep submicron and nanoscale MOS devices. . In order to further improve the performance of CMOS devices, the SOI structure of ultra-thin silicon film (≤100nm) is often required to make the device channel in a fully depleted state. CMOS circuits prepared with this ultra-thin SOI (UTSOI) structure can improve DIBL ( Drain Induced Barrier Lowering (Drain Induced Barrier Lowering) and other short channel effects, improving the sub-threshold characteristics of the device, reducing the static power consumption of the circuit, and eliminating the kink effect, etc.

However, since the top silicon film (≤100nm) of ultra-thin SOI is very thin, resulting in a large source/drain region series resistance and contact resistance, metal silicide may consume the entire silicon film, but it is still difficult to reduce the source/drain Area series resistance and contact resistance, and may also cause a large leakage current. By forming a raised source/drain (Raised Source/Drain, RSD), the contact resistance of the source/drain region can be further reduced, the driving current of the device can be increased, and the performance of the device can be improved. In the prior art, the commonly used method for forming the raised source/drain is selective epitaxial single crystal silicon, germanium, etc., and the process temperature is generally above 650°C. The redistribution of dopants in the impurity region may cause problems such as low threshold voltage or channel punch-through short circuit. Reducing the process temperature for raising the source/drain and reducing its influence on the doping profile has become an important challenge for the raising source/drain technology.

Contents of the invention

The purpose of the present invention is to at least solve the above-mentioned technical defects, provide a semiconductor device manufacturing method and its structure, reduce the process temperature for raising the source/drain growth, reduce its influence on the doping distribution of the semiconductor structure, and improve the performance and performance of the semiconductor device. reliability.

To achieve the above object, the invention provides a method for manufacturing a semiconductor structure, the method comprising the following steps:

(a) providing an SOI substrate, forming a gate stack on the SOI substrate, and forming sidewalls on the sidewalls of the gate stack;

(b) Forming a polycrystalline Si _1-x Ge _x layer on the exposed SOI substrate;

(c) Annealing to form source/drain regions in the polycrystalline Si _1-x Ge _x layer on the SOI substrate.

Wherein, before or after forming the side wall in the step (a), the step also includes:

Using the gate stack as a mask, a source/drain extension region is formed.

Another aspect of the present invention also proposes a semiconductor structure, including an SOI substrate, a gate stack, side walls, and source/drain regions, wherein:

The SOI substrate includes a base layer, an insulating layer on the base layer, and a device layer on the insulating layer;

the gate stack is located on the SOI substrate;

the sidewall is located on the sidewall of the gate stack;

The source/drain region is formed on the SOI substrate at two sides of the gate stack, and its material is polycrystalline Si _1-x Ge _x .

According to the semiconductor structure and its manufacturing method provided by the present invention, the source/drain region can be formed at a lower temperature, which reduces its influence on the doping distribution of the semiconductor structure, and reduces the series resistance and contact resistance of the source/drain region , avoid problems such as threshold voltage reduction, channel punch-through short circuit, etc., and improve the performance and reliability of semiconductor devices.

Description of drawings

The above and/or additional aspects and advantages of the present invention will become apparent and easy to understand from the following description of the embodiments in conjunction with the accompanying drawings, wherein:

Fig. 1 is the flow chart of a specific embodiment of the manufacturing method of semiconductor structure according to the present invention;

2 to 8 are schematic cross-sectional structural views of the semiconductor structure at various manufacturing stages during the process of manufacturing the semiconductor structure according to the method shown in FIG. 1 .

Detailed ways

Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention. The following disclosure provides many different embodiments or examples for implementing different structures of the present invention. To simplify the disclosure of the present invention, components and arrangements of specific examples are described below. Of course, they are only examples and are not intended to limit the invention. Furthermore, the present invention may repeat reference numerals and/or letters in different instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or arrangements discussed. In addition, various specific process and material examples are provided herein, but one of ordinary skill in the art will recognize the applicability of other processes and/or the use of other materials. Additionally, configurations described below in which a first feature is "on" a second feature may include embodiments where the first and second features are formed in direct contact, and may include additional features formed between the first and second features. For example, such that the first and second features may not be in direct contact.

FIG. 1 is a flowchart of a method for manufacturing a semiconductor structure according to the present invention, and FIGS. 2 to 8 are schematic cross-sectional views of various stages of manufacturing a semiconductor structure according to the process shown in FIG. 1 according to an embodiment of the present invention. The method for forming the semiconductor structure in FIG. 1 will be specifically described below with reference to FIGS. 2 to 8 . It should be noted that the drawings of the embodiments of the present invention are only for illustrative purposes, and therefore are not necessarily drawn to scale.

Referring to FIG. 2 to FIG. 6 , in step S101 , an SOI substrate 100 is provided, a gate stack is formed on the SOI substrate 100 , and sidewalls 230 are formed on sidewalls of the gate stack. As shown in FIG. 2 , the SOI substrate 100 includes a base layer 101 , an insulating layer 102 on the base layer 101 , and a device layer 103 on the insulating layer 102 .

In this embodiment, the base layer 101 is single crystal silicon. In other embodiments, the base layer 101 may also include other basic semiconductors such as germanium, or other compound semiconductors, such as silicon carbide, gallium arsenide, indium arsenide or indium phosphide. Typically, the thickness of the base layer 101 may be about but not limited to several hundreds of microns, such as a thickness range of 0.2mm-1mm.

The insulating layer 102 can be made of SiO ₂ , silicon nitride, Al ₂ O ₃ or any other suitable insulating material. Typically, the thickness of the insulating layer 102 ranges from 10 nm to 300 nm.

The device layer 103 may be any one of the semiconductors included in the base layer 101 . In this embodiment, the device layer 103 is single crystal silicon. In other embodiments, the device layer 103 may also include other basic semiconductors or compound semiconductors. Typically, the thickness of the device layer 103 ranges from 10 nm to 100 nm. In this embodiment, the SOI substrate 100 is an ultra-thin SOI (Ultra-Thin SOI, UTSOI) substrate with an extremely thin device layer, usually less than 10 nm in thickness, which is beneficial to control the depth of the source/drain region and form an ultra-thin SOI layer. Shallow junctions, thereby reducing short channel effects.

In particular, isolation regions, such as shallow trench isolation (STI) structures 120 are formed in the SOI substrate 100 to electrically isolate contiguous semiconductor devices.

The gate stack is formed on the SOI substrate 100 , which includes a gate dielectric layer 210 and a gate 220 , as shown in FIG. 3 . Optionally, the gate stack may further include a capping layer (not shown in the figure) covering the gate, for example, by depositing silicon nitride, silicon oxide, silicon oxynitride, silicon carbide and combinations thereof. formed to protect the top region of the gate 220 from being damaged in subsequent processes. The gate dielectric layer 210 is located on the SOI substrate 100 and may be a high-K dielectric, for example, HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al ₂ O ₃ , La ₂ O ₃ , ZrO ₂ , LaAlO one or a combination thereof. In another embodiment, it may also be a thermal oxide layer, including silicon oxide and silicon oxynitride; the thickness of the gate dielectric layer 210 may be 1 nm˜10 nm, such as 5 nm or 8 nm. Then form the gate 220 on the gate dielectric layer 210, the gate 220 can be heavily doped polysilicon formed by deposition, or form a work function metal layer (for NMOS, such as TaC, TiN, TaTbN, TaErN , TaYbN, TaSiN, HfSiN, MoSiN, _RuTax , NiTax _, etc., for PMOS, such as _MoNx , TiSiN, TiCN, TaAlC, TiAlN, TaN, _PtSix , Ni ₃ Si, Pt, Ru, Ir, Mo, HfRu, RuO _x ), whose thickness can be 1nm-20nm, such as 3nm, 5nm, 8nm, 10nm, 12nm or 15nm, and then form heavily doped polysilicon, Ti, Co, Ni, Al, W or Its alloy or the like forms the gate 220 .

As shown in FIG. 4 , the sidewalls 230 are formed on the sidewalls of the gate stacks for separating the gate stacks. The sidewall 230 may be formed of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, combinations thereof, and/or other suitable materials. The side wall 230 may have a multi-layer structure. The sidewall 230 may be formed by a deposition-etching process, and its thickness may range from 10 nm to 100 nm, such as 30 nm, 50 nm or 80 nm.

Optionally, in step S101 , further comprising forming a source/drain extension region 300 after forming the gate stack or forming the spacer 230 . A shallow source/drain extension region 300 is formed in the substrate 100 by low-energy implantation, and P-type or N-type dopants or impurities can be implanted into the substrate 100. For example, for PMOS, the source/drain extension Region 300 may be P-type doped Si; for NMOS, source/drain extension region 300 may be N-type doped Si. Optionally, the semiconductor structure is then annealed to activate the doping in the source/drain extension region 300 . The annealing can be formed by other suitable methods including rapid annealing and spike annealing. In some other embodiments of the present invention, the annealing operation may also be performed after the source/drain regions are formed. Due to the shallow thickness of the source/drain extension region 300, the short channel effect can be effectively suppressed. FIG. 5 is a cross-sectional view of the structure after forming the gate stack and implanting the gate stack as a mask to form the source/drain extension region 300. FIG. After the side wall 230 , a cross-sectional view of the structure after forming the source/drain extension region 300 .

Referring to FIG. 1 and FIG. 7 , step S102 is performed to form a polycrystalline Si _1-x Ge _x layer 310 on the SOI substrate 100 . The method for forming the polycrystalline Si _1-x Ge _x layer 310 includes plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTCVD), through the gas flow, gas pressure , equipment power, etc. can be adjusted to control the process temperature for forming the polycrystalline Si _1-x Ge _x layer 310 below 450°C, and the typical process temperatures are 425°C and 400°C. Compared with selective epitaxial single-crystal Si and Ge (process temperature ≥ 650°C), the method of forming polycrystalline Si _1-x Ge _x layer by chemical vapor deposition has less influence on the existing doping distribution of the semiconductor structure, which is beneficial to Improve the performance and reliability of semiconductor devices. Typically, the reaction gas used to form the polycrystalline Si _1-x Ge _x layer 310 is SiH ₄ , GeH ₄ , by controlling the gas flow rate or gas percentage of SiH ₄ or GeH4, the Si and Ge in Si _1-x Ge _x can be adjusted. Component ratio. In this embodiment, the value of x is 0.2-0.7. The thickness of the polycrystalline Si _1-x Ge _x layer 310 cannot be higher than the height of the gate stack, and its thickness ranges from 50 nm to 200 nm. In this embodiment, the doping of the polycrystalline Si _1-x Ge _x layer 310 is realized by performing in-situ doping when the polycrystalline Si _1-x Ge _x layer 310 is formed; in the present invention In some other embodiments, ion implantation may be performed after the polycrystalline Si _1-x Ge _x layer 310 is formed to achieve doping of the polycrystalline Si _1-x Ge _x layer 310 . Wherein the doping concentration of the polycrystalline Si _1-x Ge _x is 10 ¹⁸ ~ 2x10 ²⁰ cm ^-3 , for NMOS, the doping type of the Si _1-x Ge _x layer is N type; for PMOS, the polycrystalline The doping type of the Si _1-x Ge _x layer is P type.

Referring to FIG. 1 and FIG. 8 , in step S103 , annealing is performed, and the polycrystalline Si _1-x Ge _x layer is patterned to form source/drain regions 310 . The annealing can adopt other suitable methods including rapid annealing, spike annealing, etc., and the process temperature is 450°C-550°C. In step S102, the Si _1-x Ge _x layer formed by methods such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTCVD) may be amorphous , by annealing to restore its crystal structure and eliminate defects, thereby obtaining a polycrystalline Si _1-x Ge _x layer. On the other hand, the donor and acceptor impurities are activated by annealing. Subsequently, the polycrystalline Si _1-x Ge _x layer is patterned by a suitable method such as dry etching RIE, and the source/drain region 310 is formed on the etched Si _1-x Ge _x layer.

Then complete the fabrication of the semiconductor structure according to the steps of the conventional semiconductor manufacturing process, for example, forming metal silicide on the source/drain region; depositing an interlayer dielectric layer to cover the source/drain region and the gate stack; etching the The interlayer dielectric layer exposes the source/drain region to form a contact hole, filling the contact hole with metal; and subsequent process steps such as multi-layer metal interconnection.

The present invention also provides a semiconductor structure. As shown in FIG. 8 , the semiconductor structure includes an SOI substrate 100 , gate stacks, sidewalls 230 , and source/drain regions 310 . Wherein the SOI substrate 100 includes a base layer 101, an insulating layer 102 on the base layer 101 and a device layer 103 on the insulating layer 102; the gate stack is located on the SOI substrate 100 above; the sidewall 230 is located on the sidewall of the gate stack; the source/drain region 310 is formed on the SOI substrate 100 and located on both sides of the gate stack, and its material is Polycrystalline Si _1-x Ge _x . The thickness of the polycrystalline Si _1-x Ge _x source/drain region is 50nm-200nm, and the value of x is 0.2-0.7. The doping concentration of the polycrystalline Si _1-x Ge _x is 10 ¹⁸ ~ 2x10 ²⁰ cm ^-3 , for NMOS, the doping type of the polycrystalline Si 1-x Ge _x layer is N type; for PMOS, the doping type of the polycrystalline Si _1-x Ge x layer is N-type; The doping type of the polycrystalline Si _1-x Ge _x layer is P type. The source/drain region 310 is a raised source/drain structure, that is, the top of the source/drain region 310 is higher than the bottom of the gate stack, which is conducive to reducing the series resistance and contact resistance of the source/drain region. Polycrystalline Si Compared with polysilicon, _1-x Ge _x has a smaller contact resistance, which further improves the current driving capability of semiconductor devices.

Optionally, the semiconductor structure further includes a source/drain extension region 300 , the source/drain extension region 300 is embedded in the device layer 103 and sandwiched between the source/drain region 310 and the insulating layer 102 .

Although the example embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made to these embodiments without departing from the spirit and scope of the invention as defined by the appended claims. For other examples, those of ordinary skill in the art will readily understand that the order of process steps may be varied while remaining within the scope of the present invention.

In addition, the scope of application of the present invention is not limited to the process, mechanism, manufacture, material composition, means, method and steps of the specific embodiments described in the specification. From the disclosure of the present invention, those of ordinary skill in the art will easily understand that for the processes, mechanisms, manufacturing, material compositions, means, methods or steps that currently exist or will be developed in the future, they are implemented in accordance with the present invention Corresponding embodiments described which function substantially the same or achieve substantially the same results may be applied in accordance with the present invention. Therefore, the appended claims of the present invention are intended to include these processes, mechanisms, manufacture, material compositions, means, methods or steps within their protection scope.

Claims (10)

1. a manufacture method for semiconductor structure, the method comprises the following steps:

(a) provide SOI substrate, on described SOI substrate, form gate stack, form side wall at the sidewall of described gate stack;

(b) on the SOI substrate exposing, form polycrystalline Si _1-xge _xlayer;

(c) annealing, the polycrystalline Si on SOI substrate _1-xge _xin layer, form source/drain region.

2. method according to claim 1, in step (b), forms described polycrystalline Si _1-xge _xthe method of layer is plasma-reinforced chemical vapor deposition (PECVD), low-pressure chemical vapor phase deposition (LPCVD), rapid heat chemical vapour deposition (RTCVD).

3. method according to claim 2, wherein said polycrystalline Si _1-xge _xthe thickness of layer is 50nm～200nm, and the value of x is 0.2～0.7.

4. method according to claim 1, wherein in step (b), by the method for in-situ doped or follow-up Implantation, to described polycrystalline Si _1-xge _xlayer adulterates.

5. method according to claim 4, wherein said polycrystalline Si _1-xge _xdoping content be 10 ¹⁸～2x10 ²⁰cm ^-3, for NMOS, described polycrystalline Si _1-xge _xthe doping type of layer is N-type; For PMOS, described polycrystalline Si _1-xge _xthe doping type of layer is P type.

6. method according to claim 1, wherein, in step (a), before or after forming side wall, also comprises step:

Taking described gate stack as mask, formation source/drain extension region.

7. a semiconductor structure, this structure comprises SOI substrate, gate stack, side wall, source/drain region, wherein:

Described SOI substrate comprises basalis, is positioned at the insulating barrier on described basalis and is positioned at the device layer on described insulating barrier;

Described gate stack is positioned on described SOI substrate;

Described side wall is positioned on the sidewall of described gate stack;

Described source/drain region is formed on described SOI substrate, is positioned at the both sides of described gate stack, and its material is polycrystalline Si _1-xge _x.

8. semiconductor structure according to claim 7, wherein, described polycrystalline Si _1-xge _xthe thickness of source/drain region is 50nm～200nm, and the value of x is 0.2～0.7.

9. semiconductor structure according to claim 7, wherein, described polycrystalline Si _1-xge _xdoping content be 10 ¹⁸～2x10 ²⁰cm ^-3, for NMOS, described polycrystalline Si _1-xge _xthe doping type of layer is N-type; For PMOS, described polycrystalline Si _1-xge _xthe doping type of layer is P type.

10. semiconductor structure according to claim 7, wherein, also comprises source/drain extension region, and described source/drain extension region is embedded in the device layer of described SOI substrate, is sandwiched between described source/drain region and insulating barrier.

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