CN103824828A - Packaging support plate and manufacturing method thereof - Google Patents
Packaging support plate and manufacturing method thereof Download PDFInfo
- Publication number
- CN103824828A CN103824828A CN201410078290.1A CN201410078290A CN103824828A CN 103824828 A CN103824828 A CN 103824828A CN 201410078290 A CN201410078290 A CN 201410078290A CN 103824828 A CN103824828 A CN 103824828A
- Authority
- CN
- China
- Prior art keywords
- dielectric layer
- semiconductor substrate
- silicon
- layer
- encapsulating carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 25
- 238000004806 packaging method and process Methods 0.000 title abstract 4
- 239000000758 substrate Substances 0.000 claims abstract description 90
- 239000004065 semiconductor Substances 0.000 claims abstract description 85
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 38
- 239000010703 silicon Substances 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 claims description 96
- 229910052751 metal Inorganic materials 0.000 claims description 42
- 239000002184 metal Substances 0.000 claims description 42
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 37
- 239000011241 protective layer Substances 0.000 claims description 18
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 14
- 239000010949 copper Substances 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 239000004411 aluminium Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 238000003475 lamination Methods 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 238000005538 encapsulation Methods 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 6
- 230000004888 barrier function Effects 0.000 abstract description 5
- 238000003466 welding Methods 0.000 abstract 3
- 230000006872 improvement Effects 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 3
- 239000012212 insulator Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000005304 joining Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Images
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a package support plate which is suitable for packaging a three-dimensional integrated circuit. A silicon through hole is designed to run through a second semiconductor substrate and a second dielectric layer and be connected with a welding pad in a first dielectric layer; therefore, the complicated technology in a wire leading method during application of a packaging structure in the prior art is simplified, for example, the wire leading is realized without arranging the welding pad after opening etching is executed for multiple times, so that the working efficiency is improved; furthermore, a barrier layer for preventing damage to a lower structure during welding pad etching does not need to be formed, so that the thickness of the packaging support plate is reduced, and the performance of a semiconductor device on the rear surface of the second semiconductor substrate is optimized.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of encapsulating carrier plate and manufacture method thereof.
Background technology
Since integrated circuit invention, such as, due to the lasting improvement of various electronic units (transistor, diode, resistor, capacitor etc.) integration density, semi-conductor industry has experienced opens fast development continuously.Largely, the improvement of this integration density comes from repeatedly reducing of minimum feature size, to allow more parts to be integrated in given chip area.
These integrated improvement are two dimension (2D) substantially in essence, because being substantially positioned on the surface of semiconductor wafer for the volume being occupied by integrated component.Although the huge improvement of imprint lithography has caused the improvement that two-dimentional integrated circuit forms significantly, still has the physical restriction to obtaining density in two-dimentional integrated circuit.Wherein a kind of restriction is to manufacture the required minimum dimension of these parts.And, in the time that more devices are put in a chip, need more complicated design.
Restriction is in addition the increase that comes from interconnect between the device causing along with the remarkable increase of number of devices quantity and length.In the time of interconnection quantity and length increase, circuit capacitance-resistance (RC) postpones and power consumption all increases.
Solving in the trial of above-mentioned restriction, conventionally use through-silicon-via (TSV) in three dimensional integrated circuits (3D-IC) and stack chip, be used for connecting tube core.The weld pad that TSV is generally used for the integrated circuit on tube core to be connected to the back side of tube core is in this case realized connection.
Please refer to Fig. 1, signal Figure 200 of its encapsulating structure that is a kind of three dimensional integrated circuits of the prior art, wherein two nude films 210,230 are so that (facetoface) mode is stacking face-to-face.Lower nude film 210 comprises a substrate 212 and an inner wire 218 through dielectric material 215, to connect substrate 212 to copper joint sheet 221.In substrate 212, be formed with semiconductor element, for example transistor.Inner wire 218 can comprise multiple layer metal layer, guide hole, with contact plunger (not shown).Guide hole (Via) connects two metal levels.Contact plunger (contact) connects a metal level to substrate 212.Copper joint sheet 221 is a metal surface, is used for connecting the copper joint sheet 241 of nude film 230.Upper nude film 230 has similar structure, comprises a substrate 232 and an inner wire 238 through dielectric material 235, to connect substrate 232 to copper joint sheet 241.Inner wire 238 can comprise multiple layer metal layer, guide hole, with contact plunger (not shown).Because external signal and power supply supply are to be connected to upper nude film 230, in general technology, utilizing silicon through hole (TSV) 252 that inner wire 238 is connected to back side metal 255(is metal level).Afterwards, normally with the form of heavy distribution layer, weld pad 260 is arranged on back side metal 255, and then lead-in wire can be engaged to the projection 265 on weld pad 260.
But in the encapsulating structure for three dimensional integrated circuits of the prior art, while lead-in wire, technique is more complicated, on nude film and dielectric material, all need to carry out respectively etching technics, lead-in wire weld pad extremely above could come out the metal level of upper nude film; In addition, before carrying out weld pad, silicon through-hole surfaces need to cover one deck barrier layer, with the structure below avoiding being damaged in the time carrying out the etching of weld pad, and this layer of barrier layer is relatively thick, increase the thickness of overall three dimensional integrated circuits encapsulating carrier plate, in the time that there is high sensitive device at the upper nude film back side, can further affect the susceptibility of device.In order to reduce the process complexity that in three dimensional integrated circuits, encapsulating structure goes between and to reduce the size of encapsulating structure, those skilled in the art meet the solution of this demand always in searching.
Summary of the invention
The object of the present invention is to provide a kind of encapsulating carrier plate and manufacture method thereof, complex process while using encapsulating structure of the prior art to solve in lead-in wire method, need repeatedly carry out weld pad realization lead-in wire being just set, the problem that causes operating efficiency to decline after etching opening.
For solving the problems of the technologies described above, the invention provides a kind of encapsulating carrier plate and manufacture method thereof, described encapsulating carrier plate comprises: the first Semiconductor substrate, be formed at the first dielectric layer in described the first Semiconductor substrate, be formed at the second dielectric layer on described the first dielectric layer, be formed at the second Semiconductor substrate on described the second dielectric layer and run through the silicon through hole of described the second dielectric layer and described the second Semiconductor substrate; Wherein, in described the first dielectric layer, be provided with weld pad, described weld pad contacts with described silicon via bottoms; The surface of described silicon through hole and described the second Semiconductor substrate is provided with protective layer, and has opening on described protective layer, and described opening exposes described weld pad.
Optionally, in described encapsulating carrier plate, in described the first dielectric layer and described the second dielectric layer, be formed with multiple layer metal layer and multiple contact plunger; Between described multiple metal level, be electrically connected by described contact plunger, and be electrically connected with the first Semiconductor substrate and the second Semiconductor substrate by described contact plunger.
Optionally, in described encapsulating carrier plate, described metal level and described contact plunger are copper layer or aluminium lamination.
Optionally, in described encapsulating carrier plate, the position of described silicon through hole is set away from described metal level in described the second dielectric layer.
Optionally, in described encapsulating carrier plate, the opening on described protective layer, is formed by etching technics.
Optionally, in described encapsulating carrier plate, described the first Semiconductor substrate and described the second Semiconductor substrate are silicon substrate.
Optionally, in described encapsulating carrier plate, the material of described the first dielectric layer and described the second dielectric layer is silicon nitride or silica.
The present invention also provides a kind of manufacture method of encapsulating carrier plate, and the manufacture method of described encapsulating carrier plate comprises:
The first Semiconductor substrate is provided;
In described the first Semiconductor substrate, form the first dielectric layer;
In described the first dielectric layer, form weld pad, and form the second dielectric layer on described the first dielectric layer;
On described the second dielectric layer, form the second Semiconductor substrate;
Silicon through hole is beaten in position above the corresponding described weld pad of described the second semiconductor substrate surface, and described silicon through hole runs through described the second Semiconductor substrate and the second dielectric layer contacts with described weld pad;
Surface at described the second Semiconductor substrate and described silicon through hole forms protective layer;
On described protective layer, form opening, described opening exposes described weld pad.
Optionally, in the manufacture method of described encapsulating carrier plate, in described the first dielectric layer and described the second dielectric layer, be formed with multiple layer metal layer and multiple contact plunger; Between described multiple metal level, be electrically connected by described contact plunger, and be electrically connected with the first Semiconductor substrate and the second Semiconductor substrate by described contact plunger.
Optionally, in the manufacture method of described encapsulating carrier plate, described metal level and described contact plunger are copper layer or aluminium lamination.
Optionally, in the manufacture method of described encapsulating carrier plate, the position of described silicon through hole is set away from described metal level in described the second dielectric layer.
Optionally, in the manufacture method of described encapsulating carrier plate, the opening on described protective layer, is formed by etching technics.
Optionally, in the manufacture method of described encapsulating carrier plate, described the first Semiconductor substrate and described the second Semiconductor substrate are silicon substrate.
Optionally, in the manufacture method of described encapsulating carrier plate, the material of described the first dielectric layer and described the second dielectric layer is silicon nitride or silica.
In encapsulating carrier plate provided by the present invention, by by silicon via design for running through the second Semiconductor substrate and the second dielectric layer, the structural design being connected with the weld pad in the first dielectric layer, simplify the complicated technology in lead-in wire method while applying encapsulating structure of the prior art, as after etching opening, weld pad realization lead-in wire being just set without repeatedly carrying out, improve operating efficiency; In addition, avoid being damaged to structure below while carrying out etching soldering pad without forming barrier layer, reduced the thickness of encapsulating carrier plate, optimized the performance of the second Semiconductor substrate back side semiconductor-on-insulator device.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the encapsulating structure of existing three dimensional integrated circuits;
Fig. 2 A-2D is the generalized section that is used to form each step in the method for encapsulating carrier plate in one embodiment of the invention;
Fig. 3 is the flow chart of the manufacture method of the encapsulating carrier plate of one embodiment of the invention.
It should be noted in the discussion above that these figure are intended to illustrate the general characteristic according to the method using in certain exemplary embodiments of the present invention, structure and/or material, and the written description providing is below supplemented.But, these figure not drawn on scale, thereby may can accurately not reflect precision architecture or the performance characteristics of any given embodiment, and the numerical value that these figure should not be interpreted as limiting or restriction is contained by exemplary embodiment according to the present invention or the scope of attribute.For example, for the sake of clarity, can dwindle or amplify relative thickness and the location of molecule, layer, region and/or structural detail.In the accompanying drawings, use similar or identical Reference numeral to represent similar or identical element or feature.
Embodiment
The encapsulating carrier plate and the manufacture method thereof that the present invention are proposed below in conjunction with the drawings and specific embodiments are described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
Please refer to Fig. 2 D, it is the structural representation of encapsulating carrier plate of the present invention, as shown in Figure 2 D, the described encapsulating carrier plate that is applicable to three dimensional integrated circuits, comprising: the first Semiconductor substrate 10, be formed at the first dielectric layer 11 in described the first Semiconductor substrate 10, be formed at the second dielectric layer 12 on described the first dielectric layer 11, be formed at the second Semiconductor substrate 20 on described the second dielectric layer 12 and run through the silicon through hole 30 of described the second dielectric layer 12 and described the second Semiconductor substrate 20; Wherein, in described the first dielectric layer 11, be provided with weld pad 40, described weld pad 40 touches with described silicon through hole 30 bottom connections; The surface of described silicon through hole 30 and described the second Semiconductor substrate 20 is provided with protective layer 13, and has opening on described protective layer 13, and described opening exposes described weld pad 40.
Preferably, in described the first dielectric layer 11 and described the second dielectric layer 12, be formed with multiple layer metal layer 120 and multiple contact plunger (not shown), between described multiple metal level 120, be electrically connected by described contact plunger, and be electrically connected with the first Semiconductor substrate 10 and the second Semiconductor substrate 20 by described contact plunger.Wherein, described metal level 120 and described contact plunger are copper layer or aluminium lamination, are preferably copper layer, and the electric conductivity of copper is better.Described metal level 120 can use physical vapour deposition (PVD) or plating mode to form.
Preferably, the position that in described the second dielectric layer 12, described silicon through hole 30 is set is away from described metal level 120.In the second dielectric layer 12, there is metal level 120 if beat the position of silicon through hole 30, destroyed metal level 120, and then affected the performance of encapsulating carrier plate.
Preferably, the opening on described protective layer 13 is formed by etching technics.
Preferably, described the first Semiconductor substrate 10 is silicon substrate with described the second Semiconductor substrate 20.Described the first Semiconductor substrate 10 also can comprise other semi-conducting materials, for example III family, IV family or V group element with the material of described the second Semiconductor substrate 20.Concrete, described the first Semiconductor substrate 10 is finally to combine with face-to-face joining technique with described the second Semiconductor substrate 20, the back side that the integrated circuit in described the first Semiconductor substrate 10 is connected to described the second Semiconductor substrate 20 by use TVS is (by the weld pad of TVS bottom-exposed, lead-in wire in realization and described the first Semiconductor substrate 10, lead-in wire is to described second Semiconductor substrate 20 back sides).
Preferably, the material of described the first dielectric layer 11 and described the second dielectric layer 12 is silicon nitride or silica.
Accordingly, the present embodiment also provides a kind of manufacture method of encapsulating carrier plate.Describe the manufacture method of encapsulating carrier plate described in the present embodiment in detail below with reference to Fig. 2 A-2D and Fig. 3.
First, execution step S1, provides the first Semiconductor substrate 10.
Then, execution step S2 forms the first dielectric layer 11 in described the first Semiconductor substrate 10.
Then, execution step S3 forms weld pad 40, and form the second dielectric layer 12 on described the first dielectric layer 11 in described the first dielectric layer 11.
Concrete, the material of described the first dielectric layer 11 and described the second dielectric layer 12 is silicon nitride or silica.In described the first dielectric layer 11 and described the second dielectric layer 12, be formed with multiple layer metal layer 120 and multiple contact plunger (not shown), between described multiple metal level 120, be electrically connected by described contact plunger, and be electrically connected with the first Semiconductor substrate 10 and the second Semiconductor substrate 20 by described contact plunger; Wherein, described metal level 120 and described contact plunger are copper layer or aluminium lamination, are preferably copper layer, and the electric conductivity of copper is better; Described metal level 120 can use physical vapour deposition (PVD) or plating mode to form.
Preferably, as shown in Figure 2 A, the position that forms described weld pad 40 is the position away from metal level 120 in described the first dielectric layer 11,, under wish formation weld pad 40, there is no metal level 120 that is.
Then, execution step S4 forms the second Semiconductor substrate 20 on described the second dielectric layer 12.
Concrete, please refer to Fig. 2 B, described the first Semiconductor substrate 10 is silicon substrate with described the second Semiconductor substrate 20.The material of described Semiconductor substrate also can comprise other semi-conducting materials, for example III family, IV family or V group element.Concrete, described the first Semiconductor substrate 10 is finally to combine with face-to-face joining technique with described the second Semiconductor substrate 20, the back side that the integrated circuit in described the first Semiconductor substrate 10 is connected to described the second Semiconductor substrate 20 by use TVS is (by the weld pad of TVS bottom-exposed, lead-in wire in realization and described the first Semiconductor substrate 10, lead-in wire is to described second Semiconductor substrate 20 back sides).
Then, execution step S5, silicon through hole 30 is beaten in the position above described the second Semiconductor substrate 20 corresponding described weld pads 40 in surface, and described silicon through hole 30 runs through described the second Semiconductor substrate 20 and the second dielectric layer 12 contacts with described weld pad 40.
Concrete, please refer to Fig. 2 C, the position of described silicon through hole 30 is set in described the second dielectric layer 12 away from described metal level 120, that is, under the silicon through hole 30 that wish forms, there is no metal level 120.In the second dielectric layer 12, there is metal level 120 if beat the position of silicon through hole 30, destroyed metal level 120, and then affected the performance of encapsulating carrier plate.
Then, execution step S6, forms protective layer 13 on the surface of described the second Semiconductor substrate 20 and described silicon through hole 30.
Then, execution step S7, please refer to Fig. 2 D, on described protective layer 13, forms opening, and the opening on described protective layer 13 is formed by etching technics, and described opening exposes described weld pad 40.
To sum up, in encapsulating carrier plate provided by the present invention, by by silicon via design for running through the second Semiconductor substrate and the second dielectric layer, the structural design being connected with the weld pad in the first dielectric layer, simplify the complicated technology in lead-in wire method while applying encapsulating structure of the prior art, as after etching opening, weld pad realization lead-in wire being just set without repeatedly carrying out, improve operating efficiency; In addition, avoid being damaged to structure below while carrying out etching soldering pad without forming barrier layer, reduced the thickness of encapsulating carrier plate, optimized the performance of the second Semiconductor substrate back side semiconductor-on-insulator device.
Foregoing description is only the description to preferred embodiment of the present invention, the not any restriction to the scope of the invention, and any change, modification that the those of ordinary skill in field of the present invention does according to above-mentioned disclosure, all belong to the protection range of claims.
Claims (14)
1. an encapsulating carrier plate, be applicable to the encapsulation of three dimensional integrated circuits, it is characterized in that, comprising: the first Semiconductor substrate, be formed at the first dielectric layer in described the first Semiconductor substrate, be formed at the second dielectric layer on described the first dielectric layer, be formed at the second Semiconductor substrate on described the second dielectric layer and run through the silicon through hole of described the second dielectric layer and described the second Semiconductor substrate; Wherein, in described the first dielectric layer, be provided with weld pad, described weld pad contacts with described silicon via bottoms; The surface of described silicon through hole and described the second Semiconductor substrate is provided with protective layer, and has opening on described protective layer, and described opening exposes described weld pad.
2. encapsulating carrier plate as claimed in claim 1, is characterized in that, in described the first dielectric layer and described the second dielectric layer, is formed with multiple layer metal layer and multiple contact plunger; Between described multiple metal level, be electrically connected by described contact plunger, and be electrically connected with the first Semiconductor substrate and the second Semiconductor substrate by described contact plunger.
3. encapsulating carrier plate as claimed in claim 2, is characterized in that, described metal level and described contact plunger are copper layer or aluminium lamination.
4. encapsulating carrier plate as claimed in claim 2, is characterized in that, the position of described silicon through hole is set away from described metal level in described the second dielectric layer.
5. encapsulating carrier plate as claimed in claim 1, is characterized in that, the opening on described protective layer is formed by etching technics.
6. encapsulating carrier plate as claimed in claim 1, is characterized in that, described the first Semiconductor substrate and described the second Semiconductor substrate are silicon substrate.
7. encapsulating carrier plate as claimed in claim 1, is characterized in that, the material of described the first dielectric layer and described the second dielectric layer is silicon nitride or silica.
8. a manufacture method for encapsulating carrier plate, is characterized in that, comprising:
The first Semiconductor substrate is provided;
In described the first Semiconductor substrate, form the first dielectric layer;
In described the first dielectric layer, form weld pad, and form the second dielectric layer on described the first dielectric layer;
On described the second dielectric layer, form the second Semiconductor substrate;
Silicon through hole is beaten in position above the corresponding described weld pad of described the second semiconductor substrate surface, and described silicon through hole runs through described the second Semiconductor substrate and the second dielectric layer contacts with described weld pad;
Surface at described the second Semiconductor substrate and described silicon through hole forms protective layer;
On described protective layer, form opening, described opening exposes described weld pad.
9. the manufacture method of encapsulating carrier plate as claimed in claim 8, is characterized in that, in described the first dielectric layer and described the second dielectric layer, is formed with multiple layer metal layer and multiple contact plunger; Between described multiple metal level, be electrically connected by described contact plunger, and be electrically connected with the first Semiconductor substrate and the second Semiconductor substrate by described contact plunger.
10. the manufacture method of encapsulating carrier plate as claimed in claim 9, is characterized in that, described metal level and described contact plunger are copper layer or aluminium lamination.
11. encapsulating carrier plates as claimed in claim 8, is characterized in that, the position of described silicon through hole are set away from described metal level in described the second dielectric layer.
The manufacture method of 12. encapsulating carrier plates as claimed in claim 8, is characterized in that, the opening on described protective layer is formed by etching technics.
The manufacture method of 13. encapsulating carrier plates as claimed in claim 8, is characterized in that, described the first Semiconductor substrate and described the second Semiconductor substrate are silicon substrate.
The manufacture method of 14. encapsulating carrier plates as claimed in claim 8, is characterized in that, the material of described the first dielectric layer and described the second dielectric layer is silicon nitride or silica.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410078290.1A CN103824828A (en) | 2014-03-05 | 2014-03-05 | Packaging support plate and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410078290.1A CN103824828A (en) | 2014-03-05 | 2014-03-05 | Packaging support plate and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103824828A true CN103824828A (en) | 2014-05-28 |
Family
ID=50759809
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410078290.1A Pending CN103824828A (en) | 2014-03-05 | 2014-03-05 | Packaging support plate and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103824828A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101026102A (en) * | 2006-01-24 | 2007-08-29 | 三星电子株式会社 | Stacked chip package using warp-proof insulative material and method of manufacturing the same |
| CN101335261A (en) * | 2007-06-27 | 2008-12-31 | 台湾积体电路制造股份有限公司 | Stacked integrated circuits and semiconductor devices |
| CN202905706U (en) * | 2012-10-23 | 2013-04-24 | 格科微电子（上海）有限公司 | Three-dimensional packaging structure |
| CN103579377A (en) * | 2012-07-31 | 2014-02-12 | 台湾积体电路制造股份有限公司 | Elevated photodiode with a stacked scheme |
-
2014
- 2014-03-05 CN CN201410078290.1A patent/CN103824828A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101026102A (en) * | 2006-01-24 | 2007-08-29 | 三星电子株式会社 | Stacked chip package using warp-proof insulative material and method of manufacturing the same |
| CN101335261A (en) * | 2007-06-27 | 2008-12-31 | 台湾积体电路制造股份有限公司 | Stacked integrated circuits and semiconductor devices |
| CN103579377A (en) * | 2012-07-31 | 2014-02-12 | 台湾积体电路制造股份有限公司 | Elevated photodiode with a stacked scheme |
| CN202905706U (en) * | 2012-10-23 | 2013-04-24 | 格科微电子（上海）有限公司 | Three-dimensional packaging structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI752402B (en) | Chip package structure and manufacturing method thereof | |
| CN102931102B (en) | The method of Multi-chip wafer level package | |
| JP5435593B2 (en) | 3D integrated circuit manufacturing method and recording medium (3D integrated circuit device manufacturing method using interface wafer as permanent carrier) | |
| CN103681613A (en) | Semiconductor device with discrete blocks | |
| CN102931173A (en) | Multi-chip wafer level package | |
| CN103119711A (en) | Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby | |
| US20200365539A1 (en) | Bonding Structure And Method For Manufacturing The Same | |
| CN103545275A (en) | Through-silicon via packaging structure and forming method | |
| CN103681367A (en) | Packaging Methods and Packaged Devices | |
| CN106449525A (en) | Semiconductor package | |
| CN104051354A (en) | Semiconductor package and fabrication method thereof | |
| CN104051379A (en) | Bumpless build-up layer (bbul) semiconductor package with ultra-thin dielectric layer | |
| KR20110055973A (en) | Semiconductor chip module and semiconductor package including same | |
| KR102452242B1 (en) | Semiconductor device having protection mechanism, related system, device and method | |
| CN104733398A (en) | Wafer three-dimensional integration wire leading process | |
| US20170062399A1 (en) | Method and structure for low-k face-to-face bonded wafer dicing | |
| CN103250246A (en) | Method and system for thin multi chip stack package with film on wire and copper wire | |
| CN104051355A (en) | Package-on-Package Structure and Method of Forming Same | |
| CN104766806A (en) | Wafer three-dimensional integration method | |
| US8384215B2 (en) | Wafer level molding structure | |
| CN104517921A (en) | Bonded substrate and forming method thereof, and three-dimensional package structure and forming method thereof | |
| CN104124212A (en) | Semiconductor package and fabrication method thereof | |
| Burns | TSV-based 3D integration | |
| CN110993560A (en) | Three-dimensional integrated packaging method | |
| TWI409933B (en) | Chip stacked package structure and its fabrication method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20140528 |
|
| RJ01 | Rejection of invention patent application after publication |