CN103824774B - Trench type MOS rectifier and manufacturing method thereof - Google Patents

Abstract

The invention discloses a trench type MOS rectifying element structure, comprising: a planar MOS rectifying structure is formed on a mesa of the active region, and an active region trench is formed on an adjacent side of the mesa. The active region trench is formed in an n-epitaxial layer on a heavily doped n + semiconductor substrate. The trench of the active area has a trench gate oxide layer formed on the bottom and sidewall of the trench and a p-type doped polysilicon layer formed thereon. A top metal layer is formed on the active region and connects the gate and source of the planar MOS structure to the polysilicon layer of the active region trench. The invention also discloses a manufacturing method thereof. The present invention discloses a trench MOS device structure and its manufacturing method, which uses the trench structure to forward bias V_FLower, reverse leakage is less.

Description

Trench type MOS rectifier and manufacturing method thereof

technical field

The invention relates to semiconductor elements, in particular to a new trench type MOS rectifier diode structure and a manufacturing method thereof.

Background technique

Schottky diode is an important power component, which is widely used in power supply switching, motor control, telecom switching, factory automation, electronic automation, etc. and many high-speed power switching applications. Schottky diodes are attractive because they have good performance, for example, under reverse bias, they have a reasonable leakage current (the leakage current of Schottky diodes is higher than that of ordinary PN diodes), low forward bias The voltage and the reverse recovery time tRR are short, and the high voltage of at least 250 volts can be blocked when the reverse bias voltage is applied. However, the leakage current of the Schottky diode is higher than that of the general PN type diode, and the leakage current is not a stable value but increases with the increase of the reverse bias voltage. This is because the image charge potential barrier lowering. Another major disadvantage is that the reliability of the metal-semiconductor contact decreases as the temperature increases, which reduces the Schottky diode's ability to withstand forward and reverse surges.

A new generation of MOS rectifier diodes can overcome these problems. As shown in FIG. 1 , a top metal layer 20 connects the metal oxide semi-gate (metal or polysilicon layer 15 and gate oxide layer 10 ) and the source 5 , and the heavily n+ doped source 5 is formed in the p-type well. However, when the forward bias voltage is applied under the metal-oxide-semiconductor gate, the current does not flow from left to right (because the sources on the left side are not at the same potential), but flows downward from the channel 30 to the n+ substrate. At reverse bias, the channel is pinched by the depletion region formed by the p-well. MOS guarantees that the forward bias performance is similar to that of a Schottky diode, while the performance of reverse bias is greatly improved, because it does not have the aforementioned image charge potential barrier reduction, so that the leakage current becomes constant and does not increase with the reverse bias value. And increase.

Contents of the invention

The invention discloses a method for manufacturing a trench type MOS rectifier element, which includes the following steps: firstly, an n+ semiconductor substrate is provided with an n- epitaxial layer formed thereon, and then an insulating layer is formed on the n- epitaxial layer On the layer, the insulating layer is defined as an active area and an active area trench with a photoresist pattern.

Subsequently, a first oxide layer is formed on the bottom, sidewalls and platforms of all the trenches by a thermal oxidation process to serve as a trench gate oxide layer; and then a conductive impurity-doped polysilicon layer is deposited to fill the plurality of trenches; Next, an anisotropic etching process is performed, and the first oxide layer on the plurality of platforms is used as an etching stop layer.

Afterwards, a CVD oxide layer is formed on all exposed surfaces, and the active area is defined with a photoresist pattern, and the oxide layer in the active area is removed by anisotropic etching. Next, a planar gate oxide layer is formed on the surface of the active region by a thermal oxidation process; subsequently, a second conductive impurity-doped polysilicon layer is deposited on all exposed surfaces; and a photoresist pattern is formed On the active region, a photoresist pattern defines a source region and a MOS planar gate region, the source region and the MOS planar gate region are pre-located on the n-epitaxial layer between the plurality of active region trenches within the platform.

An etching technique is applied to remove the polysilicon layer not doped by the second conductivity impurity of the photoresist pattern mask to form a planar MOS gate and an exposed source predetermined region. Then, ion implantation is performed to implant p-type conductive impurities on the plurality of predetermined regions of the source regions and the unmasked trench polysilicon layer, using the photoresist pattern as a mask. After removing the photoresist pattern mask, an RTA annealing process is performed to activate the plurality of dopant ions. Afterwards, the gate oxide layer not masked by the planar gate is removed to expose the source region and the trench polysilicon layer. Then apply the self-aligned metal silicide layer technology to form a metal silicide layer on all exposed polysilicon layers and platforms. Forming a top metal layer on all exposed surfaces; then defining a metal pad by photoresist patterning and etching techniques to serve as the anode of the trench MOS. Finally, after grinding the back of the semiconductor substrate to a predetermined thickness, a metal layer is formed on the back of the n+ semiconductor substrate to serve as the cathode of the n+ semiconductor substrate.

The present invention also discloses the structure of the above-mentioned trenched MOS rectifier element, including: a plurality of trenches in the active region are formed in the n- epitaxial layer on the heavily doped n+ semiconductor substrate, and a trench gate oxide layer is formed in the plurality of trenches The bottoms and sidewalls of the plurality of trenches are filled with p-type doped polysilicon layer; the planar gate includes a gate oxide layer and a conductive layer are sequentially formed on the platform between the plurality of trenches in the active region and the trenches a source region is formed in the n- epitaxial layer below the plurality of platforms and adjacent to the planar gate; a top metal layer covers the active region as an anode; and a metal layer as a cathode is formed on the on the heavily doped n+ semiconductor substrate.

The aforementioned trench MOS structure further includes a salicide layer formed between the plurality of polysilicon layers and the plurality of source regions under the top metal layer.

The trench type MOS device structure and its manufacturing method disclosed by the present invention utilize the trench type structure, so that the forward bias voltage V _F is lower and the reverse leakage current is smaller.

Description of drawings

Figure 1 shows a schematic cross-sectional view of a known planar MOS rectifier.

FIG. 2A shows a schematic top view of a trench MOS structure (without the top metal pad) fabricated according to the method of the present invention.

2B is a schematic cross-sectional view along line A-A' of FIG. 2A , showing that the top metal layer of the trench MOS is connected to the planar gate, the trench gate, and the p-type doped polysilicon conductor layer in the trench.

Fig. 2C is a schematic cross-sectional view along the BB' line of Fig. 2A, showing that the top metal layer of the trench MOS device is connected to the p+ heavily doped source region, the trench gate and the p-type doped polysilicon conductor in the trench Layer cross-sectional schematic.

2D is a schematic cross-sectional view taken along line C-C' of FIG. 2A, showing the top metal layer of the SBR connected to the planar gate and p+ heavily doped source region 148. FIG.

FIG. 3A shows a schematic cross-sectional view of forming a first oxide layer pattern as a hard mask.

FIG. 3B shows a schematic cross-sectional view of using the first oxide layer pattern as a hard mask and performing dry etching 0 to form trenches in the active region.

FIG. 3C shows a schematic cross-sectional view of a sacrificial oxide layer formed entirely by a high temperature oxidation process.

FIG. 3D shows a schematic cross-sectional view of dilute hydrofluoric acid removing the sacrificial oxide layer 125 .

FIG. 3E is a schematic cross-sectional view showing the thickening of the oxide layer formed by the high temperature oxidation process as the withstand voltage capability of the device increases.

FIG. 3F shows a polysilicon etch-back technique in which a p-type impurity-doped polysilicon layer is deposited and then anisotropic etching is performed, using the gate oxide layer as an etch stop layer.

FIG. 3G shows a schematic cross-sectional view of an oxide layer deposited by CVD technique.

FIG. 3H shows a schematic diagram of removing both the gate oxide layer and the CVD oxide layer on the platform by anisotropic etching.

FIG. 3I shows the oxide layer of the planar gate of the trench MOS device growing a second gate oxide layer by high temperature oxidation process.

FIG. 3J shows a schematic cross-sectional view of depositing a second polysilicon layer on the second gate oxide layer 150 .

FIG. 3K shows that a photoresist pattern is formed on the second polysilicon layer in the active region to define predetermined positions of the gate and source of the trenched MOS.

FIG. 3L shows that an anisotropic etching technique is applied to the second polysilicon layer 160, using the photoresist pattern as a mask to remove the unmasked second polysilicon layer.

3MA and 3MB are cross-sectional views along A-A' and B-B', respectively. Using the photoresist pattern as a mask, ion implantation technology is applied to implant p-type impurities to form a source region.

3NA and 3NB are cross-sectional views along A-A' and B-B', respectively, showing the removal of the photoresist pattern followed by RTA annealing to form the source region.

3OA and 3OB are cross-sectional views along A-A' and B-B', respectively, showing that the oxide layer above the source region is removed by dilute hydrofluoric acid to expose the source region.

Figures 3PA and 3PB are cross-sectional views along A-A' and BB', respectively, showing the salicide process of sequentially depositing Ti/TiN by sputtering, followed by RTA and etching .

Figures 3QA and 3QB are cross-sectional views along A-A' and B-B', respectively, showing the deposition of a top metal layer followed by the photoresist pattern defining the anode pad.

3RA and 3RB are cross-sectional views along A-A' and B-B' respectively, showing that after removing the photoresist pattern, a metal layer is deposited on the back surface of the semiconductor substrate to form a cathode.

3SA and 3SB are cross-sectional views along A-A' and B-B' of the second embodiment of the present invention, respectively, and the trench reaches the heavily doped n+ semiconductor substrate.

Figure number:

100 heavily doped n+ semiconductor substrate 105 n- epitaxial layer

110 First oxide layer 115 Active area

120A Trench in active area

130' Gate Oxide (Second Embodiment) 125 Sacrificial Oxide

130 Gate Oxide 135 CVD Oxide

140 p-doped

148 Source region 150 Second gate oxide

160 second polysilicon layer 165 photoresist pattern

175 Barrier metal layer 180 Top metal layer

190 back metal layer

detailed description

The present invention discloses a trench type MOS device structure, including: a planar MOS structure is formed on the platform of the active area, and there is a trench in the active area on the adjacent side of the platform. The trench in the active region is formed in the n- epitaxial layer on the heavily doped n+ semiconductor substrate. In the ditch of the active region, a ditch gate oxide layer is formed on the bottom and side walls of the ditch and a p-type doped polysilicon layer is formed thereon. A top metal layer is formed on the active area, connecting the gate, the source of the planar MOS structure and the polysilicon layer on the trench of the active area.

Please refer to the top view shown in FIG. 2A for the trenched MOS device structure (excluding the top metal layer) multi-platform and multi-active area trench structure of the present invention. FIG. 2B is a schematic cross-sectional view of the trench MOS device along line A-A' of FIG. 2A. 2B shows a schematic cross-sectional diagram showing that the top metal layer 180 of the trench MOS is connected to the planar gate 160 and the trench gate 130 and the p-type doped polysilicon conductor layer 140 in the trench. The trench gate 130 and the p-type doped polysilicon conductor layer 140 in the trench are formed in the n- epitaxial layer 105 . There is a thin gate oxide layer 150 under the planar gate 160 .

FIG. 2C shows a schematic cross-sectional view of the trench MOS device along the line B-B' of FIG. 2A. The cross-sectional schematic diagram shown in FIG. 2C shows that the top metal layer 180 of the trench MOS is connected to the p+ heavily doped source region 148 and the trench gate 130 and the p-type doped polysilicon conductor layer 140 in the trench is built on the n-epitaxy. In the crystal layer 105.

2D is a schematic cross-sectional view of line C-C' in FIG. 2A , showing that the top metal layer 180 of the trench MOS is connected to the planar gate 160 and the p+ heavily doped source region 148.

The manufacturing method will be described in detail below. In the following description, "-" following n or p represents light doping, and "+" represents heavy doping.

Please refer to the cross-sectional schematic diagram shown in FIG. 3A , firstly, an n+ semiconductor substrate 100 heavily doped with n-type impurities is provided with an n- epitaxial layer 105 doped with n-type impurities, and a first oxide layer 110 is formed thereon. . The first oxide layer 110 is formed by thermal oxidation process or chemical vapor deposition (CVD), with a thickness of about 100-2000nm.

Next, a photoresist pattern (not shown) is defined as an etching mask for the first oxide layer 110 . Subsequently, using the photoresist pattern as a mask and the n- epitaxial layer 105 as an etching stop layer, an etching step is performed to remove the first oxide layer 110 not masked by the photoresist pattern. Next, remove the photoresist pattern.

Subsequently, please refer to FIG. 3B , using the pattern of the first oxide layer 110 as a hard mask, dry etching is performed to etch the n- epitaxial layer 105, and the etching depth is approximately from 0.5um to the heavily doped n+ semiconductor substrate 100 to form Active area trench 120A. Subsequently, the first oxide layer 110 is removed. The depth of the trench 120A in the active area is approximately 0.5 to 50 times the width. In addition, the ditch gate oxide layer (please refer to the description of FIG. 3E below) will be formed in the subsequent process to be quite thick and increase with the high voltage withstand capability of the device, which will significantly affect the width of the ditch 120A in the active region.

Referring to FIG. 3C , a high temperature oxidation process is performed to form a sacrificial oxide layer 125 with a thickness of about 10-150 nm on the bottom, sidewalls and platforms of all the trenches 120A. The purpose of forming the sacrificial oxide layer 125 is to repair the damage caused by etching and increase the width of the trench in the active region.

Please refer to FIG. 3D , and then wet etching is performed with dilute hydrofluoric acid to remove the sacrificial oxide layer 125 .

Subsequently, a high temperature oxidation process is used to form a trench oxide layer 130 with a thickness of about 80-800 nm on the bottom, sidewalls and platforms of all the trenches 120 . The trench oxide layer 130 is the trench gate oxide layer 130 of the trench MOS, and the result is shown in FIG. 3E . The thickness of the gate oxide layer 130 varies according to the desired high voltage withstand capability.

Next, please refer to FIG. 3F. First, a p-type impurity-doped polysilicon layer 140 is deposited by CVD to fill the trench 120A and at least fill up the trench 120A in the active region. An anisotropic etching technique and polysilicon etch-back technique using the gate oxide layer 130 as an etching stop layer are applied to etch the p-type doped polysilicon 140 . Subsequently, an oxide layer 135 is deposited by CVD technique. The result, as shown in Figure 3G.

Then, referring to FIG. 3H , the active region is defined with a photoresist pattern, anisotropic etching is performed to remove the oxide layer of the active region, and then the photoresist is removed.

Next, as shown in FIG. 3I , a thin second gate oxide layer 150 is grown on the exposed n- epitaxial layer 105 and p-type doped polysilicon layer 140 by high temperature oxidation process. The second gate oxide layer 150 is an oxide layer of the planar gate of the MOS device, and its thickness is about 2 to 20 nm.

Referring to FIG. 3J , a second polysilicon layer 160 is deposited on the second gate oxide layer 150 with a thickness of about 50-500 nm. The second gate oxide layer 150 and the second polysilicon layer 160 are used as planar gates of MOS.

Please also refer to FIG. 3K to form a photoresist pattern 165 on the second polysilicon layer 160 in the active region to define predetermined positions of the MOS gate and source. The rest are all naked. Next, please refer to FIG. 3L to perform anisotropic etching on the second polysilicon layer 160 , using the photoresist pattern 165 as a mask to remove the unmasked second polysilicon layer 160 .

Next, please refer to the schematic diagrams of FIGS. 3MA and 3MB. Please note that the second English letters A and B here and below are cross-sectional views along A-A' and BB' respectively. Using the photoresist pattern as a mask, apply ion implantation technology to implant p-type impurities, such as implanting BF ₂ ⁺ or B ⁺ ions in the p-type doped polysilicon 140 region at the predetermined position of the source of the MOS element, to form The source region 148 and the trench polysilicon layer 140 are not masked. Next, the photoresist pattern 165 is removed, and RTA annealing is performed, for example, at 900-1100° C. for about 30-90 seconds, to activate the conductive impurity ions. The source region 148 after activation of the conductive p-type impurity is the cross-sectional view of FIGS. 3NA and 3NB.

Please refer to the cross-sectional views of two different positions in FIG. 30A and 3OB , and then use diluted hydrofluoric acid to remove the oxide layer above the source region to expose the source region 148 .

Please refer to the cross-sectional views of two different positions in FIGS. 3PA and 3PB , and then sputtering technology is used to deposit the contact metal, and then RTA is applied to form the metal silicide 175 as the contact metal layer 175 .

Next, please refer to the cross-sectional views of two different locations in FIGS. 3QA and 3QB , and then deposit a top metal layer 180 to define the anode pad with a photoresist pattern (not shown). Etching is then performed using the photoresist pattern as a mask to remove the unmasked top metal layer 180 to complete the anode pad 180 .

3RA and 3RB show the cross-sectional views of two different positions. The photoresist pattern is removed, and the backside of the semiconductor substrate 100 is ground to a thickness of 4-12mil. Finally, another metal layer 190 is deposited on the back surface of the substrate to form a cathode.

In the present invention, the width of the ditch 120A in the active region and the width of the platform are about 1:1~1:10. When a reverse bias is applied, a depletion region is formed between the ditch to prevent the passage of current. When a forward bias is applied, it can pass through The conductor layer 140 in the trench increases the doping concentration of the n- epitaxial layer 105 under the platform to reduce the resistance.

According to yet another embodiment of the present invention, the trench of the trench type MOS rectifier element can also be deepened, for example, as deep as the heavily doped n+ semiconductor substrate 100, other processes except that the gate oxide layer 130' needs to be thickened , and the rest of the steps remain unchanged. Please refer to the cross-sectional views of two different positions shown in FIGS. 3SA and 3SB. The advantage of this is that the forward bias voltage can be significantly reduced. The reason why the gate oxide layer 130' is thicker than the gate oxide layer 130 in the first embodiment is to obtain the benefit of significantly reducing the forward bias without sacrificing too much withstand voltage capability. The thickness of the gate oxide layer 130' in the second embodiment is about 0.05-2 μm for the withstand voltage capability of 10-600V.

The present invention has the following advantages:

(1) It has a low forward bias voltage V _F and the ability to withstand high voltage.

(2) Benefiting from the trench structure in the active area, the same plane area can carry higher forward current.

(3) When the trench is as deep as the heavily doped n+ semiconductor substrate 100, the required forward bias can be lower than that of the trench only reaching the n- epitaxial layer 105 (embodiment 1), and the average can be reduced by about 5 %.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention; all other equivalent changes or modifications that do not deviate from the spirit disclosed in the present invention should be included in the application. within the scope of the patent.

Claims (10)

1. a kind of manufacture method of ditching type MOS rectifier cells, is characterized in that, the manufacturer of the ditching type MOS rectifier cells Method includes at least following steps:

There is provided a n+ semiconductor substrates to be formed thereon with a n- epitaxial layers；

An insulating barrier is formed on the n- epitaxial layers；

Define and etch the insulating barrier to form multiple action zone irrigation canals and ditches；

Remove the insulating barrier；

One first oxide layer is formed on all irrigation canals and ditches bottoms, side wall and platform, using as irrigation canals and ditches gate oxidation with thermal oxidation technology Layer；

The polysilicon layer of conductive impurities doping is deposited to fill up the plurality of irrigation canals and ditches；

The etch-back technics of anisotropic etching is imposed to remove the polysilicon layer on platform, described on the plurality of platform First oxide layer is etch stop layer；

Remove first oxide layer；

One planar gate oxide layer is re-formed on the surface after etching with thermal oxidation technology；

Deposit one second conductive impurities doping polysilicon layer on all exposed surfaces；

A photoresistance pattern is formed on action zone, the photoresistance pattern definition source area and ditching type MOS planar gates, the source The pre- area in pole and the planar gate polar region is located in the platform of the n- epitaxial layers between the plurality of action zone irrigation canals and ditches；

Impose etching technique to remove not by the second polysilicon layer of the photoresistance patterned mask to form ditching type MOS planar gates Pole and source electrode fate；

Ion implant implant p-type conductivity impurity is imposed in the plurality of source area fate and not by the irrigation canals and ditches polysilicon of mask On layer, with the photoresistance pattern as mask；

Remove not by the planar gate oxide layer of the photoresistance patterned mask；

Remove the photoresistance pattern；

Impose annealing process to activate the plurality of dopant ion；

Remove not by the planar gate oxide layer of the planar gate mask；

Autoregistration metal silicified layer technology is imposed, to form metal silicified layer on exposed all polysilicon layers and platform；

Formation metal layer at top is on all exposed surfaces；

Metal gasket is defined with photoresistance pattern and etching technique, using the anode as the ditching type MOS；

Impose the n+ semiconductor substrates grinding back surface to be ground to the n+ semiconductor substrates of predetermined thickness；

A metal level is formed in the semiconductor-based backs of the n+, using as n+ semiconductor substrate negative electrodes.

2. manufacture method as claimed in claim 1, is characterized in that, the depth-to-width ratio of the action zone irrigation canals and ditches is 1:1～50:1, and Action zone irrigation canals and ditches and the platform area width ratio are 1:1～1:10.

3. manufacture method as claimed in claim 1, is characterized in that, the action zone irrigation canals and ditches inner grid oxidated layer thickness be 80～ 800nm and increase with the increase of the MOS high-voltage resistance capabilities.

4. manufacture method as claimed in claim 1, is characterized in that, the manufacture method is further included after etchback step and moved Before first oxide layer, a CVD oxide layers are formed in all exposed surfaces, then with photoresistance pattern definition action zone, Impose anisotropic etching and will remove action zone oxide layer, then remove photoresistance, to increase the oxygen of the terminator beyond the action zone Change thickness degree.

5. a kind of ditching type MOS rectifier cells, is characterized in that, the ditching type MOS rectifier cells are included at least:

Multiple action zone irrigation canals and ditches are formed in the n- epitaxial layers on heavily doped n+ semiconductor substrates, are had in the plurality of irrigation canals and ditches Irrigation canals and ditches grid oxic horizon is formed at the plurality of trench bottom and side wall, and the polysilicon layer of p-type doping is then filled up in which；

Planar gate includes that grid oxic horizon and gate polycrystalline silicon conducting layer are sequentially formed at the plurality of action zone irrigation canals and ditches and ditch On platform between canal；

Source area is formed at the n- epitaxial layers below the plurality of platform Nei and adjacent to the planar gate；

One metal layer at top covers the action zone as anode, and a metal level is formed at the heavily doped n+ as negative electrode On semiconductor substrate.

6. ditching type MOS rectifier cells as claimed in claim 5, is characterized in that, the thickness of the irrigation canals and ditches grid oxic horizon is 80nm～800nm, the thickness of the planar gate oxide layer is 2～20nm.

7. ditching type MOS rectifier cells as claimed in claim 5, is characterized in that, the ditching type MOS rectifier cells are further included Self-aligned metal silicate layer is formed at the plurality of polysilicon layer under the metal layer at top and the plurality of source area Between.

8. a kind of ditching type MOS rectifier cells, is characterized in that, the ditching type MOS rectifier cells are included at least:

Multiple action zone irrigation canals and ditches are by n- epitaxial layers, and are formed in heavily doped n+ semiconductor substrates, in the plurality of irrigation canals and ditches The plurality of trench bottom and side wall, then the polysilicon layer for filling up p-type doping are formed at irrigation canals and ditches grid oxic horizon；

It is flat between the plurality of action zone irrigation canals and ditches and irrigation canals and ditches that planar gate includes that grid oxic horizon and conductive layer are sequentially formed at On platform；

Source area is formed at the n- epitaxial layers below the plurality of platform Nei and adjacent to the planar gate；And

One top layer metallic layer covers the action zone as anode, and a metal level is formed at the heavily doped n+ as negative electrode On semiconductor substrate.

9. ditching type MOS rectifier cells as claimed in claim 8, is characterized in that, the plurality of action zone trench depth reaches n+ In semiconductor substrate, to reduce forward magnitude of voltage.

10. ditching type MOS rectifier cells as claimed in claim 8, is characterized in that, the grid in the plurality of action zone irrigation canals and ditches Oxidated layer thickness is 0.05-2 μm to reach the ability with resistance to 10～600V of reverse bias.