CMOS radio-frequency (RF) switch
Technical field
The present invention relates to a kind of switch of radio system front end, be specifically related to a kind of radio-frequency (RF) switch of the CMOS of employing technique, belong to radio-frequency front-end technical field.
Background technology
In modern wireless communication systems, radio-frequency front-end is the critical component of realizing radiofrequency signal wireless transmission.Radio-frequency (RF) switch is the important component part of radio-frequency front-end, for switching radiofrequency signal path.The main performance index of radio-frequency (RF) switch comprises insertion loss, isolation, harmonic wave index and the linearity etc.Conventionally the receiving and transmitting signal that is applied to antenna end due to radio-frequency (RF) switch switches, so radio-frequency (RF) switch need to work in high-power applications scene conventionally; Also therefore, the selectable semiconductor technology for radio-frequency (RF) switch is just more rare.Traditional radio-frequency (RF) switch, mainly adopts GaAs pHEMT technique to manufacture, and makes full use of the characteristic that pHEMT device electric breakdown strength is high, electron mobility is high and cut-off frequency is high, to guarantee the performance of radio-frequency (RF) switch.In recent years, along with the progress of semiconductor process techniques, the radio-frequency (RF) switch based on CMOS SOI technique has obtained increasing application, and becomes gradually mainstream technology.Cmos device in SOI technique is made on dielectric substrate, thus between device and substrate almost without any parasitic active device effect, and the radio frequency loss of substrate is also very low.
As Fig. 1 (a) is depicted as a typical radio-frequency (RF) switch branch road based on CMOS SOI technique.The grid that three SOI nmos device D1, D2, D3 have formed laminated construction: D1 is connected to switch controlling signal
vg, the drain electrode of D1 is connected to rf inputs mouth
vin, the source electrode of D1 is connected to the drain electrode of D2, and the grid of D2 is connected to switch controlling signal
vg, the source electrode of D2 is connected to the drain electrode of D3, and the grid of D3 is connected to switch controlling signal
vg, the source electrode of D3 is connected to radio frequency output port
vout.Work as switch controlling signal
vgwhen level is high level, D1, D2, D3 conducting, radiofrequency signal can be from rf inputs mouth
vinand radio frequency output port
voutbetween pass through, the laminated construction of D1, D2, D3 composition is equivalent to the conducting resistance of bringing insertion loss; Work as switch controlling signal
vgwhen level is low level, D1, D2, D3 cut-off, radiofrequency signal can not be from rf inputs mouth
vinand radio frequency output port
voutbetween pass through, the laminated construction of D1, D2, D3 composition is equivalent to the great breaking resistor of resistance, simultaneously due to the existence of parasitic capacitance,
vinwith
voutbetween exist faint radio frequency to reveal.Why to adopt laminated construction, due in switching branches during in cut-off state, on its a certain prevention at radio-frequency port, may there is high power RF signal (as the antenna end of radio-frequency antenna switch), need to utilize laminated construction to divide the voltage swing between each device drain and source class equally, guarantee that each device ends, thereby guarantee that all devices all work in safety zone and this switching branches keeps higher isolation performance.As shown in Fig. 1 (b), for when a certain prevention at radio-frequency port of described radio-frequency (RF) switch branch road (
vinor
vout) there is high power RF signal, and this radio-frequency (RF) switch branch road is in the time of cut-off state, in laminated construction each device D1, D2, D3 drain separately and source class on voltage swing distribute.Can see, the drain electrode of each device, source class voltage difference are all the same, have guaranteed that not breakdown and each device of device all remains cut-off state.It should be noted that, count for convenience of description here, laminated construction is 3 device stack; In actual applications, work according to radio-frequency (RF) switch time, required watt level of bearing is carried out the number of device stack in flexible design laminated construction.
Why CMOS SOI technique can utilize laminated construction to form radio-frequency (RF) switch, is due to its special semiconductor material structures.The oxygen buried layer (Buried Oxide) and the dielectric substrate that in SOI, exist are kept apart active device and P type backing material, and making active device is independent isolating each other, and and substrate between there is not parasitic diode yet.Thereby MOS transistor device can design laminated construction in SOI, make each transistor divide the radio-frequency power amplitude of oscillation equally, separately in area of safety operaton.
Current, along with the continuous progress that CMOS technique is maked rapid progress, the integrated level of integrated circuit becomes more and more higher, and function integrated in same integrated circuit (IC) chip is also more and more.Large scale digital circuit and analog circuit, and the radio circuit of small-signal, all can realize the technologic monolithic of CMOS integrated; But the radio circuit of large-signal, especially radio-frequency power amplifier and radio-frequency (RF) switch still cannot realize high-performance integrated in CMOS technique; Meanwhile, if adopt unified all digital circuits, analog circuit, small-signal radio circuit and the large-signal radio circuit manufactured of SOI technique, will make integrated circuit cost very high; The problems referred to above have hindered the further lifting of integrated circuit integrated level.As shown in Fig. 1 (c), it is the nmos device profile of common CMOS process.As we can see from the figure, because drain electrode and the source class of nmos device are N-type doping, and there is parasitic PN junction diode between the substrate (the B utmost point) of P type doping.So, in the time adopting the large signal circuits such as common CMOS process design radio-frequency (RF) switch and radio-frequency power amplifier, active device is in the time of conducting state, and parasitic diode, under the effect of large-signal radiofrequency signal, parasitic turn-on and cut-off can occur, and produces the linearity of harmonic component deterioration circuit; Active device is in the time of cut-off state, and the existence of parasitic diode makes each device that conducting still may occur under the effect of large-signal radiofrequency signal, thereby worsens isolation and linearity index.
In sum, in the urgent need to a kind of radio-frequency (RF) switch method for designing based on common CMOS process, make to utilize device stack structure to form radio-frequency (RF) switch, and there is the high-performance suitable with radio-frequency (RF) switch based on SOI technique.
Summary of the invention
The object of the invention is, for eliminating the impact of parasitic diode for radio-frequency (RF) switch transistor radio-frequency performance, to utilize cmos device laminated construction to form radio-frequency (RF) switch branch road, and the high performance level suitable with the radio-frequency (RF) switch based on SOI technique of maintenance simultaneously.
For achieving the above object, the present invention is by the following technical solutions:
A kind of CMOS radio-frequency (RF) switch is provided, comprise at least one three well structure nmos pass transistor, this three well structures nmos pass transistor has grid G, source class S, drain D, body utmost point B, N-type deep trap utmost point NW, six electrodes of P type substrate utmost point Sub, wherein body utmost point B is connected to the P type body of this three well structures nmos pass transistor device, P type body is a well structure, and the active part of this three well structures nmos pass transistor is enclosed in wherein; N-type deep trap utmost point NW is connected to the N-type trap of this three well structures nmos pass transistor, and N-type trap is the deep trap structure of a N-type doping, and the P type body of this three well structures nmos pass transistor is enclosed in wherein; P type substrate utmost point Sub is connected to the P type doped substrate of this three well structures nmos pass transistor, and P type doped substrate is enclosed in the N-type trap of this three well structures nmos pass transistor wherein; The grid G of this three well structures nmos pass transistor is connected to switch controlling signal by resistance one; Drain D is connected to prevention at radio-frequency port one; Source class S is connected to prevention at radio-frequency port two; Drain D and source class S also link together by resistance two; Body utmost point B is connected to offset signal one by resistance three; N-type deep trap utmost point NW is connected to offset signal two by resistance four; P type substrate utmost point Sub is connected to offset signal one by resistance five.Generally, the equal >10kOhm of described resistance one-resistance four.
Preferably, described three well structure nmos pass transistors are two of M1 and M2, three well structure nmos pass transistor M1 and M2 composition laminated construction, the grid of M1 is connected to switch controlling signal Vg by resistance R 1, the drain electrode of M1 is connected to rf inputs IN, the source class of M1 is connected to the drain electrode of three well structure nmos pass transistor M2, and the drain electrode of M1 and source class link together by resistance R 6; The B utmost point of M1 is connected to offset signal V1 by resistance R 3, and the NW utmost point of M1 is connected to offset signal V2 by resistance R 5; The Sub utmost point of M1 is connected to offset signal V1 by resistance R 4; The grid of M2 is connected to switch controlling signal Vg by resistance R 2, and the source class of M2 is connected to radio-frequency (RF) output end OUT, and the drain electrode of M2 is connected to the source class of three well structure nmos pass transistor M1, and the drain electrode of M2 and source class link together by resistance R 10; The B utmost point of M2 is connected to offset signal V1 by resistance R 7, and the NW utmost point of M2 is connected to offset signal V2 by resistance R 9; The Sub utmost point of M1 is connected to offset signal V1 by resistance R 8.Described offset signal V1 is 0V or negative voltage, and described offset signal V2 is supply voltage or system maximum voltage value.Generally, the equal >10kOhm of described resistance R 1-R10.
The present invention uses triple-well (Triple-Well) structure nmos pass transistor in common CMOS process as radio-frequency (RF) switch transistor, and provide direct current biasing and radio frequency suspend (floating) by large resistance resistance for the parasitic diode in triple-well transistor, no matter make at transistor in conducting state or cut-off state, the operating state of transistorized operating state and parasitic diode all keeps stable and does not affect the transistorized radio-frequency performance of radio-frequency (RF) switch, there is stable isolation and linearity index, and greatly reduce with respect to the radio-frequency (RF) switch cost based on SOI technique, and the high performance level suitable with the radio-frequency (RF) switch based on SOI technique of maintenance simultaneously.
Accompanying drawing explanation
Fig. 1 (a): based on the radio-frequency (RF) switch branch road of CMOS SOI technique;
Fig. 1 (b): in the radio-frequency (RF) switch branch road laminated construction based on CMOS SOI technique each device D1, D2, D3 drain separately and source class on voltage swing distribute;
Fig. 1 (c): the nmos device profile of common CMOS process;
Fig. 2 (a): the schematic diagram of three well structure nmos pass transistors;
Fig. 2 (b): the equivalent electric circuit of three well structure nmos pass transistors;
Fig. 3: the double-layer overlapped layer transistor arrangement of two three well structure nmos pass transistor compositions.
Embodiment
Technical scheme proposed by the invention as shown in Figure 2.As shown in Fig. 2 (a), it is the schematic diagram of three well structure nmos pass transistors.Grid G, source class S, drain D, body utmost point B, N-type deep trap utmost point NW, P type substrate utmost point Sub are transistorized 6 electrodes of described triple-well.Body utmost point B is connected to the P type body (Bulk) of this nmos device, and described P type body is a well structure, and the active part of this nmos device is enclosed in wherein.N-type deep trap utmost point NW is connected to the N-type trap of this nmos device, and described N-type trap is the deep trap structure of a N-type doping, and aforementioned P type body is enclosed in wherein.P type substrate utmost point Sub is connected to the substrate of P type doping, and this substrate is enclosed in aforementioned N-type trap wherein.Visible, described nmos device has formed P type-N-type-P-type material structure around, therefore will have two parasitic PN junction diodes here: the parasitic diode between body utmost point B and N-type trap NW, the parasitic diode between N-type trap NW and P type substrate S ub.The equivalent circuit structure of described nmos device, as shown in Fig. 2 (b).
Based on the above-mentioned three well structure nmos pass transistor structures of the present invention, a radio-frequency (RF) switch embodiment of technical scheme proposed by the invention as shown in Figure 3.This is a double-layer overlapped layer transistor arrangement being made up of two three well structure nmos pass transistors.The grid of the one or three well structure nmos pass transistor M1 passes through resistance
r1be connected to switch controlling signal
vg, the drain electrode of M1 is connected to rf inputs
iN, the source class of M1 is connected to the drain electrode of the two or three well structure nmos pass transistor M2, and the drain electrode of M1 and source class also pass through resistance
r6link together; M1's
bthe utmost point passes through resistance
r3be connected to the first offset signal
v1, the NW utmost point of M1 passes through resistance
r5be connected to the second offset signal
v2; The Sub utmost point of M1 passes through resistance
r4be connected to the first offset signal
v1.The grid of the two or three well structure nmos pass transistor M2 passes through resistance
r2be connected to switch controlling signal
vg, the source class of M2 is connected to radio-frequency (RF) output end
oUT, the drain electrode of M2 is connected to the source class of the one or three well structure nmos pass transistor M1, and the drain electrode of M2 and source class also pass through resistance
r10link together; M2's
bthe utmost point passes through resistance
r7be connected to the first offset signal
v1, the NW utmost point of M2 passes through resistance
r9be connected to the second offset signal
v2; The Sub utmost point of M1 passes through resistance
r8be connected to the first offset signal
v1.
Under foregoing circuit connected mode, the relative radio system characteristic impedance of all resistance is generally high resistant (>10kOhm), when stable direct current biasing is provided for each device nodes, also play the effect that each node radio frequency is suspended.The first offset signal in circuit
v1with the second offset signal
v2magnitude of voltage remain fixing, the first offset signal
v1for low level, the second offset signal
v2for high level; The first offset signal
v1the typical value of voltage is 0V or negative voltage; The first offset signal
v2the typical value of voltage is supply voltage or system maximum voltage value.Can know, in above-mentioned the first offset signal
v1with the second offset signal
v2magnitude of voltage value under, in described radio-frequency (RF) switch, all parasitic PN junction diode of three well structure nmos pass transistors is all reverse bias, in cut-off state, and can be by the first offset signal is set
v1with the second offset signal
v2the nargin of magnitude of voltage make all parasitic PN junction diodes remain off all under any radio frequency state.Switch controlling signal
vgcontrolling conducting and the cut-off of switch; When
vgduring for high level, three well structure nmos pass transistor M1 and M2 are in conducting state, and radiofrequency signal can be from rf inputs mouth
iNand radio frequency output port
oUTbetween pass through, M1, M2 composition laminated construction be equivalent to the conducting resistance of bringing insertion loss; When
vgduring for low level, M1, M2 cut-off, radiofrequency signal can not be from rf inputs mouth
iNand radio frequency output port
oUTbetween pass through, the laminated construction of M1, M2 composition is equivalent to the great breaking resistor of resistance, simultaneously due to the existence of parasitic capacitance,
iNwith
oUTbetween exist faint radio frequency to reveal.
In sum, in the technical solution that the present invention proposes, eliminate the impact of parasitic diode for radio-frequency (RF) switch transistor radio-frequency performance, can utilize device stack structure to form radio-frequency (RF) switch branch road, and the high performance level suitable with the radio-frequency (RF) switch based on SOI technique of maintenance simultaneously.It should be noted that, in above-described embodiment, adopt two three well structure nmos devices compositions to build up structure, only for setting forth the present invention's thought but not the lamination number of three well structure nmos devices used is limited.In actual applications, according to the present invention's spirit, and according to the service behaviour requirement of radio-frequency (RF) switch, can select three well structure nmos pass transistor devices of any suitable number to form radio-frequency (RF) switch branch road.