CN103812472A - Trigger resistant to single event transient effect - Google Patents
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Abstract
抗单粒子瞬态效应的触发器，涉及集成电路领域。解决了集成电路设计中单粒子瞬态效应的发生概率越来越高，其脉冲干扰信号被集成电路系统中存储单元捕获导致电路软错误的概率越来越高的问题。初始信号经第一反相器反相后发送至第三脉冲锁存器并输出至异或门xor1和第二反相器，异或门xor1的输出信号经第三反相器反相后同时发送至第一脉冲锁存器和第二脉冲锁存器，第一脉冲锁存器与第二脉冲锁存器的输出信号均发送至与非门，与非门的输出信号经第四反相器反相后发送至异或门xor2，第三脉冲锁存器的输出信号经第二反相器反相后发送至第四脉冲锁存器，第四脉冲锁存器的输出信号经第五反相器反相后发送至异或门xor2，异或门xor2的输出信号为触发器的输出信号。本发明适用于消除单粒子瞬态效应。
The invention relates to a trigger against single-event transient effect, which relates to the field of integrated circuits. It solves the problem that the occurrence probability of single event transient effect in integrated circuit design is getting higher and higher, and its pulse interference signal is captured by the storage unit in the integrated circuit system, resulting in a higher and higher probability of soft error in the circuit. The initial signal is sent to the third pulse latch after being inverted by the first inverter and output to the XOR gate xor1 and the second inverter. The output signal of the XOR gate xor1 is inverted by the third inverter and simultaneously Send to the first pulse latch and the second pulse latch, the output signals of the first pulse latch and the second pulse latch are sent to the NAND gate, and the output signal of the NAND gate is inverted by the fourth The output signal of the third pulse latch is sent to the fourth pulse latch after being inverted by the second inverter, and the output signal of the fourth pulse latch is passed through the fifth The inverter inverts and sends to the exclusive OR gate xor2, and the output signal of the exclusive OR gate xor2 is the output signal of the flip-flop. The invention is suitable for eliminating single event transient effects.
Description
Technical field
The present invention relates to integrated circuit fields, be specifically related to the trigger field of anti-single particle transient radiation effect in digital circuitry.
Background technology
Single-ion transient state effect (Single Event Transient, SET) is a kind of shock due to the α particle beams and neutron etc. energetic particle beam, a kind of single particle effect in the circuit bringing out.Main manifestations is to cause pulse interference signal on the combinational logic node in Circuits System, and sort signal, through logical path transmission, may be latched device or trigger etc. memory cell and catch, thereby causes the generation of digital circuitry soft error.
Along with the continuous reduction of integrated circuit (IC) design size, node capacitor constantly reduces, character voltage constantly reduces, the clock frequency of digital IC system constantly rises simultaneously, there are data to show, comparatively speaking, SET effect probability of happening is more and more higher, thereby the probability that its pulse interference signal is caught detonator circuit soft error by memory cell in IC system is also more and more higher.
Summary of the invention
The present invention is in order to solve in integrated circuit (IC) design, because the probability of happening of single-ion transient state effect is more and more higher, its pulse interference signal is integrated memory cell in Circuits System and catches the more and more higher problem of probability that causes circuit soft error, has proposed the trigger of anti-single particle transient effect.
The trigger of anti-single particle transient effect comprises the first inverter, the second inverter, the 3rd inverter, the 4th inverter, the 5th inverter, XOR gate xor1, XOR gate xor2, NAND gate, the first pulse latches, the second pulse latches, the 3rd pulse latches and the 4th pulse latches, initialize signal D is sent to XOR gate xor1 and the first inverter simultaneously, initialize signal D is sent to the 3rd pulse latches after the first inverter is anti-phase, the output signal of the 3rd pulse latches is sent to XOR gate xor1 and the second inverter simultaneously, the output signal P of XOR gate xor1 is sent to the first pulse latches and the second pulse latches after the 3rd inverter is anti-phase simultaneously, the output signal of the output signal of the first pulse latches and the second pulse latches is all sent to NAND gate, the output signal check of NAND gate is sent to XOR gate xor2 after the 4th inverter is anti-phase, the output signal of the 3rd pulse latches is sent to the 4th pulse latches after the second inverter is anti-phase, the output signal of the 4th pulse latches is sent to XOR gate xor2 after the 5th inverter is anti-phase, the output signal Q of XOR gate xor2 is the output signal of the trigger of anti-single particle transient effect.
The first pulse latches, the 3rd pulse latches is identical with the circuit structure of the 4th pulse latches, described the first pulse latches comprises the first cmos transmission gate, the second cmos transmission gate, hex inverter and the 7th inverter, the signal input part of the first cmos transmission gate receives external input signal as the signal input part of the first pulse latches, the second cmos transmission gate, hex inverter and the 7th inverter connect and compose closed loop successively, the signal input part of the second cmos transmission gate receives the output signal of the first cmos transmission gate as the signal input part of described closed loop, the signal output part of hex inverter is as the signal output part of described closed loop, and the output signal of described closed loop is sent to NAND gate, clock signal clk_g1 and clock signal clk_g1_n are all sent to the clock signal input terminal of the first cmos transmission gate and the second cmos transmission gate, for detection of the transparent level control of sampling the first pulse latches, and clock signal clk_g1 and clock signal clk_g1_n are anti-phase, be clk_g1=～clk_g1_n.
The second pulse latches comprises the 3rd cmos transmission gate, the 4th cmos transmission gate, the 8th inverter and the first NOR gate, the signal input part of the 3rd cmos transmission gate receives external input signal as the signal input part of the second pulse latches, the 4th cmos transmission gate, the 8th inverter and the first NOR gate connect and compose closed loop successively, the signal input part of the 4th cmos transmission gate receives the output signal of the 3rd cmos transmission gate as the signal input part of described closed loop, the signal input part of the first NOR gate is as the signal output part of described closed loop, and the output signal of described closed loop is sent to NAND gate, clock signal clk_g2 and clock signal clk_g2_n are all sent to the clock signal input terminal of the 3rd cmos transmission gate and the 4th cmos transmission gate, for detection of the transparent level control of sampling the second pulse latches, and clock signal clk_g2 and clock signal clk_g2_n are anti-phase, be clk_g2=～clk_g2_n, clock signal clk_re is sent to an input of the first NOR gate, being used to the second pulse latches to provide high level to reset controls.
The trigger of anti-single particle transient effect also comprises local clock administrative unit, described local clock administrative unit comprises the 9th inverter, the second NOR gate, the first delay circuit, the second delay circuit, the first pulse generate logical circuit and the second pulse generate logical circuit
Clock signal clk is sent to the 9th inverter and the first delay circuit simultaneously, the output signal of clock signal clk after the 9th inverter is anti-phase is clock signal clk_n, clock signal clk_n is sent to the second NOR gate, the first delay circuit carries out clock signal clk_1 after delay process to clock signal clk, clock signal clk_1 is sent to the second delay circuit and the first pulse generate logical circuit simultaneously, the first pulse generate logical circuit carries out pulse generate to clock signal clk_1 and processes rear clock signal clk_g1 and clock signal clk_g1_n, the second delay circuit carries out clock signal clk_2 after delay process to clock signal clk_1, clock signal clk_2 is sent to the second NOR gate and the second pulse generate logical circuit simultaneously, the second pulse generate logical circuit carries out pulse generate to clock signal clk_2 and processes rear clock signal clk_g2 and clock signal clk_g2_n, clock signal clk_n and clock signal clk_2 be clock signal clk_re after the second NOR gate is calculated, be clk_re=clk_n ⊕ clk_2.
The first pulse generate logical circuit is identical with the circuit structure of the second pulse generate logical circuit, described the first pulse generate logical circuit comprise PMOS pipe, NMOS pipe, with door, the tenth inverter and the 11 inverter, clock signal is sent to and door and PMOS pipe simultaneously, the output signal of PMOS pipe is sent to and door and NMOS pipe simultaneously, converges and clock signal clk_g2 and clock signal clk_g2_n successively with the output signal of door after the tenth inverter and the 11 inverter anti-phase with the output signal of NMOS pipe.
Beneficial effect: the present invention propose anti-single particle transient effect trigger effectively reduce even eliminate single-ion transient state effect on the impact of digital integrated circuit (IC) system in, additional areas consumption is less, sequential requires simple, little to digital integrated circuit (IC) system performance impact; The inversion signal of XOR gate xor1 and the needed input signal of xor2 can be provided by trigger internal node, does not need to add extra inverter, thereby saves certain area consumption.
Accompanying drawing explanation
Fig. 1 is the electrical principle schematic diagram of the trigger of the anti-single particle transient effect described in embodiment one;
Fig. 2 is the electrical principle schematic diagram of the local clock management circuit described in embodiment four;
Fig. 3 is the electrical principle schematic diagram of the first pulse generate logical circuit 23 described in embodiment six;
Fig. 4 is a normal input signal and trigger internal node node1 of the present invention and the upper oscillogram that forms of node2;
Fig. 5 is the oscillogram that SET disturbing pulse that width that a trigger described by the present invention is caught is L forms on node node1 and node2;
Fig. 6 is the oscillogram that single-ion transient state effect disturbing pulse that trigger not described by the present invention is caught forms on node node1 and node2;
Fig. 7 is the signal output waveform figure of the first pulse generate logical circuit 23 described in embodiment six;
Fig. 8 is the signal output waveform figure of the local clock management circuit described in embodiment four.
Embodiment
Embodiment one, in conjunction with Fig. 1, this embodiment is described, the trigger of the anti-single particle transient effect described in present embodiment comprises the first inverter 1, the second inverter 2, the 3rd inverter 3, the 4th inverter 4, the 5th inverter 5, XOR gate xor1, XOR gate xor2, NAND gate 6, the first pulse latches 7, the second pulse latches 8, the 3rd pulse latches 9 and the 4th pulse latches 10
Initialize signal D is sent to XOR gate xor1 and the first inverter 1 simultaneously, initialize signal D is sent to the 3rd pulse latches 9 after the first inverter 1 is anti-phase, the output signal of the 3rd pulse latches 9 is sent to XOR gate xor1 and the second inverter 2 simultaneously, the output signal P of XOR gate xor1 is sent to the first pulse latches 7 and the second pulse latches 8 after the 3rd inverter 3 is anti-phase simultaneously, the output signal of the output signal of the first pulse latches 7 and the second pulse latches 8 is all sent to NAND gate 6, the output signal check of NAND gate 6 is sent to XOR gate xor2 after the 4th inverter 4 is anti-phase, the output signal of the 3rd pulse latches 9 is sent to the 4th pulse latches 10 after the second inverter 2 is anti-phase, the output signal of the 4th pulse latches 10 is sent to XOR gate xor2 after the 5th inverter 5 is anti-phase, the output signal Q of XOR gate xor2 is the output signal of the trigger of anti-single particle transient effect.
Embodiment two, in conjunction with Fig. 1, this embodiment is described, this embodiment is with the difference of the trigger of the anti-single particle transient effect described in embodiment one, the first pulse latches 7, the 3rd pulse latches 9 are identical with the circuit structure of the 4th pulse latches 10, described the first pulse latches 7 comprises the first cmos transmission gate 11, the second cmos transmission gate 12, hex inverter 13 and the 7th inverter 14
The signal input part of the first cmos transmission gate 11 receives external input signal as the signal input part of the first pulse latches 7, the second cmos transmission gate 12, hex inverter 13 and the 7th inverter 14 connect and compose closed loop successively, the signal input part of the second cmos transmission gate 12 receives the output signal of the first cmos transmission gate 11 as the signal input part of described closed loop, the signal output part of hex inverter 13 is as the signal output part of described closed loop, and the output signal of described closed loop is sent to NAND gate 6, clock signal clk_g1 and clock signal clk_g1_n are all sent to the clock signal input terminal of the first cmos transmission gate 11 and the second cmos transmission gate 12, for detection of the transparent level control of sampling the first pulse latches 7, and clock signal clk_g1 and clock signal clk_g1_n are anti-phase, be clk_g1=～clk_g1_n.
Embodiment three, in conjunction with Fig. 1, this embodiment is described, this embodiment is with the difference of the trigger of the anti-single particle transient effect described in embodiment one, the second pulse latches 8 comprises the 3rd cmos transmission gate 15, the 4th cmos transmission gate 16, the 8th inverter 17 and the first NOR gate 18
The signal input part of the 3rd cmos transmission gate 15 receives external input signal as the signal input part of the second pulse latches 8, the 4th cmos transmission gate 16, the 8th inverter 17 and the first NOR gate 18 connect and compose closed loop successively, the signal input part of the 4th cmos transmission gate 16 receives the output signal of the 3rd cmos transmission gate 15 as the signal input part of described closed loop, the signal input part of the first NOR gate 18 is as the signal output part of described closed loop, and the output signal of described closed loop is sent to NAND gate 6, clock signal clk_g2 and clock signal clk_g2_n are all sent to the clock signal input terminal of the 3rd cmos transmission gate 15 and the 4th cmos transmission gate 16, for detection of the transparent level control of sampling the second pulse latches 8, and clock signal clk_g2 and clock signal clk_g2_n are anti-phase, be clk_g2=～clk_g2_n, clock signal clk_re is sent to an input of the first NOR gate 18, being used to the second pulse latches 8 to provide high level to reset controls.
Embodiment four, in conjunction with Fig. 2, this embodiment is described, this embodiment is with the difference of the trigger of the anti-single particle transient effect described in embodiment one, two or three, it also comprises local clock administrative unit, described local clock administrative unit comprises the 9th inverter 19, the second NOR gate 20, the first delay circuit 21, the second delay circuit 22, the first pulse generate logical circuit 23 and the second pulse generate logical circuit 24
Clock signal clk is sent to the 9th inverter 19 and the first delay circuit 21 simultaneously, the output signal of clock signal clk after the 9th inverter 19 is anti-phase is clock signal clk_n, clock signal clk_n is sent to the second NOR gate 20, the first delay circuit 21 carries out clock signal clk_1 after delay process to clock signal clk, clock signal clk_1 is sent to the second delay circuit 22 and the first pulse generate logical circuit 23 simultaneously, the first pulse generate logical circuit 23 carries out pulse generate to clock signal clk_1 and processes rear clock signal clk_g1 and clock signal clk_g1_n, the second delay circuit 22 carries out clock signal clk_2 after delay process to clock signal clk_1, clock signal clk_2 is sent to the second NOR gate 20 and the second pulse generate logical circuit 24 simultaneously, the second pulse generate logical circuit 24 carries out pulse generate to clock signal clk_2 and processes rear clock signal clk_g2 and clock signal clk_g2_n, clock signal clk_n and clock signal clk_2 be clock signal clk_re after the second NOR gate 20 is calculated, be clk_re=clk_n ⊕ clk-2.
In present embodiment, the first delay circuit 21 and the second delay circuit 22 form by chain of inverters, be used for providing clock delay, jointly provide the first pulse latches 7, the second pulse latches 8, the 3rd pulse latches 9 and the needed different transparent level of the 4th pulse latches 10 from the first pulse generate logical circuit 23 and the second pulse generate logical circuit 24.
In present embodiment, clock signal clk and clock signal clk_n be for detection of the transparent level control of sampling the 3rd pulse latches 9 and the 4th pulse latches 10, and clock signal clk and clock signal clk_n are complementary relationship, i.e. clk=～clk_n.
Embodiment five, in conjunction with Fig. 3, this embodiment is described, this embodiment is with the difference of the trigger of the anti-single particle transient effect described in embodiment four, the first pulse generate logical circuit 23 is identical with the circuit structure of the second pulse generate logical circuit 24, described the first pulse generate logical circuit 23 comprise PMOS pipe 25, NMOS pipe 26, with door 27, the tenth inverter the 28 and the 11 inverter 29
Clock signal is sent to and door 27 and PMOS pipe 25 simultaneously, the output signal of PMOS pipe 25 is sent to and door 27 and NMOS pipe 26 simultaneously, converges and clock signal clk_g2 and clock signal clk_g2_n successively with the output signal of door 27 after the tenth inverter the 28 and the 11 inverter 29 anti-phase with the output signal of NMOS pipe 26.
In present embodiment, the first pulse generate logical circuit 23 and the second pulse generate logical circuit 24 are all for generating short pulse at rising edge clock, short pulse width is by determining with door 27 and chain of inverters, can suitably increase or reduce the number of inverter to adjust the size of short pulse width, the oscillogram of output signal as shown in Figure 7.
Be illustrated in figure 4 the upper oscillogram that forms of a normal input signal and trigger internal node node1 of the present invention and node2, Fig. 5 is the oscillogram that SET disturbing pulse that width that a trigger described by the present invention is caught is L forms on node node1 and node2.Two dotted lines of Fig. 4 and Fig. 5 represent respectively the sampling time point of the first pulse latches 7, the second pulse latches 8, and take rising edge clock as reference, the sampling time is t1 for the first time, and the sampling time is t2 for the second time, require: t1-t2 >=L and t1 >=L; Output signal P represents the signal that the signal on initialize signal D and node node1 produces via XOR gate xor1, two sampled points in Fig. 3, the logic level of the signal on initialize signal D and node node1 is respectively 11,11, P1=P2=0, represent to receive signal normal, at Fig. 5, the logic level of the signal on initialize signal D and node node1 is respectively 01,01, P1=P2=1, represents to receive disturbing pulse signal.
Receive single event transient pulse when input signal and disturb, but do not catch at the clock edge device that is triggered, take Fig. 6 waveform as example, now, the logic level of the signal on initialize signal D and node node1 is respectively 10,00, P1=1, P2=0, in like manner, works as P1=0, when P2=1, also indicate disturbing pulse signal, but the device that is not triggered catches, thereby do not cause soft error.
So, in the time of P1=1 and P2=1, with check=P1 & P2, can determine whether that single-ion transient state disturbing pulse and the device that is triggered catch by check, then export correct state by XOR relation.
Each signal output waveform figure in Fig. 8 local clock management circuit, local clock management circuit is as a shared cell, for digital integrated circuit system and trigger of the present invention provide the needed various overall situation and half overall signal.
Wherein, clk_re controls for the second pulse latches 8 provides high level to reset, thereby provide periodic reset for single-ion transient state effect judges signal check, recover by check signal the burr that delay causes to weaken when the next clock cycle receives normal signal after occurring and judging a single-ion transient state effect event.
Trigger involved in the present invention, for guaranteeing normal function, needs the pollution delay Tcd under applied logical path to meet: Tcd>t2+t_pulse, wherein, t_pulse is short pulse width.
Claims (5)
1. the trigger of anti-single particle transient effect, it is characterized in that, it comprises the first inverter (1), the second inverter (2), the 3rd inverter (3), the 4th inverter (4), the 5th inverter (5), XOR gate (xor1), XOR gate (xor2), NAND gate (6), the first pulse latches (7), the second pulse latches (8), the 3rd pulse latches (9) and the 4th pulse latches (10)
Initialize signal D is sent to XOR gate (xor1) and the first inverter (1) simultaneously, initialize signal D is sent to the 3rd pulse latches (9) after the first inverter (1) is anti-phase, the output signal of the 3rd pulse latches (9) is sent to XOR gate (xor1) and the second inverter (2) simultaneously, the output signal P of XOR gate (xor1) is sent to the first pulse latches (7) and the second pulse latches (8) after the 3rd inverter (3) is anti-phase simultaneously, the output signal of the output signal of the first pulse latches (7) and the second pulse latches (8) is all sent to NAND gate (6), the output signal check of NAND gate (6) is sent to XOR gate (xor2) after the 4th inverter (4) is anti-phase, the output signal of the 3rd pulse latches (9) is sent to the 4th pulse latches (10) after the second inverter (2) is anti-phase, the output signal of the 4th pulse latches (10) is sent to XOR gate (xor2) after the 5th inverter (5) is anti-phase, the output signal Q of XOR gate (xor2) is the output signal of the trigger of anti-single particle transient effect.
2. the trigger of anti-single particle transient effect according to claim 1, it is characterized in that, the first pulse latches (7), the 3rd pulse latches (9) are identical with the circuit structure of the 4th pulse latches (10), described the first pulse latches (7) comprises the first cmos transmission gate (11), the second cmos transmission gate (12), hex inverter (13) and the 7th inverter (14)
The signal input part of the first cmos transmission gate (11) receives external input signal as the signal input part of the first pulse latches (7), the second cmos transmission gate (12), hex inverter (13) and the 7th inverter (14) connect and compose closed loop successively, the signal input part of the second cmos transmission gate (12) receives the output signal of the first cmos transmission gate (11) as the signal input part of described closed loop, the signal output part of hex inverter (13) is as the signal output part of described closed loop, and the output signal of described closed loop is sent to NAND gate (6), clock signal clk_g1 and clock signal clk_g1_n are all sent to the clock signal input terminal of the first cmos transmission gate (11) and the second cmos transmission gate (12), for detection of the transparent level control of sampling the first pulse latches (7), and clock signal clk_g1 and clock signal clk_g1_n are anti-phase, be clk_g1=～clk_g1_n.
3. the trigger of anti-single particle transient effect according to claim 1, is characterized in that, the second pulse latches (8) comprises the 3rd cmos transmission gate (15), the 4th cmos transmission gate (16), the 8th inverter (17) and the first NOR gate (18),
The signal input part of the 3rd cmos transmission gate (15) receives external input signal as the signal input part of the second pulse latches (8), the 4th cmos transmission gate (16), the 8th inverter (17) and the first NOR gate (18) connect and compose closed loop successively, the signal input part of the 4th cmos transmission gate (16) receives the output signal of the 3rd cmos transmission gate (15) as the signal input part of described closed loop, the signal input part of the first NOR gate (18) is as the signal output part of described closed loop, and the output signal of described closed loop is sent to NAND gate (6), clock signal clk_g2 and clock signal clk_g2_n are all sent to the clock signal input terminal of the 3rd cmos transmission gate (15) and the 4th cmos transmission gate (16), for detection of the transparent level control of sampling the second pulse latches (8), and clock signal clk_g2 and clock signal clk_g2_n are anti-phase, be clk_g2=～clk_g2_n, clock signal clk_re is sent to an input of the first NOR gate (18), being used to the second pulse latches (8) to provide high level to reset controls.
4. the trigger of anti-single particle transient effect according to claim 1, it is characterized in that, it also comprises local clock administrative unit, described local clock administrative unit comprises the 9th inverter (19), the second NOR gate (20), the first delay circuit (21), the second delay circuit (22), the first pulse generate logical circuit (23) and the second pulse generate logical circuit (24)
Clock signal clk is sent to the 9th inverter (19) and the first delay circuit (21) simultaneously, the output signal of clock signal clk after the 9th inverter (19) is anti-phase is clock signal clk_n, clock signal clk_n is sent to the second NOR gate (20), the first delay circuit (21) carries out clock signal clk_1 after delay process to clock signal clk, clock signal clk_1 is sent to the second delay circuit (22) and the first pulse generate logical circuit (23) simultaneously, the first pulse generate logical circuit (23) carries out pulse generate to clock signal clk_1 and processes rear clock signal clk_g1 and clock signal clk_g1_n, the second delay circuit (22) carries out clock signal clk_2 after delay process to clock signal clk_1, clock signal clk_2 is sent to the second NOR gate (20) and the second pulse generate logical circuit (24) simultaneously, the second pulse generate logical circuit (24) carries out pulse generate to clock signal clk_2 and processes rear clock signal clk_g2 and clock signal clk_g2_n, clock signal clk_n and clock signal clk_2 be clock signal clk_re after the second NOR gate (20) is calculated, be clk_re=clk_n ⊕ clk_2.
5. the trigger of anti-single particle transient effect according to claim 4, it is characterized in that, the first pulse generate logical circuit (23) is identical with the circuit structure of the second pulse generate logical circuit (24), described the first pulse generate logical circuit (23) comprise PMOS pipe (25), NMOS pipe (26), with door (27), the tenth inverter (28) and the 11 inverter (29)
Clock signal is sent to and door (27) and PMOS pipe (25) simultaneously, the output signal of PMOS pipe (25) is sent to and door (27) and NMOS pipe (26) simultaneously, with the output signal of door (27) successively after the tenth inverter (28) and the 11 inverter (29) anti-phase and the NMOS output signal of managing (26) converge also clock signal clk_g2 and clock signal clk_g2_n.
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| CN104502750A (en) * | 2014-12-05 | 2015-04-08 | 中国航天科技集团公司第九研究院第七七一研究所 | Trigger unit single event upset effect experimental verification circuit |
| CN106330164A (en) * | 2015-06-29 | 2017-01-11 | 复旦大学 | A preparation method of radiation-resistant latch based on NOR gate and AND gate |
| CN107204774A (en) * | 2017-05-11 | 2017-09-26 | 成都华微电子科技有限公司 | Support the cold standby system high-impedance state High Linear sampling hold circuit of multichannel input |
| CN109314506A (en) * | 2016-06-02 | 2019-02-05 | 高通股份有限公司 | Low clock power data gated FF |
| CN112702043A (en) * | 2021-03-24 | 2021-04-23 | 上海海栎创科技股份有限公司 | Bidirectional deburring circuit |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104502750A (en) * | 2014-12-05 | 2015-04-08 | 中国航天科技集团公司第九研究院第七七一研究所 | Trigger unit single event upset effect experimental verification circuit |
| CN104502750B (en) * | 2014-12-05 | 2017-05-10 | 中国航天科技集团公司第九研究院第七七一研究所 | Trigger unit single event upset effect experimental verification circuit |
| CN106330164A (en) * | 2015-06-29 | 2017-01-11 | 复旦大学 | A preparation method of radiation-resistant latch based on NOR gate and AND gate |
| CN106330164B (en) * | 2015-06-29 | 2019-12-20 | 复旦大学 | Preparation method of anti-radiation latch based on NOR gate and AND gate |
| CN109314506A (en) * | 2016-06-02 | 2019-02-05 | 高通股份有限公司 | Low clock power data gated FF |
| CN107204774A (en) * | 2017-05-11 | 2017-09-26 | 成都华微电子科技有限公司 | Support the cold standby system high-impedance state High Linear sampling hold circuit of multichannel input |
| CN112702043A (en) * | 2021-03-24 | 2021-04-23 | 上海海栎创科技股份有限公司 | Bidirectional deburring circuit |
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|---|---|
| CN103812472B (en) | 2016-06-01 |
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