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CN103797569A - 金属凸块的焊料沉积系统和方法 - Google Patents

金属凸块的焊料沉积系统和方法 Download PDF

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Publication number
CN103797569A
CN103797569A CN201280040478.6A CN201280040478A CN103797569A CN 103797569 A CN103797569 A CN 103797569A CN 201280040478 A CN201280040478 A CN 201280040478A CN 103797569 A CN103797569 A CN 103797569A
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China
Prior art keywords
column
projection block
nude film
substrate
methods
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CN201280040478.6A
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S·W·塔姆
B·李
彭康成
冯泰伟
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Flextronics International USA Inc
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Flextronics International USA Inc
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Publication of CN103797569A publication Critical patent/CN103797569A/zh
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Abstract

一种制造技术，包括以晶片或裸片的形式在裸片上的电接触上创建柱状凸块。提供具有与裸片上的电接触对应的腔体的单独模板或载体。腔体利用焊膏填充，并且使裸片紧密接近模板，使得柱状凸块延伸到腔体中并且与焊膏发生接触。当移除裸片时，焊膏保持固定至柱状凸块，并且从而将焊膏被转移并递送至柱状凸块。然后可以将裸片固定至诸如PCB之类的衬底。

Description

金属凸块的焊料沉积系统和方法
交叉引用
本申请是名称为“Solder Deposition System and Method forMetal Bumps”的在2011年7月6日提交的第61/504797号美国临时专利申请的非临时申请，该临时专利申请通过引用并入本申请。
技术领域
本公开总体涉及电子器件，并且更具体地涉及用于附着电子部件的技术。甚至更具体地，其涉及减少成本并增加制造吞吐量的制造设计。
背景技术
通常使用焊料来将一个电子部件的电接触与另一个电子部件的电接触连接。存在已经用于应用焊料的各种方法。应牢记，随着电子部件变得越来越小并且其功能和能力的增强，在部件上的相邻电接触之间的节距（pitch）缩小了。这就大大增加了应用焊料和连接部件的挑战。一种方法包括在部件上沉积光刻胶，将铜柱电镀到部件上的每个金属焊盘上（在不被光刻胶覆盖的区域中），并且然后将焊料帽印刷并回流到铜柱上，接着移除光刻胶。这一方法遭受用于溅射、光刻和镀制的高成本。
另一种方法包括在部件的金属焊盘上创建柱状凸块，直接将焊膏放置到在另一个部件上的每个金属焊盘上，并且然后紧接另一个部件上的焊膏放置柱状凸块并且回流焊料。这一方法遭受如对于可以被应用于在另一个部件上的每个小金属焊盘的焊料量的约束，并且遭受在柱状凸块被应用后（由于柱状凸块的不规则形状）不能简单地对部件进行电测试的问题。
因此，需要更低廉的并且具有更高吞吐量的制造设计。
发明内容
在本文中公开的是一种用于将焊料应用于裸片上的柱状凸块的方法，包括：提供具有多个柱状凸块的裸片，每个柱状凸块被固定至裸片上的对应的金属焊盘；提供具有与裸片上的柱状凸块的相对位置对应的多个腔体的模板；将焊膏放置到模板的腔体中；将柱状凸块浸渍到模板的腔体中，以便使焊膏与柱状凸块发生接触；并且从腔体移除柱状凸块，使得焊膏被固定至柱状凸块。
该方法还可以包括在腔体以外的区域中从模板擦去过量的焊膏。可以已经从多个裸片的晶片创建裸片。多个裸片可以被连接在一起作为晶片的一部分，并且模板具有用于晶片上的所有裸片上的所有柱状凸块的腔体。焊膏可以已经被加热以提高其温度，以助于焊膏中的焊料固定至柱状凸块。该方法还可以包括在焊料已经被固定至柱状凸块之后并且在从腔体移除柱状凸块之前，对焊料进行冷却。
裸片上的柱状凸块可以包括铜。可以通过印刷将焊料放置到腔体中。该方法还可以包括提供具有与裸片上的柱状凸块对应的金属接触的衬底；并且利用焊料将柱状凸块固定至衬底上的金属接触。该方法还可以包括回流焊料。该方法还可以包括在裸片和衬底之间添加粘附材料，以进一步将裸片和衬底固定在一起。粘附材料可以包括底部填料。可以在已经利用焊料将裸片固定至衬底之后点胶粘附材料。可以在已经利用焊料将裸片固定至衬底之前点胶粘附材料。粘附材料还可以包括助焊剂。可以在跨衬底的图案中点胶底部填料。粘附材料可以包括非导电膏（NCP）。可以在跨衬底的图案中点胶NCP。该方法还可以包括固化粘附剂。可以将所有柱状凸块同时浸渍到腔体中。
附图说明
本公开通过参照以下附图来描述，其中相似的附图标记表示基本相似的元件：
图1是用于将焊料应用于电子部件上的柱状凸块的工艺流程；
图2a、图2b、图2c和图2d是关于用于将焊料应用于电子部件上的柱状凸块的工艺流程的进一步细节；
图3是用于晶片处理的工艺流程；
图4是用于晶片处理的工艺流程的另一个实施例；以及
图5是用于晶片处理的工艺流程的另一个实施例。
具体实施方式
虽然本文公开的实施例允许有各种修改和替代形式，但是在附图中已经借由示例示出了并且在本文中详细描述了具体的实施例。然而应理解，并不旨在将本发明限制于公开的具体形式，而是本发明将覆盖如所附权利要求所限定的本发明的实施例的所有修改、等效和替代。本公开参考附图进行描述，其中相似的附图标记表示基本相似的元件。
图1示出晶片形状的模板10，虽然这一技术也可以在裸片级实施。如在晶片10的放大部分12中所示，在其中限定了多个腔体14，并且在这一情况下其被限定在与晶片上的单独裸片对应的限定区域的外围周围，该限定区域将具有添加于其的焊料。进一步放大的部分16在截面图中示出腔体14中的两个。接着，将焊膏18印刷到模板16上的腔体14中。之后可以跨模板16的顶部拖动刮刷器（wiper）或刮板（squeegee）20，以移除在腔体14以外的过量的焊膏。然后模板10准备好用于如下文中将描述的那样转移焊膏18。
并行地，多个单独裸片的晶片24具有多个电接触，该多个电接触具有固定至其的适当导电材料（例如铜）的柱状凸块26。图1示出晶片24、放大部分28和进一步放大的部分30，该放大部分28示出在每个裸片的外围周围的柱状凸块26，该进一步放大的部分30示出柱状凸块26中的两个柱状凸块26。现在准备好晶片24以用于转移焊膏18。
接下来，使两个晶片10和24处于相互相对并相邻的关系，并且将它们移动到其中每个柱状凸块26都被插入到一个腔体14中并且与焊膏18接触的位置。然后将该晶片分开，并且每个柱状凸块26将如所示在其上具有焊膏18的层，并且具体地如显著放大的形式34所示。
图2a至图2d示出这一工艺的进一步的细节。如在图2a中所示，模板或载体16具有限定于其中的多个腔体14。图2b示出由打印头（print head）40和用于移除过量的焊膏18的刮板20来印刷焊膏18的工艺。图2c示出具有与晶片16接近的柱状凸块26的晶片30，使得柱状凸块26延伸到腔体14中并且与焊膏18发生接触。如所注意到的那样，可以存在一些总体或局部加热，以加热焊膏18和柱状凸块26并且帮助将焊膏18转移至柱状凸块26。图2d示出从晶片16移开的晶片30，使得从腔体14移除柱状凸块26，而此时焊膏18被附着到柱状凸块26。
图3提供关于该工艺的一个变体的细节。作为第一步骤，减薄多个单独裸片的晶片24以便平坦化晶片24。随后，将铜柱状凸块26添加到晶片24上的电接触。随后，晶片24可以被安装在划片胶带50或类似物上。随后，晶片24被锯切为单独裸片52。之后，从划片胶带50上拾取每个裸片52，并且将其移动到相对于模板的位置，以接收在每个柱状凸块26上的焊膏18。随后，可以加热焊膏18以固化焊料。随后，将非导电膏（NCP）54点胶（dispense）到衬底56（例如PCB或柔性电路板或类似物或其它电子部件）上，裸片52将被附着到衬底56。虽然图3的图示呈现为示出仅在衬底56上的电接触58的顶部上点胶的NCP54，但是实际上可以在跨衬底56的与裸片52对应的部分的图案中点胶NCP54。然后在衬底56上放置裸片52，使柱状凸块26与电接触58对准，并且使用局部加热以回流焊料。然后可以将整个组件放置到炉中以固化NCP54，此时NCP54由于与衬底56接近放置的裸片52的压力，而使其自身分布于裸片52下方并支持裸片52。
图4提供关于该工艺的另一个变体的细节。作为第一步骤，减薄多个单独裸片的晶片24以便平坦化晶片24。随后，将铜柱状凸块26添加到晶片24上的电接触。随后，晶片24可以被安装在划片胶带50或类似物上。随后，晶片24被锯切为单独裸片52。之后，从划片胶带50上拾取每个裸片52，并且将其移动到相对于模板的位置，以接收在每个柱状凸块26上的焊膏18。随后，可以加热焊膏18以固化焊料。随后，将助焊剂（flux）66点胶到衬底56（例如PCB或柔性电路板或类似物或其它电子部件）上，裸片52将被附着到衬底56。虽然图4的图示呈现为示出仅在衬底56上的电接触58的顶部上点胶的助焊剂66，但是实际上可以在跨衬底56的与裸片52对应的部分的图案中点胶助焊剂66。然后在衬底56上放置裸片52，使柱状凸块26与电接触58对准，并且回流焊料。随后，在裸片52和衬底56之间点胶底部填料68，并且然后可以将整个组件放置到炉中以固化底部填料68。
图5提供关于该工艺的另一个变体的细节。作为第一步骤，减薄多个单独裸片的晶片24以便平坦化晶片24。随后，将铜柱状凸块26添加到晶片24上的电接触。随后在晶片级，使用具有包含焊膏的腔体的模板来将焊膏18转移到柱状凸块26。随后回流焊料。随后，晶片24可以被安装在划片胶带50或类似物上。随后，晶片24被锯切为单独裸片52。之后，可以将无流动底部填料（底部填料加助焊剂）80点胶到衬底56上，裸片52将被附着到衬底56。然后在衬底56上放置裸片52，使柱状凸块26与电接触58对准，并且然后回流焊料。
本公开的制造技术提供几个优于现有技术的优点。如可见，这些方法提供无需昂贵工艺（如溅射和光刻）的用于应用焊料的简单的和低成本的解决方案。也易于基于每个腔体的体积来控制使用的焊料体积。易于在不同的焊料材料之间切换。可选地，可以执行柱状凸块压印（coining）（在柱状凸块上产生更规则的表面）。用于焊膏的模板或载体可以由硅组成，并且腔体可以通过湿法蚀刻产生。模板可以重复使用。可以添加额外的焊料体积，以有效增加凸块高度。最后，这一简化平坦化衬底（例如PCB、柔性电路板（flex）等）的问题。
虽然已经在附图和前述说明中详细地图示并描述了本发明的实施例，但是这类图示和说明应被理解为示例，而不是限制性的。例如，上文中所描述的某个实施例可以与其它所描述实施例组合并且/或者以其它方式布置（例如可以以其它顺序执行工艺元素）。因此应理解，仅已经示出并描述了本发明的示例实施例和变体。

Claims (20)

1.一种用于将焊料应用于裸片上的柱状凸块的方法，包括：
提供具有多个柱状凸块的裸片，每个柱状凸块被固定至所述裸片上的对应的金属焊盘；
提供具有多个腔体的模板，所述多个腔体对应于所述裸片上的所述柱状凸块的相对位置；
将焊膏放置到所述模板的所述腔体中；
将所述柱状凸块浸渍到所述模板的所述腔体中，以便使所述焊膏与所述柱状凸块发生接触；并且
从所述腔体移除所述柱状凸块，使得所述焊膏被固定至所述柱状凸块。
2.根据权利要求1所限定的方法，还包括在所述腔体以外的区域中从所述模板擦去过量的焊膏。
3.根据权利要求1所限定的方法，其中已经从多个裸片的晶片创建所述裸片。
4.根据权利要求1所限定的方法，其中多个所述裸片被连接在一起作为晶片的一部分，并且所述模板具有用于所述晶片上的所有所述裸片上的所有所述柱状凸块的腔体。
5.根据权利要求1所限定的方法，其中所述焊膏已经被加热以提高其温度，以助于所述焊膏中的所述焊料固定至所述柱状凸块。
6.根据权利要求5所限定的方法，还包括在所述焊料已经被固定至所述柱状凸块之后并且在从所述腔体移除所述柱状凸块之前，对所述焊料进行冷却。
7.根据权利要求1所限定的方法，其中所述裸片上的所述柱状凸块包括铜。
8.根据权利要求1所限定的方法，其中通过印刷将所述焊料放置到所述腔体中。
9.根据权利要求1所限定的方法，还包括提供具有与所述裸片上的所述柱状凸块对应的金属接触的衬底；并且利用所述焊料将所述柱状凸块固定至所述衬底上的所述金属接触。
10.根据权利要求9所限定的方法，还包括回流所述焊料。
11.根据权利要求9所限定的方法，还包括在所述裸片和所述衬底之间添加粘附材料，以进一步将所述裸片和所述衬底固定在一起。
12.根据权利要求11所限定的方法，其中所述粘附材料包括底部填料。
13.根据权利要求12所限定的方法，其中在已经利用所述焊料将所述裸片固定至所述衬底之后，点胶所述粘附材料。
14.根据权利要求12所限定的方法，其中在已经利用所述焊料将所述裸片固定至所述衬底之前，点胶所述粘附材料。
15.根据权利要求14所限定的方法，其中所述粘附材料还包括助焊剂。
16.根据权利要求12所限定的方法，其中在跨所述衬底的图案中点胶所述底部填料。
17.根据权利要求11所限定的方法，其中所述粘附材料包括非导电膏（NCP）。
18.根据权利要求17所限定的方法，其中在跨所述衬底的图案中点胶所述NCP。
19.根据权利要求11所限定的方法，还包括固化所述粘附剂。
20.根据权利要求1所限定的方法，其中将所有所述柱状凸块同时浸渍到所述腔体中。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022027351A1 (zh) * 2020-08-05 2022-02-10 重庆康佳光电技术研究院有限公司 微元件制程中的绑定装置及绑定方法以及焊接剂盛放单元
CN114068791A (zh) * 2020-08-05 2022-02-18 重庆康佳光电技术研究院有限公司 微元件制程中的绑定装置及绑定方法以及焊接剂盛放单元

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9426898B2 (en) * 2014-06-30 2016-08-23 Kulicke And Soffa Industries, Inc. Thermocompression bonders, methods of operating thermocompression bonders, and interconnect methods for fine pitch flip chip assembly

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06124953A (ja) * 1992-10-12 1994-05-06 Matsushita Electron Corp 半導体装置のバンプ形成方法
US20050218195A1 (en) * 2004-04-02 2005-10-06 Fry's Metals, Inc. Underfill fluxing curative
CN101728287A (zh) * 2008-10-23 2010-06-09 嘉盛马来西亚公司 使用涂覆有焊料的柱形凸起的晶片级封装

Family Cites Families (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0590751A (ja) * 1991-09-30 1993-04-09 Taiyo Yuden Co Ltd グリーンシートスルーホールへの導体充填方法
US5478700A (en) * 1993-12-21 1995-12-26 International Business Machines Corporation Method for applying bonding agents to pad and/or interconnection sites in the manufacture of electrical circuits using a bonding agent injection head
US6528346B2 (en) * 1994-01-20 2003-03-04 Fujitsu Limited Bump-forming method using two plates and electronic device
JP3173547B2 (ja) * 1994-03-18 2001-06-04 松下電器産業株式会社 半田バンプの形成方法
US5536677A (en) * 1994-12-01 1996-07-16 Motorola, Inc. Method of forming conductive bumps on a semiconductor device using a double mask structure
US5607099A (en) * 1995-04-24 1997-03-04 Delco Electronics Corporation Solder bump transfer device for flip chip integrated circuit devices
US5872051A (en) * 1995-08-02 1999-02-16 International Business Machines Corporation Process for transferring material to semiconductor chip conductive pads using a transfer substrate
US5710071A (en) * 1995-12-04 1998-01-20 Motorola, Inc. Process for underfilling a flip-chip semiconductor device
US5806753A (en) * 1995-12-22 1998-09-15 International Business Machines Corporation Application of low temperature metallurgical paste to form a bond structure to attach an electronic component to a carrier
US5673844A (en) * 1995-12-29 1997-10-07 Gte Laboratories Incorporated Gas pressure adjustable diebonding apparatus and method
JP2861965B2 (ja) * 1996-09-20 1999-02-24 日本電気株式会社 突起電極の形成方法
KR100199293B1 (ko) * 1996-11-08 1999-06-15 윤종용 반도체 패키지 제조 장치
JP3410639B2 (ja) * 1997-07-23 2003-05-26 株式会社日立製作所 ペースト充填方法及びはんだ付け方法及びペースト印刷機
US20020040923A1 (en) * 1997-08-08 2002-04-11 Pac Tech-Packaging Technologies Gmbh Contact structure for connecting two substrates and also process for producing such a contact structure
JP3544614B2 (ja) * 1998-01-30 2004-07-21 松下電器産業株式会社 クリーム半田印刷装置及び印刷方法
JP3565047B2 (ja) * 1998-10-07 2004-09-15 松下電器産業株式会社 半田バンプの形成方法および半田バンプの実装方法
US6390439B1 (en) * 1999-04-07 2002-05-21 International Business Machines Corporation Hybrid molds for molten solder screening process
US6245595B1 (en) * 1999-07-22 2001-06-12 National Semiconductor Corporation Techniques for wafer level molding of underfill encapsulant
US6527163B1 (en) * 2000-01-21 2003-03-04 Tessera, Inc. Methods of making bondable contacts and a tool for making such contacts
US20020027294A1 (en) * 2000-07-21 2002-03-07 Neuhaus Herbert J. Electrical component assembly and method of fabrication
JP4156227B2 (ja) * 2001-11-02 2008-09-24 松下電器産業株式会社 スクリーン印刷装置
US6677179B2 (en) * 2001-11-16 2004-01-13 Indium Corporation Of America Method of applying no-flow underfill
US6889427B2 (en) * 2002-02-15 2005-05-10 Freescale Semiconductor, Inc. Process for disengaging semiconductor die from an adhesive film
US20030170450A1 (en) * 2002-03-05 2003-09-11 Stewart Steven L. Attachment of surface mount devices to printed circuit boards using a thermoplastic adhesive
US6910615B2 (en) * 2003-03-27 2005-06-28 International Business Machines Corporation Solder reflow type electrical apparatus packaging having integrated circuit and discrete components
JP3933094B2 (ja) * 2003-05-27 2007-06-20 セイコーエプソン株式会社 電子部品の実装方法
US7295445B2 (en) * 2004-09-30 2007-11-13 Intel Corporation Holder for surface mount device during reflow
JP4260721B2 (ja) * 2004-10-29 2009-04-30 富士通株式会社 電子部品の基板実装方法、及び基板実装装置
US7422973B2 (en) * 2006-01-27 2008-09-09 Freescale Semiconductor, Inc. Method for forming multi-layer bumps on a substrate
JP4757070B2 (ja) * 2006-03-27 2011-08-24 富士通株式会社 半田付け用フラックス及び半導体素子の接合方法
JP4816194B2 (ja) * 2006-03-29 2011-11-16 パナソニック株式会社 電子部品実装システムおよび電子部品搭載装置ならびに電子部品実装方法
DE102006024213A1 (de) * 2006-05-23 2007-11-29 Infineon Technologies Ag Verfahren zum Herstellen eines Bausteins mit einer elektrischen Kontaktierung
JP4804324B2 (ja) * 2006-12-15 2011-11-02 富士通株式会社 ペースト印刷装置およびペースト印刷方法
US7674651B2 (en) * 2006-12-26 2010-03-09 International Business Machines Corporation Mounting method for semiconductor parts on circuit substrate
US20080164300A1 (en) * 2007-01-08 2008-07-10 Endicott Interconnect Technologies, Inc. Method of making circuitized substrate with solder balls having roughened surfaces, method of making electrical assembly including said circuitized substrate, and method of making multiple circuitized substrate assembly
US7521284B2 (en) * 2007-03-05 2009-04-21 Texas Instruments Incorporated System and method for increased stand-off height in stud bumping process
US7772540B2 (en) * 2007-03-06 2010-08-10 Pasternak Barton A RF controlled sequential lighting system
US7829384B2 (en) * 2007-09-25 2010-11-09 Stats Chippac, Ltd. Semiconductor device and method of laser-marking wafers with tape applied to its active surface
US8581403B2 (en) * 2008-01-30 2013-11-12 Nec Corporation Electronic component mounting structure, electronic component mounting method, and electronic component mounting board
US20090301771A1 (en) * 2008-06-04 2009-12-10 Shozo Ochi Conductive bump, method for forming the same, and electronic component mounting structure using the same
TW201011830A (en) * 2008-09-03 2010-03-16 United Test Ct Inc Self-adhesive semiconductor wafer
US8168458B2 (en) * 2008-12-08 2012-05-01 Stats Chippac, Ltd. Semiconductor device and method of forming bond wires and stud bumps in recessed region of peripheral area around the device for electrical interconnection to other devices
JP5310252B2 (ja) * 2009-05-19 2013-10-09 パナソニック株式会社 電子部品実装方法および電子部品実装構造
US8372692B2 (en) * 2010-01-27 2013-02-12 Marvell World Trade Ltd. Method of stacking flip-chip on wire-bonded chip
US9559004B2 (en) * 2011-05-12 2017-01-31 STATS ChipPAC Pte. Ltd. Semiconductor device and method of singulating thin semiconductor wafer on carrier along modified region within non-active region formed by irradiating energy
US8716858B2 (en) * 2011-06-24 2014-05-06 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure with barrier layer on post-passivation interconnect
JP2014529182A (ja) * 2011-07-29 2014-10-30 ヘンケル アイピー アンド ホールディング ゲゼルシャフト ミット ベシュレンクテル ハフツング コーティング後グラインディング前のダイシング

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06124953A (ja) * 1992-10-12 1994-05-06 Matsushita Electron Corp 半導体装置のバンプ形成方法
US20050218195A1 (en) * 2004-04-02 2005-10-06 Fry's Metals, Inc. Underfill fluxing curative
CN101728287A (zh) * 2008-10-23 2010-06-09 嘉盛马来西亚公司 使用涂覆有焊料的柱形凸起的晶片级封装

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022027351A1 (zh) * 2020-08-05 2022-02-10 重庆康佳光电技术研究院有限公司 微元件制程中的绑定装置及绑定方法以及焊接剂盛放单元
CN114068791A (zh) * 2020-08-05 2022-02-18 重庆康佳光电技术研究院有限公司 微元件制程中的绑定装置及绑定方法以及焊接剂盛放单元

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