CN103794575A - Encapsulation structure and method - Google Patents
Encapsulation structure and method Download PDFInfo
- Publication number
- CN103794575A CN103794575A CN201410033771.0A CN201410033771A CN103794575A CN 103794575 A CN103794575 A CN 103794575A CN 201410033771 A CN201410033771 A CN 201410033771A CN 103794575 A CN103794575 A CN 103794575A
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- chip
- cover plate
- packaging material
- plastic packaging
- heat
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Packaging Frangible Articles (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Cooling Or The Like Of Electrical Apparatus (AREA)
Abstract
本发明公开了一种封装结构及封装方法，该方法包括：将芯片贴装在基板上；在所述基板与芯片之间连接引线，且该引线包覆有塑封料；以及盖片覆盖所述芯片并通过导热胶与所述芯片接合。本发明将盖片通过涂覆在芯片上的导热胶连接在芯片上，可以通过导热系数高的盖片将芯片产生的大量热量有效地传递到外界，对芯片的散热性能和可靠性都有显著的提高。
The invention discloses a package structure and a package method. The method comprises: attaching a chip on a substrate; connecting a lead wire between the substrate and the chip, and the lead wire is covered with a plastic sealing compound; and a cover sheet covers the chip and is bonded to the chip by thermally conductive glue. In the present invention, the cover sheet is connected to the chip through the thermally conductive glue coated on the chip, and a large amount of heat generated by the chip can be effectively transferred to the outside through the cover sheet with high thermal conductivity, which significantly improves the heat dissipation performance and reliability of the chip. improvement.
Description
Technical field
The present invention relates to encapsulation technology, particularly, relate to a kind of encapsulating structure and method for packing.
Background technology
Traditional wire bond package product is mainly made up of several parts of chip, substrate (or lead frame), lead-in wire and plastic packaging material.Wherein, plastic packaging material is the impact that protection chip and lead-in wire are not subject to extraneous dust, moisture and mechanical shock etc., guarantees the reliability of electrical connection.
But the conductive coefficient of plastic packaging material is lower, thereby the chip being completely wrapped in plastic packaging material cannot be delivered to the external world effectively by the amount of heat that produce of working.
Summary of the invention
The object of this invention is to provide a kind of encapsulating structure and method for packing, for solving the poor problem of conventional wire bonding product heat dispersion.
To achieve these goals, the invention provides a kind of encapsulating structure, this structure comprises: substrate; Chip, is mounted on described substrate; Lead-in wire, be connected between described substrate and chip, and this lead-in wire is coated with plastic packaging material; And cover plate, cover described chip and by heat-conducting glue and described chip join.
Correspondingly, the present invention also provides a kind of method for packing, and the method comprises: by chip attachment on substrate; Connecting lead wire between described substrate and chip, and this lead-in wire is coated with plastic packaging material; And cover plate covers described chip and by heat-conducting glue and described chip join.
Pass through technique scheme, the present invention is connected to cover plate on chip by the heat-conducting glue being coated on chip, the amount of heat that can chip be produced by the high cover plate of conductive coefficient is delivered to the external world effectively, and heat dispersion and reliability to chip all increase significantly.
Other features and advantages of the present invention are described in detail the embodiment part subsequently.
Accompanying drawing explanation
Accompanying drawing is to be used to provide a further understanding of the present invention, and forms a part for specification, is used from explanation the present invention, but is not construed as limiting the invention with embodiment one below.In the accompanying drawings:
Fig. 1 a, Fig. 1 b, Fig. 1 c show respectively the schematic diagram of encapsulating structure provided by the invention; And
Fig. 2 is the flow chart of method for packing provided by the invention.
Description of reference numerals
1, substrate 2, chip
3, lead-in wire 4, cover plate
5, plastic packaging material 6, heat-conducting glue
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is elaborated.Should be understood that, embodiment described herein only, for description and interpretation the present invention, is not limited to the present invention.
Fig. 1 a, Fig. 1 b, Fig. 1 c show respectively three kinds of multi-form cover plates.As shown in Figure 1a, this encapsulating structure comprises substrate 1, chip 2, lead-in wire 3 and cover plate 4.Wherein, chip 2 is mounted on substrate 1, is connected with lead-in wire 3 to be electrically connected substrate 1 and chip 2 by lead-in wire 3 between substrate 1 and chip 2, and this lead-in wire 3 is coated with plastic packaging material 5, and cover plate 4 covers chip 2, and this cover plate 4 engages with chip 2 by heat-conducting glue 6.
Fig. 1 a shows a kind of cover plate 4 and only covers the encapsulating structure of chip 2, now cover plate 4 is box-shaped, Fig. 1 b and Fig. 1 c show respectively the encapsulating structure that cover plate 4 had not only covered chip 2 but also covered the plastic packaging material 5 of coated lead-in wire 3, wherein, cover plate 4 in Fig. 1 b protrudes with respect to these cover plate 4 entirety corresponding to the part of chip 2, and the cover plate 4 in Fig. 1 c is recessed with respect to these cover plate 4 entirety corresponding to the part of chip 2.In Fig. 1 b and Fig. 1 c, cover plate 4 engages with chip 2 and plastic packaging material 5 by heat-conducting glue 6.
Wherein, Fig. 1 a and the shown encapsulating structure of Fig. 1 c can be saved the material of making cover plate 4, can also cut down finished cost.And the cover plate 4 of Fig. 1 c can be made up through Sheet Metal Forming Technology of flat board.
Wherein, heat-conducting glue 6 is except for bonding, the cavity of the microvoid also producing when filling up chip 2 and engage with cover plate 4 and the surface irregularity of chip 2 and cover plate 4, can reduce like this heat transfer contact thermal resistance, to make the heat producing to be directly delivered to the external world by cover plate 4 in the time that chip 2 is worked.If adopt the structure shown in Fig. 1 b or Fig. 1 c, the heat at chip 2 edges can be delivered to the external world by cover plate 4 again by plastic packaging material 5.
Wherein, the material of cover plate 4 can be metal or alloy or pottery, for example, can be copper or aluminium.And cover plate 4 can be 0.3mm to 1mm corresponding to the thickness (being namely positioned at the thickness of the cover plate on chip 2 tops) of chip 2 parts, too thin heat dispersion is not good, and too thick volume is too large, and weight also can be too heavy.
Correspondingly, the present invention also provides a kind of method for packing, first chip 2 is mounted on substrate 1, then connecting lead wire 3 between substrate 2 and chip 2, and this lead-in wire 3 is coated with plastic packaging material 5, cover chip 2 with cover plate 4 again and by heat-conducting glue 6, cover plate 4 engaged with chip 2, if cover plate 4 also covers the plastic packaging material 5 of coated lead-in wire 3, can engage with plastic packaging material 5 by heat-conducting glue 6.
In addition, in order further to improve heat dispersion, when packaging body is connected on pcb board (printed circuit board (PCB)), the heat abstractor being arranged on plastic packaging material or chip can also be arranged on to (not shown) on cover plate 4 in conventional method, as fin, further to improve heat dispersion.
Fig. 2 is the flow chart of method for packing provided by the invention, as shown in Figure 2, first chip 2 is mounted on substrate 1, then 3 chip 2 is electrically connected with substrate 1 by going between, and 3 bondings operations go between.To be placed into substrate 1 for the template of filling plastic packaging material 5, so that fill plastic packaging material 5, then carry out plastic packaging material 5 fillings and plastic packaging material 5 and solidify, wherein, the curing mode of plastic packaging material 5 is to take the mode of heating, makes plastic packaging material 5 that curing reaction occur.After plastic packaging material 5 solidifies, template is removed, carry out again heat-conducting glue 6 and apply, if adopt the encapsulating structure of Fig. 1 a, coated with thermally conductive glue 6 on chip 2 only, if adopt the encapsulating structure of Fig. 1 b and Fig. 1 c, which kind of encapsulating structure no matter equal coated with thermally conductive glue 6 on the plastic packaging material 5 of chip 2 and coated lead-in wire 3, in addition, take, all can be on cover plate 4 coated with thermally conductive glue 6, wherein the painting method of heat-conducting glue 6 can adopt dotting glue method to apply.After heat-conducting glue 6 has applied, can carry out cover plate 4 and be placed with, can use placement equipment well known to those skilled in the art to carry out being placed with of cover plate 4 here.Finally, carry out the curing operation of heat-conducting glue 6, solidifying of heat-conducting glue 6 can be taked the curing mode heating in conveying type heating furnace or box type heater well known to those skilled in the art.
After the flow process providing at Fig. 2, can carry out the conventional subsequent step such as ball, cutting of planting.
It should be noted that, the detail of method for packing provided by the invention and benefit are corresponding with encapsulating structure provided by the invention, and in this, it will not go into details.
Below describe by reference to the accompanying drawings the preferred embodiment of the present invention in detail; but; the present invention is not limited to the detail in above-mentioned execution mode; within the scope of technical conceive of the present invention; can carry out multiple simple variant to technical scheme of the present invention, these simple variant all belong to protection scope of the present invention.
Technology provided by the invention goes for need to be by moulding technology to the encapsulating structure going between and bonding is protected; for example, FBGA(thin space ball grid array), QFN(quad flat non-pin package), QFP(square Flat type packaged) etc. the packing forms of substrate or lead frame.In addition, the present invention is by engaging the chip upper surface the exposing cover plate higher with conductive coefficient, the heat producing while making chip operation is delivered to the external world by cover plate effectively, thereby improve the reliability of chip, and cover plate ratio is easier to realize and recycles, thereby compared with conventional art, the present invention has certain environment protection significance.
It should be noted that in addition each the concrete technical characterictic described in above-mentioned embodiment, in reconcilable situation, can combine by any suitable mode.For fear of unnecessary repetition, the present invention is to the explanation no longer separately of various possible compound modes.
In addition, also can carry out combination in any between various execution mode of the present invention, as long as it is without prejudice to thought of the present invention, it should be considered as content disclosed in this invention equally.
Claims (10)
1. an encapsulating structure, is characterized in that, this structure comprises:
Substrate;
Chip, is mounted on described substrate;
Lead-in wire, be connected between described substrate and chip, and this lead-in wire is coated with plastic packaging material; And
Cover plate, covers described chip and by heat-conducting glue and described chip join.
2. encapsulating structure according to claim 1, is characterized in that, described cover plate also covers the plastic packaging material of coated described lead-in wire, and engages with this plastic packaging material by heat-conducting glue.
3. encapsulating structure according to claim 2, is characterized in that, described cover plate protrudes with respect to this cover plate entirety corresponding to the part of described chip or be recessed.
4. encapsulating structure according to claim 1, is characterized in that, the material of described cover plate is metal or alloy or pottery.
5. encapsulating structure according to claim 4, is characterized in that, the material of described cover plate is copper or aluminium.
6. encapsulating structure according to claim 1 and 2, is characterized in that, described cover plate is 0.3mm to 1mm corresponding to the thickness of the part of described chip.
7. a method for packing, is characterized in that, the method comprises:
By chip attachment on substrate;
Connecting lead wire between described substrate and chip, and this lead-in wire is coated with plastic packaging material; And
Cover plate is covered on described chip and by heat-conducting glue and described chip join.
8. method for packing according to claim 7, is characterized in that, described cover plate also covers the plastic packaging material of coated described lead-in wire, and engages with this plastic packaging material by heat-conducting glue.
9. method for packing according to claim 7, is characterized in that, described cover plate protrudes with respect to this cover plate entirety corresponding to the part of described chip or be recessed.
10. method for packing according to claim 7, is characterized in that, described heat-conducting glue adopts dotting glue method to apply.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810388309.0A CN108615711A (en) | 2014-01-24 | 2014-01-24 | A kind of encapsulating structure and packaging method based on template |
| CN201410033771.0A CN103794575A (en) | 2014-01-24 | 2014-01-24 | Encapsulation structure and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410033771.0A CN103794575A (en) | 2014-01-24 | 2014-01-24 | Encapsulation structure and method |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810388309.0A Division CN108615711A (en) | 2014-01-24 | 2014-01-24 | A kind of encapsulating structure and packaging method based on template |
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| Publication Number | Publication Date |
|---|---|
| CN103794575A true CN103794575A (en) | 2014-05-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810388309.0A Pending CN108615711A (en) | 2014-01-24 | 2014-01-24 | A kind of encapsulating structure and packaging method based on template |
| CN201410033771.0A Pending CN103794575A (en) | 2014-01-24 | 2014-01-24 | Encapsulation structure and method |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201810388309.0A Pending CN108615711A (en) | 2014-01-24 | 2014-01-24 | A kind of encapsulating structure and packaging method based on template |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1187037A (en) * | 1996-12-30 | 1998-07-08 | Lg半导体株式会社 | Semiconductor package and method for fabricating same |
| CN1577815A (en) * | 2003-06-28 | 2005-02-09 | 三星电机株式会社 | High-density chip scale package and method of manufacturing the same |
| CN101101881A (en) * | 2006-07-03 | 2008-01-09 | 矽品精密工业股份有限公司 | Heat dissipation type package structure and manufacturing method thereof |
| CN101375389A (en) * | 2006-12-21 | 2009-02-25 | 艾格瑞系统有限公司 | High Thermal Performance Packaging for Circuit Dies |
| CN102362347A (en) * | 2009-01-20 | 2012-02-22 | 阿尔特拉公司 | IC package with capacitors disposed on an interposal layer |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2154713B1 (en) * | 2008-08-11 | 2013-01-02 | Sensirion AG | Method for manufacturing a sensor device with a stress relief layer |
-
2014
- 2014-01-24 CN CN201810388309.0A patent/CN108615711A/en active Pending
- 2014-01-24 CN CN201410033771.0A patent/CN103794575A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1187037A (en) * | 1996-12-30 | 1998-07-08 | Lg半导体株式会社 | Semiconductor package and method for fabricating same |
| CN1577815A (en) * | 2003-06-28 | 2005-02-09 | 三星电机株式会社 | High-density chip scale package and method of manufacturing the same |
| CN101101881A (en) * | 2006-07-03 | 2008-01-09 | 矽品精密工业股份有限公司 | Heat dissipation type package structure and manufacturing method thereof |
| CN101375389A (en) * | 2006-12-21 | 2009-02-25 | 艾格瑞系统有限公司 | High Thermal Performance Packaging for Circuit Dies |
| CN102362347A (en) * | 2009-01-20 | 2012-02-22 | 阿尔特拉公司 | IC package with capacitors disposed on an interposal layer |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108615711A (en) | 2018-10-02 |
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Application publication date: 20140514 |
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