CN103794551B - Method for defining connecting hole by adopting electron beam process - Google Patents

Abstract

The invention discloses a method for defining a connection hole of a semiconductor device using an electron beam process, comprising: forming a basic structure of the device on a substrate, including an underlying structure that needs to be electrically connected to the connection hole; forming a first rigid structure on the basic structure. Mask layer; using an electron beam exposure process to form a negative photoresist pattern on the first hard mask layer to define a connection area; use the photoresist pattern as a mask to etch the first hard mask layer, forming a first hard mask pattern; forming a second hard mask layer on the first hard mask pattern; removing the first hard mask pattern, leaving the second hard mask layer to form a second hard mask pattern, exposing The connection area is formed; using the second hard mask pattern as a mask, etch to form a connection hole in contact with the underlying structure. According to the method of the present invention, the micro-nano level connecting hole pattern is successfully defined by using the electron beam process of the negative glue through patterning the hard mask twice successively. Improved efficiency and safety.

Description

The Method of Defining Connection Hole Using Electron Beam Technology

technical field

The invention relates to a manufacturing method of a semiconductor device, in particular to a method for defining a connection hole of a semiconductor device by using an electron beam process.

Background technique

The continuous shrinking of the critical dimension (CD) is the development trend of the very large scale integration (VLSI) industry. In the CD shrinking process, the photolithography process (Litho) is increasingly challenged. Electron beam (eBeam), as a nanoscale lithography process, has become one of the research hotspots in the international semiconductor field in recent years.

For the eBeam process, one of the main problems is that the process time is too slow because it needs to scan the e-beam photoresist to be patterned line by line. Therefore, during the process, the fewer areas that need to be written by the electron beam, the better. On the other hand, in the VLSI manufacturing process, the area of the contact hole (Contact) is relatively small, that is, the area where the photoresist is removed is relatively small. The photoresist in the semiconductor lithography process has two materials: positive resist and negative resist. The exposed area of the positive resist is removed after development, while the exposed area of the negative resist is retained after development. If eBeam is used to define the contact area, the exposed area of the positive film is much smaller than that of the negative film. In order to reduce the writing area of eBeam, the positive glue process should be adopted according to the above logical reasoning.

At present, for the eBeam process, negative glue is generally used. Because eBeam’s positive photodeveloper is usually a mixed liquid of methyl isobutyl ketone (MIBK) + isopropanol (IPA), and MIBK is a toxic substance, it will be dangerous if inhaled, which is not conducive to process safety.

Therefore, eBeam encountered inevitable contradictions when defining Contact graphics: using negative glue, the area that needs to be written by eBeam is greatly increased; using positive glue, there are safety problems.

Contents of the invention

From the above, the purpose of the present invention is to overcome the above technical difficulties and propose a new method for defining connection holes of semiconductor devices by electron beam technology, which can efficiently and safely form connection hole mask patterns.

To this end, the present invention provides a method for defining a connection hole of a semiconductor device using an electron beam process, comprising: forming the basic structure of the device on the substrate, including the underlying structure that needs to be electrically connected to the connection hole; The first hard mask layer; using an electron beam exposure process, forming a negative photoresist pattern on the first hard mask layer to define a connection area; using the photoresist pattern as a mask, etching the first hard mask A mold layer, forming a first hard mask pattern; forming a second hard mask layer on the first hard mask pattern; removing the first hard mask pattern, leaving the second hard mask layer to form a second hard mask pattern, exposing the connection area; using the second hard mask pattern as a mask, etch to form a connection hole in contact with the underlying structure.

Wherein, the underlying structure includes the source and drain regions and gate stacks of MOSFETs, the damascene structure in the multilayer wiring, and the pads in the passivation layer on the surface of the substrate.

Wherein, the material of the first hard mask layer is different from that of the second hard mask layer. Wherein, the first hard mask layer and/or the second hard mask layer are selected from polysilicon, amorphous silicon, microcrystalline silicon, amorphous carbon, amorphous germanium, SiC, SiGe, silicon nitride, silicon oxide, and combinations thereof .

Wherein, a plasma dry etching process is used to etch the first hard mask layer to form a first hard mask pattern.

Wherein, after forming the second hard mask layer, planarizing the second hard mask layer by CMP process until the first hard mask pattern is exposed.

Wherein, a wet etching process is used to remove the first hard mask pattern.

Among them, the negative glue includes COP, epoxy Exopy618, SAL601, AR-N-7520.

According to the method of the present invention for defining connection holes of semiconductor devices by using electron beam technology, by patterning the hard mask twice successively, the electron beam technology of negative glue is used to successfully define the micro-nano level connection hole pattern, which improves the efficiency and safety sex.

Description of drawings

Describe technical scheme of the present invention in detail below with reference to accompanying drawing, wherein:

1 to 8 are cross-sectional views of each step of a method for defining a connection hole of a semiconductor device using an electron beam process according to the present invention; and

FIG. 9 is a schematic flowchart of a method for defining a connection hole of a semiconductor device using an electron beam process according to the present invention.

Detailed ways

The features and technical effects of the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and in combination with schematic embodiments, and a method for efficiently and safely defining connection holes of semiconductor devices by electron beam technology is disclosed. It should be pointed out that similar reference numerals represent similar structures, and the terms "first", "second", "upper", "lower" and the like used in this application can be used to modify various device structures or manufacturing processes . These modifications do not imply spatial, sequential or hierarchical relationships of the modified device structures or fabrication processes unless specifically stated.

Referring to FIG. 9 and FIG. 1 , the basic structure of the device is formed on the substrate, wherein the basic structure of the device includes the underlying structure that needs to be electrically connected to the connection hole. Taking the structure of the gate dielectric layer of high-k material and the gate conductive layer of metal material in the gate-last process as an example, the gate oxide layer 2 is first grown on the substrate 1 made of bulk Si by thermal oxidation, and then the gate oxide layer 2 is grown on the gate oxide layer. A dummy gate (not shown) made of amorphous silicon is deposited on layer 2 and photolithography/etching forms a dummy gate stack. Source and drain doping is performed using the dummy gate stack as a mask to form source and drain regions 3 in the substrate, and gate spacers 4 are formed around the dummy gate stack structure. The gate sidewall 4 can be a multi-layer structure, including a vertical sidewall 4A of silicon nitride, an "L" shaped sidewall 4B of silicon oxide, and a stress side made of silicon nitride or diamond-like amorphous carbon (DLC). Wall 4C. An interlayer dielectric layer (ILD) 5 is deposited on the substrate 1 around the gate spacer 4, and its material may be silicon oxide, silicon nitride or other low-k materials. Low-k materials include but are not limited to organic low-k materials ( Such as organic polymers containing aryl or polycyclic rings), inorganic low-k materials (such as amorphous carbon-nitrogen films, polycrystalline boron-nitride films, fluorosilicate glass, BSG, PSG, BPSG), porous low-k materials (such as disilicon Trioxane (SSQ)-based porous low-k materials, porous silica, porous SiOCH, C-doped silica, F-doped porous amorphous carbon, porous diamond, porous organic polymer). Use fluorocarbon-based plasma dry etching or TMAH wet etching to remove the dummy gate made of amorphous silicon, leave a gate trench (not shown) in the ILD 5, and deposit in the gate trench A gate dielectric layer 6 of a high-k material, a gate work function adjustment layer 7 , and a gate resistance adjustment layer 8 . Among them, high-k materials include but are not limited to nitrides (such as SiN, AlN, TiN), metal oxides (mainly subgroup and lanthanide metal element oxides, such as Al ₂ O ₃ , Ta ₂ O ₅ , TiO ₂ , ZnO , ZrO ₂ , HfO ₂ , CeO ₂ , Y ₂ O ₃ , La ₂ O ₃ ), perovskite phase oxides (such as PbZr _x Ti1- _x O ₃ (PZT), Ba _x Sr1- _x TiO ₃ (BST) ), the gate work function adjustment layer 7 includes TiN, TaN, TiAl, and the gate resistance adjustment layer 8 includes W, Ti, Ta, Mo, Cu, Al and combinations thereof. Each layer is planarized by CMP process until the ILD 5 is exposed. The basic structure of HK/MG in the MOSFET is described above, wherein the underlying structures that need to be electrically connected to the connection holes are the source and drain regions 3 and the gate resistance adjustment layer 8 . But the connection hole process of the present invention is not limited thereto, and can also be applied to any other applications that require interconnection, such as a damascene structure in multilayer wiring (Damascene structure, through holes and wiring stacked interlaced), substrate surface passivation layer pad connections in the etc.

Referring to FIG. 9 and FIG. 2 , a first hard mask layer 9 is deposited and formed on the entire device, covering the ILD 5 , sidewalls 4 ( 4C, 4B, 4A) and gate stack structures 6 / 7 / 8 . Deposition methods include LPCVD, PECVD, HDPCVD, MOCVD, MBE, ALD, etc. The material of the first hard mask layer 9 can be polysilicon, amorphous silicon, microcrystalline silicon, amorphous carbon, amorphous germanium, SiC, SiGe, nitrogen silicon oxide, silicon oxide, and combinations thereof. Preferably, the material of the first hard mask layer 9 is different from that of the adjacent ILD 5 , sidewall 4 , and gate stack structure, so as to improve the etching selectivity.

Referring to FIG. 9 and FIG. 3 , a photoresist mask pattern 10P forming a negative resist is defined on the first hard mask layer 9 by using an electron beam process of negative resist. Spin-coat negative glue 10 on the first hard mask layer 9 earlier, such as epoxy-based negative glue, such as COP (copolymer of glycidyl methacrylate-ethyl acrylate), epoxy Exopy618 (a kind of containing two Bisphenol A epoxy resin with epoxy groups), SAL601, AR-N-7520 (available for example from Beijing Huidexin Technology Co., Ltd.) and the like. Electron beam exposure systems (such as improved SEM, Gaussian scanning system, shaped beam system, limited scattering angle projection electron beam exposure system, etc.) Electron beam scanning exposure, cationic initiator decomposes under electron beam irradiation, produces protonic acid, promotes cationization of epoxy group molecules, epoxy ring opens to initiate polymerization reaction, and finally cross-links to form an insoluble developer such as isopropanol. The gel constitutes the photoresist mask pattern 10P. In this process, due to the use of negative photoresist, the electron beam exposure system only needs to scan the area where 10P is located, which saves a lot of working time and improves efficiency. And because the developing solution of the negative film contains less or less toxic substances, the operation safety is improved.

Referring to FIG. 9 and FIG. 4 , using the photoresist mask pattern 10P as a mask, the first hard mask layer 9 is etched to stop on the ILD 5 to form a first hard mask pattern 9P. The etching method may be plasma dry etching, such as reactive ion etching (RIE) using fluorocarbon-based etching gas.

Referring to FIGS. 9 and 5 , the second hard mask layer 11 is deposited and formed on the first hard mask pattern 9P and the ILD 5 . The second hard mask layer 11 is deposited by LPCVD, PECVD, HDPCVD, etc. The material of layer 11 can also be selected from polysilicon, amorphous silicon, microcrystalline silicon, amorphous carbon, amorphous germanium, SiC, SiGe, nitride Silicon, silicon oxide and combinations thereof, but the material is different from the first hard mask layer 9 in order to provide a higher etching selectivity. In one embodiment of the present invention, the first hard mask layer 9 is polysilicon or amorphous silicon, and the second hard mask layer 11 is silicon oxide. In other embodiments, the first hard mask layer 9 can also be amorphous carbon, amorphous germanium, SiC, SiGe, and the second hard mask layer 11 can be silicon nitride. In yet another embodiment, layer 9 is silicon nitride and layer 11 is silicon oxide, polysilicon, amorphous silicon.

Referring to FIG. 9 and FIG. 6 , the second hard mask layer 11 is planarized until the first hard mask pattern 9P is exposed by etching back or CMP. At this time, the remaining second hard mask layer 11 constitutes a second hard mask pattern 11P complementary to the first hard mask pattern 9P.

Referring to FIGS. 9 and 7 , the first hard mask pattern 9P is etched away, leaving the connection hole opening 11H surrounded by the second hard mask pattern 11P. When the layer 9 is made of polysilicon, amorphous silicon, microcrystalline silicon and other silicon-based materials and the layer 11 is not made of silicon-based materials, the first hard mask pattern 9P can be removed by a wet etching process such as TMAH. When layer 9 is made of amorphous carbon, it can be removed by dry etching with oxygen plasma. When layer 9 is made of amorphous germanium, SiC, SiGe, etc., fluorine-based plasma dry etching can be used (reasonable adjustment of the ratio is required to reduce the etching of layer 11). When layer 9 is made of silicon oxide (layer 11 is not made of silicon oxide), it can be removed by using an HF-based wet etching process.

Referring to FIG. 9 and FIG. 8 , the ILD 5 is etched using a dry etching process until the underlying structure (source-drain region 3 and gate stack structure) requiring electrical interconnection is exposed to form a connection hole 5H. Subsequently, a metal/metal nitride may be further deposited in the connection hole 5H to form a contact plug (not shown).

According to the method of the present invention for defining connection holes of semiconductor devices by using electron beam technology, by patterning the hard mask twice successively, the electron beam technology of negative glue is used to successfully define the micro-nano level connection hole pattern, which improves the efficiency and safety sex.

While the invention has been described with reference to one or more exemplary embodiments, those skilled in the art will recognize various suitable changes and equivalents in device structures that do not depart from the scope of the invention. In addition, many modifications, possibly suited to a particular situation or material, may be made from the disclosed teaching without departing from the scope of the invention. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode for carrying out this invention, but that the disclosed device structures and methods of making the same will include all embodiments falling within the scope of the invention .

Claims (8)

1. A method for defining connection holes using an electron beam process, comprising: Form the basic structure of the device on the substrate, including the underlying structure that needs to be electrically connected to the connection hole; forming a first hard mask layer on the base structure; Using the electron beam exposure process, a negative photoresist pattern is formed on the first hard mask layer, and only the area that needs to be electrically interconnected is subjected to electron beam scanning exposure to save working time, improve efficiency and improve operational safety. Define the connection area; Using the photoresist pattern as a mask, etching the first hard mask layer to form a first hard mask pattern; forming a second hard mask layer on the first hard mask pattern; removing the first hard mask pattern, leaving a second hard mask layer to form a second hard mask pattern, exposing the connection region; Using the second hard mask pattern as a mask, etch to form a connection hole in contact with the underlying structure. 2. The method of claim 1, wherein the underlying structures include MOSFET source-drain regions and gate stacks, damascene structures in multilayer wiring, and solder pads in the passivation layer on the substrate surface. 3. The method of claim 1, wherein the first hard mask layer and the second hard mask layer are made of different materials. 4. The method according to claim 3, wherein the first hard mask layer and/or the second hard mask layer are selected from polysilicon, amorphous silicon, microcrystalline silicon, amorphous carbon, amorphous germanium, SiC, SiGe, Silicon nitride, silicon oxide, and combinations thereof. 5. The method of claim 1, wherein the first hard mask layer is etched using a plasma dry etching process to form the first hard mask pattern. 6. The method of claim 1, wherein after forming the second hard mask layer, further comprising planarizing the second hard mask layer using a CMP process until the first hard mask pattern is exposed. 7. The method of claim 1, wherein the first hard mask pattern is removed using a wet etching process. 8. The method of claim 1, wherein the negative resist comprises COP, epoxy Exopy618, SAL601, AR-N-7520.