CN103780270B - The physical layer receiver of mobile industry processor interface - Google Patents

Abstract

The invention provides a physical layer receiver of a mobile industry processor interface. The receiver provided by the invention includes a control module, a data receiving circuit and a shielding circuit. The control module generates an enabling signal according to a set of differential signals provided by a transmitter. After being driven by the enabling signal, the data receiving circuit starts to generate an output signal according to the set of differential signals, and the masking circuit starts to mask the output signal. After the enabling signal is generated, the control module starts to provide a bias voltage to the group of differential signals, so that the output signal has a first state. The transmitter adjusts the set of differential signals so that the output signal enters the second state from the first state. After detecting that the output signal enters the second state, the control module stops providing bias voltage and generates a disabling signal, so that the shielding circuit stops shielding the output signal.

Description

PHY Receiver for Mobile Industry Processor Interface

technical field

The present invention is related to data transmission technology, especially to receivers in the physical layer (D-PHY) of the mobile industry processor interface (MIPI).

Background technique

Mobile Industry Processor Interface (MIPI) is a communication software/hardware interface standard that has been developing rapidly in recent years, and is mainly used in mobile electronic devices, digital cameras, monitors, tablet computers and notebook computers. The physical layer serial interface commonly known as D-PHY in the MIPI protocol provides a high-speed serial interface solution required for communication between various components in an electronic device. The D-PHY solution can expand the bandwidth of the transmission interface with low power consumption.

For data transmission, the MIPID-PHY standard defines two states: a high-speed (HS) state and a low-power (LP) state. In practice, the high-speed data receiving circuit and the low-power data receiving circuit of the MIPID-PHY receiving end share the same set of differential transmission lines to receive messages from the MIPI transmitting end. Figure 1 is a timing diagram of the signal in the group of differential transmission lines transitioning from a low power state to a high speed state; DP represents the positive end of the differential transmission line, and DN represents the negative end of the differential transmission line. In a low power state (eg period T0), both the DP signal and the DN signal have a high level (1.2 volts). When the MIPI transmitter wants to leave the low-power state and enter the high-speed state to start transmitting data to the receiver, there will be a period of time (T1) to first lower the DP signal to a low level, and then a period of time (T2) to turn the DN signal Also tuned down to low level. In the time period T3, the transmitting end must send a high-speed differential signal 0 through the set of differential transmission lines, that is, make the DN signal 200 mV higher than the DP signal. During the period T4, the transmitting end sends out a synchronization signal for reference by the receiving end. After the time period T4 ends, the transmitting end starts to transmit real data content.

According to the regulations of MIPID-PHY, the receiving end must enter the high-speed receiving mode during the time period T2, that is, make its high-speed data receiving circuit start to operate. For the high-speed data receiving circuit, the equipotential DP/DN signal within the time period T2 is an unrecognizable invalid signal, and the MIPI standard also stipulates that the receiving end must ignore and block the data received during the time period T2. Period T3 can be regarded as a buffer during this masking period; more specifically, the receiving end must at least shield the received data in the entire period T2, and the shielding range can cover part or all of the period T3, but at most it cannot include the period Synchronization signal in T4.

The lower limit of the aforementioned masking period is 85ns+6*UI, and the upper limit is 145ns+10*UI, where ns represents nanoseconds, and UI represents the period of the clock signal used in the high-speed state. In practical applications, the frequency of the clock signal will vary with different settings, and the range of UI is between 1 nanosecond and 12.5 nanoseconds. To correctly determine the length of the masking period, the MIPI receiver must know the value of the UI. Most of the current practice is to use software to perform handshaking between the transmitting end and the receiving end to transmit UI information. The disadvantage of this approach is that it consumes a considerable amount of software resources, and it cannot cope with unexpected conditions that do not conform to the MIPID-PHY specification (eg, the UI length used by the transmitter exceeds 12.5 ns).

Contents of the invention

In order to solve the above problems, the present invention proposes a new MIPID-PHY receiver, which uses the voltage characteristics of the DP/DN signal itself between state transitions to determine when to start and end the shielding period, without the need to detect or report to the transmitting end Query the period of the clock signal, so the trouble of using software to exchange signals can be saved, and it can also deal with the unexpected situation that the signal frequency used by the transmitting end does not comply with the MIPID-PHY specification.

A specific embodiment according to the present invention is a receiver, which includes a control module, a data receiving circuit and a shielding circuit. The control module is used for generating an enable signal according to a set of differential signals provided by a transmitter. After being driven by the enabling signal, the data receiving circuit starts to generate an output signal according to the set of differential signals. After being driven by the enabling signal, the masking circuit starts to mask the output signal. After the enable signal is generated, the control module starts to provide a bias voltage to the group of differential signals, so that the output signal has a first state. The transmitter adjusts the set of differential signals to make the output signal enter a second state from the first state. After detecting that the output signal enters the second state, the control module stops providing the bias voltage and generates a disabling signal to make the shielding circuit stop shielding the output signal.

The advantages and spirit of the present invention can be further understood through the following detailed description of the invention and the accompanying drawings.

Description of drawings

FIG. 1 is a timing diagram of MIPI differential signal transition from a low-power state to a high-speed state.

FIG. 2 is a block diagram of a receiver according to an embodiment of the invention.

FIG. 3 is a block diagram of a receiver according to another embodiment of the invention.

Explanation of main component symbols

DP: Positive terminal of differential signal DN: Negative terminal of differential signal

200: MIPI receiver 21: Low-speed data receiving circuit

22: High-speed data receiving circuit 23: Shielding circuit

24: Bias circuit 25: High-speed data detection circuit

26: Control module

Detailed ways

A specific embodiment according to the present invention is a mobile industry processor interface (mobileindustryprocessorinterface, MIPI) D-PHY receiver 200 shown in FIG. Pressure circuit 24 and high-speed data detection circuit 25. Practically, the receiver 200 can be integrated in various electronic devices (such as smart phones, personal digital assistants, notebook computers, game consoles or tablet computers), and can also exist independently.

As shown in FIG. 2, the differential signals DP/DN are supplied to the low-speed data receiving circuit 21 and the high-speed data receiving circuit 22, respectively. The low-speed data receiving circuit 21 determines a time point for generating an enable signal EN according to the DP signal and/or the DN signal. The enable signal EN is used to instruct the high-speed data receiving circuit 22 to start operating, and instructs the masking circuit 23 to start masking the output signal R generated by the high-speed data receiving circuit 22 . During masking, the masking circuit 23 can fix its output signal V to a certain voltage that is not affected by the signal R.

Please refer to the timing diagram in Figure 1. For example, the low-speed data receiving circuit 21 can generate the enable signal EN when detecting a falling edge of the DP signal (that is, the beginning of the period T1) or a falling edge of the DN signal (that is, the end of the period T1). . Alternatively, the low-speed data receiving circuit 21 can be designed to generate the enable signal EN when detecting a voltage difference between the DP signal and the DN signal that is higher than a threshold value.

In addition to the high-speed data receiving circuit 22 and the shielding circuit 23 , the enable signal EN is also provided to the bias circuit 24 . The enable signal EN instructs the bias circuit 24 to start to provide a bias voltage to the DP signal line in the high speed data receiving circuit 22 . For example, the magnitude of the bias voltage can be 50 mV or 100 mV (that is, the voltage on the DP signal line is increased by 50 mV or 100 mV), but it is not limited thereto. As mentioned above, both the DP signal and the DN signal provided by the transmitting end during the period T2 are at low level. The function of this bias voltage is to make the DP signal higher than the DN signal, so that the high-speed data detection circuit 25 responsible for detecting the output signal R of the high-speed data receiving circuit 22 will detect that the output signal R is fixed equal to logic “1” in the period T2.

As mentioned earlier, in the time period T3, the transmitter makes the DN signal 200 mV higher than the DP signal. Therefore, after entering the period T3, even if the bias voltage exists, the DN signal will still be higher than the DP signal, so that the high-speed data detection circuit 25 detects that the output signal R changes from logic "1" to logic "0". After this transition occurs, the high-speed data detection circuit 25 generates a disable signal D, which is provided to the shielding circuit 23 and the bias circuit 24 respectively. The disable signal D is used to instruct the shielding circuit 23 to stop shielding the output signal R, and to make the bias circuit 24 stop providing the bias voltage to the high-speed data receiving circuit 22 . Please note that the operation range of the disable signal D is not opposite to that of the aforementioned enable signal EN.

After the disable signal D appears, the output signal R of the high-speed data receiving circuit 22 returns to the state not affected by the bias voltage, and the shielding circuit 23 can directly use the output signal R as the output signal V to provide to subsequent circuits.

In practice, the upper limit of the bias voltage can be determined according to the voltage amplitude of the DP/DN signal in the high-speed state. To be more specific, the bias voltage cannot make the judgment result of the high-speed data detection circuit 25 change from logic “1” to logic “0” after the transmitter adds 200 millivolts to the DN signal. On the other hand, the lower limit of the bias voltage is such that after the bias voltage circuit 24 adds the bias voltage to the DP signal, the judgment result of the high-speed data detection circuit 25 is logic "1".

In this embodiment, the start time of the mask period is determined by the low-speed data receiving circuit 21 , and the end time of the mask period is determined by the high-speed data detection circuit 25 . Obviously, the above method can effectively shield the output signal R in the period T2 and stop shielding the output signal R before the period T4 begins. In one embodiment, the low-speed data receiving circuit 21 is designed to generate the enable signal EN when the DN signal falls, and the high-speed data detection circuit 25 is designed to detect that the output signal R changes from logic "1" to logic When "0", the disable signal D is sent immediately. In this way, the operating time of the bias circuit 24 can be shortened as much as possible to save its power consumption.

It should be noted that the above bias voltage does not have to be directly provided to the DP signal line, for example, it can also be provided to some circuit nodes in the high-speed data receiving circuit 22 . As long as the bias voltage can cause the output signal R of the high-speed data receiving circuit 22 to be logic "1" in the period T2 and change to logic "0" in the period T3 after being affected by the transmitter, the aforementioned effect can be achieved.

As shown in FIG. 3 , in another embodiment, the functions of the aforementioned low-speed data receiving circuit 21 , bias voltage circuit 24 and high-speed data detecting circuit 25 can be integrated into a control module 26 . Those with ordinary knowledge in the technical field of the present invention can understand that the work of generating the enable signal EN according to the DP/DN signal can also be performed by other detection circuits, and does not necessarily need to be realized by the low-speed data receiving circuit in the MIPI receiver.

It can be seen from the above description that the MIPI receiver 200 uses the voltage characteristics of the DP/DN signal itself between state transitions to determine when to start and end the masking period, and does not need to detect or query the transmitting end for the period of the clock signal ( That is, the numerical value of the UI), so the trouble of using software for signal exchange can be saved, and it can also deal with the unexpected situation that the signal frequency adopted by the transmitting end does not comply with the MIPI specification.

Through the above detailed description of the preferred embodiments, it is hoped that the features and spirit of the present invention can be described more clearly, rather than limiting the scope of the present invention by the preferred embodiments disclosed above. On the contrary, the intention is to cover various changes and equivalent arrangements within the scope of the claimed patent scope of the present invention.

Claims (4)

1. a receiver, for one group of differential wave that reception one conveyer provides, this receiver comprises:

One control module, when a default change appears in this group differential wave, this control module produces an enable signal and provides a bias voltage;

One data receiver circuit, starts according to this group differential wave and this bias voltage to produce an output signal after driving by this enable signal; And

One screened circuit, starts to shield this after driving output signal by this enable signal;

Wherein when this control module starts to provide this bias voltage, this output signal is in one first state; Detect this output signal because of by this conveyer affects after this first state enters one second state, this control module stop this bias voltage is provided and produces a disable signal to this screened circuit, make this screened circuit stop shielding this output signal.

2. receiver as claimed in claim 1, it is characterized in that, this group differential wave comprises positive end signal and a negative terminal signal, and this bias voltage is provided to this positive end signal by this control module.

3. receiver as claimed in claim 1, it is characterized in that, this bias voltage is provided to this data receiver circuit by this control module.

4. receiver as claimed in claim 1, it is characterized in that, this data receiver circuit is a high-speed data equalization circuitry, and this control module comprises:

One low speed data receiving circuit, in order to produce this enable signal according to this group differential wave;

One bias circuit, starts to provide this bias voltage after driving by this enable signal; And

One testing circuit, in order to detect this output signal, and produces this disable signal after this output signal enters this second state.