CN103780258B - Digital double-line delay phase lock loop - Google Patents

Abstract

The invention discloses a digital double-chain delay phase-locked loop. The digital double-chain delay phase-locked loop includes a delay unit remainder chain, a phase detector, a locking control unit and two delay chains, wherein the two delay chains are composed of multiple A delay chain composed of three delay units and a compensation chain composed of multi-stage compensation delay units, the delay unit includes a coarse adjustment chain delay unit and a fine adjustment chain delay unit that are set upside down in an interleaved manner; the reference clock passes through the coarse adjustment chain delay unit and the fine adjustment chain successively The delay unit is input to the delay unit of the coarse adjustment chain, and the delay unit of the fine adjustment chain is output. At the same time, the reference clock passes through the multi-stage compensation delay unit of the compensation chain, and the phase detector compares the output clock of the compensation chain with the reference clock, and outputs the phase detection result , the output clock is adjusted by the locking control unit according to the phase detection result, if the output clock is ahead of the reference clock, the delay time is increased, the output clock is pushed back, and vice versa, until the phase detector identifies that the two clock signals are synchronous, the system locking.

Description

Digital Double Chain Delay Locked Loop

technical field

The invention relates to a DLL, in particular to a digital double-chain delay phase-locked loop.

Background technique

DLL is the abbreviation of Delay Lock Loop. The function of DLL is to adjust the phase of a clock signal, which is often used for clock synchronization of processor memory.

For a single-chain DLL, the reference clock is connected to the input terminals of all delay units at the same time, and the phase detector compares the phases of the reference clock and the feedback clock. If the feedback clock is faster than the reference clock, the shift register is controlled to shift to the left, and the delay time is increased. , until the reference clock and feedback clock are synchronized, and vice versa. The disadvantage is that the locking time is long and the accuracy is low.

For analog DLL, the phase detector compares the phase of the reference clock and the feedback clock, and generates a control signal according to the phase difference to control the current of the charge pump to charge or discharge the filter capacitor. The signal is filtered to generate a control voltage, and the phase of the feedback clock is changed by changing the voltage value to adjust the delay time of the voltage-controlled delay line. The disadvantage is high power consumption and slow speed.

In a high-speed, parallel chip-to-chip communication system, in order to achieve clock synchronization between channels and complete reliable data sampling, there is an urgent need for a high-speed quadrature clock generation system. And in order to meet the requirements of different communication protocols, it is necessary to provide support for different frequencies and an expandable application range of the quadrature clock generation system.

Contents of the invention

In order to solve the above-mentioned technical problems, the object of the present invention is to provide a digital double-chain delay-locked loop, which adopts a high-speed quadrature clock system to ensure the high-precision requirements of the quadrature clock, and can meet the requirements of high-speed and wide-range frequency locking. , voltage, temperature changes have strong adaptability and reliability.

Specifically, the present invention discloses a digital double-chain delay phase-locked loop, which includes a delay unit remainder chain, a phase detector, a locking control unit and two delay chains, wherein the two delay The chain includes a delay chain composed of a plurality of delay units and a compensation chain composed of multi-stage compensation delay units, and the delay units include a coarse-tuning chain delay unit and a fine-tuning chain delay unit arranged upside down;

The reference clock is input from the first delay unit of the delay chain, passes through the delay unit of the coarse adjustment chain and the delay unit of the fine adjustment chain, and then enters the next delay unit, the input of the delay unit of the coarse adjustment chain, the output of the delay unit of the fine adjustment chain, after the delay Choose to enter the phase detector or enter the phase detector through the remainder chain of the delay unit. At the same time, the reference clock passes through the multi-stage compensation delay unit of the compensation chain, and enters the phase detector after delay compensation. The phase detector outputs the clock from the compensation chain and the reference clock Make a comparison and output the phase detection result. According to the phase detection result, the output clock is adjusted by the locking control unit. If the output clock is ahead of the reference clock, the delay time is increased and the output clock is pushed back, and vice versa until the phase detector is identified. The two clock signals are synchronized and the system is locked.

Multiple delay units and multi-stage compensation delay units of the two delay chains are equidistantly set to obtain an ideal duty cycle.

The data lines respectively output by the coarse adjustment chain delay unit and the fine adjustment chain delay unit have a Bus structure.

Delay units in the remainder chain have the same structure as the coarse adjustment chain delay units.

The reference clock is a pair of differential clocks.

The metal traces for the differential clock signals are the same length.

The difference between the output clock and the reference clock is locked to within less than half a clock period.

A digital double-chain delay phase-locked method, comprising the steps of:

1) Set up two delay chains, including a delay chain composed of multiple delay units and a compensation chain composed of multi-stage compensation delay units;

2) The coarse-tuning chain delay unit and the fine-tuning chain delay unit of each delay unit are set upside down;

3) The reference clock is input from the first delay unit of the delay chain, passes through the delay unit of the coarse adjustment chain and the delay unit of the fine adjustment chain, and then enters the next delay unit, the input of the delay unit of the coarse adjustment chain, the output of the delay unit of the fine adjustment chain, After delay selection, it enters the phase detector or enters the phase detector through the remainder chain of the delay unit. At the same time, the reference clock passes through the multi-stage compensation delay unit of the compensation chain, and enters the phase detector after delay compensation. The phase detector combines the output clock of the compensation chain with the The reference clock is compared, and the phase detection result is output;

4) According to the phase detection result, the output clock is adjusted by the locking control unit. If the output clock is ahead of the reference clock, the delay time is increased and the output clock is pushed back, and vice versa until the phase detector identifies that the two clock signals are synchronous. System locked.

A processor or memory and a clock synchronization device using the above DDL.

Technical effect of the present invention:

It is mainly aimed at the routing of the differential clock CKN/CKP to keep the synchronization of the two signals. Even through different delay units, a better synchronization effect can still be obtained

Description of drawings

Fig. 1 block diagram of digital double-chain delay phase-locked loop of the present invention;

Fig. 2 is a single-chain circuit diagram of the coarse adjustment chain delay unit of the present invention;

Fig. 3 is a differential circuit diagram of the coarse adjustment chain delay unit of the present invention.

Among them, reference signs

1 is the locking control unit;

2 is a phase detector;

3 is delay selection;

4 is delay compensation;

5 is the delay unit remainder chain;

6 is a compensation delay unit;

7 is a coarse adjustment chain delay unit;

8 is a fine-tuning chain delay unit.

detailed description

The digital double-chain delay phase-locked loop DLL of the present invention, referring to Fig. 1, the main functional units include: compensation delay unit 6 (DelayLine), coarse adjustment chain delay unit 7 (Delaycell CT), fine adjustment chain delay unit 8 (Delaycell FT ), phase detector 2 (PhaseDetect), delay compensation 4, delay selection 3, delay unit remainder chain 5 and lock control unit 1 (LockControl).

The two delay chains include a delay chain composed of multiple delay units and a compensation chain composed of a multi-stage compensation delay unit 6. The delay unit adopts a double-chain structure, including a coarse adjustment chain delay unit 7 (Delaycell CT) and a fine adjustment chain delay unit 8 (Delaycell FT). The advantage of this double-chain structure is that it can reduce the locking time and reduce the static phase error. Lock time is a key parameter to evaluate a DLL design.

In order to realize quadrature clock generation, the design uses exactly the same 4 delay units, and the 4 delay units are controlled by the same coarse code and fine code, and the accuracy of coarse code and fine code is 4 times that of a single delay chain.

The reference clock CKP/CKN (a pair of differential clocks), CKP/CKN is input from the first delay unit Delaycell, and passes through the coarse adjustment chain delay unit 7 (Delaycell CT) and the fine adjustment chain delay unit 8 (Delaycell FT), and then Enter the next level of delay, the coarse adjustment chain delay unit 7 (Delaycell CT) enters, the fine adjustment chain delay unit 8 (Delaycell FT) exits, and the coarse adjustment chain delay unit 7 (Delaycell CT) can realize digital double chain delay in large steps The fast locking of the phase-locked loop DLL itself, after the digital double-chain delay phase-locked loop DLL is quickly locked, through the adjustment code fallback mechanism of the coarse adjustment chain delay unit 7 (Delaycell CT) and the fine adjustment chain delay unit 8 (Delaycell FT) Fine adjustment realizes the high-precision locking of the digital double-chain delay-locked loop DLL again, so as to meet the characteristics of wide-frequency fast locking and high precision. Referring to Figure 1, the coarse-tuning chain delay unit 7 (DelaycellCT) and the fine-tuning chain delay unit 8 (DelaycellFT) are alternately placed upside down. The first advantage of this setting is that CKP/CKN are output from the last stage of delay through the same path. The second advantage is that the differential clock directly enters the next stage of delay along the shortest path in the delay chain, and the third advantage is that it is beneficial to maintain the equidistant requirements between different stages.

In addition, the coarse-tuning chain delay unit 7 (Delaycell CT)/fine-tuning chain delay unit 8 (Delaycell FT) also respectively output 8-bit data lines, because the coarse-tuning chain delay unit 7 (Delaycell CT)/fine-tuning chain delay unit 8 (DelaycellFT) is placed upside down. Therefore, the data output is connected through the horizontal main data line placed between the cells. The wiring method is a Bus structure.

It is worth noting that this delay chain path strictly follows the equidistant principle between each stage, that is, the delay chains are placed equidistantly to obtain an ideal duty cycle. In order to ensure that the phase difference of each stage of the delay unit Delaycell is 90 degrees, the structure of the delay at each stage must be consistent, the routing must be uniform, and the differential signal path must be consistent.

At the same time, the reference clock CKP/CKN at the input end also passes through another compensation chain composed of a compensation delay unit 6 (DelayLine), and reaches the output end of the delay chain. This is to compensate for the influence of intrinsic delay (that is, the delay of the delay unit when both the coarse code and the fine code are 0) when used at high frequencies, a specially designed 4-stage compensation chain.

After CKP/CKN (differential clock) is output from the above two delay chains respectively, the reference clock CKP5/CKN5 enters the phase detector 2 after delay compensation 4, and the compared clock CKP4/CKN4 directly enters the phase detector 2 after delay selection 3, Or enter the phase detector 2 through the remainder chain 5 of the delay unit.

In this process, the trace length between a pair of differential signals needs to be highly consistent. For example, when the output signal of compensation delay unit 6 (DelayLine) is output to delay compensation 4, since CKP is closer to delay compensation 4 than CKN, Therefore, in the layout design, it is necessary to deliberately lengthen the traces of CKP to ensure the matching of the two differential lines.

In order to make the phase error more accurate, when the coarse adjustment is locked, a lock detection signal is set from low to high, and the fine adjustment process with higher precision begins until the system is finally locked, and the difference between the output clock and the reference clock is locked at less than Within the range of half a clock period, that is, the error between the output clock and the reference clock is smaller than the dead zone of the phase detector 2 .

In order to solve the phase locking of better frequency under the condition of ensuring the accuracy and locking speed, after the fine-tuning chain delay unit 8 (Delaycell FT), the delay unit remainder chain 5 structure is adopted. The delay unit in the remainder chain 5 of the delay unit adopts the same structure as the delay unit 7 (Delaycell CT) of the coarse adjustment chain.

After the coarse adjustment process, the delay cell remainder chain 5 realizes the delay adjustment of the 1st, 2nd, 3rd, and 4th grade coarse adjustment chain delay unit 7 (Delaycell CT) under the control of the remainder adjustment code. When the delay of the delay cell remainder chain 5 reaches When the 4-level coarse adjustment chain delay unit 7 (Delaycell CT) is used, the remainder chain 5 of the delay unit is cleared and carried at the same time, that is, one bit of coarse adjustment code CT is added, which ensures that a coarse adjustment chain delay unit 7 is used during the entire coarse adjustment process. The accuracy of (Delaycell CT) is continuously adjusted. When the coarse adjustment lock is reached, the delay of the delay cell remainder chain 5 is bypassed by using the delay selection 3, and the delay of the delay selection 3 itself is compensated during the phase detection of the clock.

In the next two units phase detector 2 (PD) and lock control unit 1 (LockControl), the differential signal remains symmetrical until the differential clock enters lock control unit 1 (LockControl).

After the reference clock passes through the 4-stage compensation delay unit 6 (Delayline), the phase detector 2 compares the output clock of the compensation delay unit 6 (Delayline) with the reference clock, and the lock control unit 1 (LockControl) adjusts the output clock according to the phase detection result , if the output clock is ahead of the reference clock, the delay time is increased and the output clock is pushed back, and vice versa, until the phase detector 2 verifies that the two signals are in sync and the system locks.

Fig. 2 is a single-chain circuit diagram of the coarse adjustment chain delay unit of the present invention; Fig. 3 is a differential circuit diagram of the coarse adjustment chain delay unit of the present invention.

In summary, a digital double-chain delay-locked loop, the digital double-chain delay-locked loop includes a delay unit remainder chain 5, a phase detector 2, a locking control unit 1 and two delay chains, wherein the two delay chains include A delay chain composed of multiple delay units and a compensation chain composed of a multi-stage compensation delay unit 6 (Delayline), the delay unit includes a coarse adjustment chain delay unit 7 (Delaycell CT) and a fine adjustment chain delay unit 8 (Delaycell FT);

The reference clock is input from the first delay unit of the delay chain, passes through the coarse adjustment chain delay unit 7 (Delaycell CT) and the fine adjustment chain delay unit 8 (Delaycell FT), and then enters the next delay unit, the coarse adjustment chain delay unit 7 (Delaycell CT) input, fine-tuning chain delay unit 8 (Delaycell FT) output, enter phase detector 2 through delay selection 3 or enter phase detector 2 through delay unit remainder chain 5, at the same time, the reference clock passes through the multi-stage compensation chain The compensation delay unit 6 (Delayline) enters the phase detector 2 after the delay compensation 4, and the phase detector 2 compares the output clock of the compensation chain with the reference clock, and outputs the phase detection result. According to the phase detection result, the locking control unit 1 ( LockControl) adjusts the output clock, if the output clock is ahead of the reference clock, the delay time is increased, the output clock is pushed back, and vice versa, until the phase detector 2 identifies the synchronization of the two clock signals, and the system is locked.

The multiple delay units of the two delay chains and the multi-stage compensation delay unit 6 (Delayline) are equidistantly set to obtain an ideal duty cycle.

The data lines output by the coarse-tuning chain delay unit 7 (Delaycell CT) and the fine-tuning chain delay unit 8 (Delaycell FT) respectively have a Bus structure.

The delay unit in the delay unit remainder chain 5 has the same structure as the coarse adjustment chain delay unit 7 (Delaycell CT).

The reference clock is a pair of differential clocks. The metal traces for the differential clock signals are the same length.

The difference between the output clock and the reference clock is locked to within less than half a clock period.

The invention also discloses a digital double-chain delay phase-locked method, which includes the following steps:

1) Set up two delay chains, including a delay chain composed of multiple delay units and a compensation chain composed of multi-stage compensation delay units 6 (Delayline);

2) The coarse adjustment chain delay unit 7 (Delaycell CT) and the fine adjustment chain delay unit 8 (Delaycell FT) of each delay unit are interleaved and reversed;

3) The reference clock is input from the first delay unit of the delay chain, passes through the coarse adjustment chain delay unit 7 (Delaycell CT) and the fine adjustment chain delay unit 8 (Delaycell FT), and then enters the next delay unit, the coarse adjustment chain delay The input of unit 7 (Delaycell CT), the output of fine-tuning chain delay unit 8 (Delaycell FT), enters phase detector 2 through delay selection 3 or enters phase detector 2 through delay unit remainder chain 5, and at the same time, the reference clock passes through the compensation chain The multi-level compensation delay unit 6 (Delayline) enters the phase detector 2 through the delay compensation 4, and the phase detector 2 compares the output clock of the compensation chain with the reference clock, and outputs the phase detection result;

4) According to the phase detection result, the output clock is adjusted by the lock control unit 1 (LockControl). If the output clock is ahead of the reference clock, the delay time is increased and the output clock is pushed back, and vice versa until the phase detector 2 identifies two The clock signal is synchronized and the system is locked.

A processor or a memory or a clock synchronization device using the above-mentioned DDL.

Claims (9)

1. A digital double-chain delay-locked loop, characterized in that, this digital double-chain delay-locked loop comprises a delay unit remainder chain, a phase detector, a locking control unit and two delay chains, wherein the two delay chains comprise A delay chain composed of a plurality of delay units and a compensation chain composed of multi-stage compensation delay units, the delay units include a coarse adjustment chain delay unit and a fine adjustment chain delay unit arranged upside down; The reference clock is input from the first delay unit of the delay chain, passes through the delay unit of the coarse adjustment chain and the delay unit of the fine adjustment chain, and then enters the next delay unit, the input of the delay unit of the coarse adjustment chain, the output of the delay unit of the fine adjustment chain, after the delay Choose to enter the phase detector or enter the phase detector through the remainder chain of the delay unit. At the same time, the reference clock passes through the multi-stage compensation delay unit of the compensation chain, and enters the phase detector after delay compensation. The phase detector outputs the clock from the compensation chain and the reference clock Make a comparison and output the phase detection result. According to the phase detection result, the output clock is adjusted by the locking control unit. If the output clock is ahead of the reference clock, the delay time is increased and the output clock is pushed back, and vice versa until the phase detector is identified. The two clock signals are synchronized and the system is locked, wherein the reference clock is a pair of differential clocks, namely a differential clock CKP and a differential clock CKN, and the differential clock CKP is elongated to ensure that it matches the differential clock CKN. 2. The digital double-chain delay phase-locked loop as claimed in claim 1, wherein a plurality of delay units and multi-stage compensation delay units of the two delay chains are equidistantly arranged to obtain an ideal duty cycle. 3. The digital double-chain delay phase-locked loop as claimed in claim 1, wherein the data lines respectively output by the coarse adjustment chain delay unit and the fine adjustment chain delay unit are Bus structures. 4. The digital double-chain delay-locked loop as claimed in claim 1, wherein the delay unit in the delay unit remainder chain has the same structure as the coarse adjustment chain delay unit. 5. The digital double-chain delay-locked loop as claimed in claim 1, wherein the lengths of the metal traces of the differential clock signals are the same. 6. The digital double-chain delay-locked loop as claimed in claim 1, wherein the difference between the output clock and the reference clock is locked within a range less than half a clock cycle. 7. A digital double-chain delay-locked method, is characterized in that, comprises the steps: 1) Two delay chains are set, including a delay chain composed of multiple delay units and a compensation chain composed of multi-stage compensation delay units; 2) The coarse-tuning chain delay unit and the fine-tuning chain delay unit of each delay unit are arranged upside down in an alternate manner; 3) The reference clock is input from the first delay unit of the delay chain, passes through the delay unit of the coarse adjustment chain and the delay unit of the fine adjustment chain successively, and then enters the next delay unit, the input of the delay unit of the coarse adjustment chain, and the output of the delay unit of the fine adjustment chain, After delay selection, it enters the phase detector or enters the phase detector through the remainder chain of the delay unit. At the same time, the reference clock passes through the multi-stage compensation delay unit of the compensation chain, and enters the phase detector after delay compensation. The phase detector combines the output clock of the compensation chain with the The reference clock is compared, and the phase detection result is output, wherein the reference clock is a pair of differential clocks, respectively, the differential clock CKP and the differential clock CKN, and the differential clock CKP is elongated to ensure that it matches the differential clock CKN ; 4) Adjust the output clock by the locking control unit according to the phase detection result, if the output clock is ahead of the reference clock, the delay time is increased, the output clock is pushed back, and vice versa, until the phase detector identifies that the two clock signals are synchronous, System locked. 8. A processor or memory using the digital double-chain delay-locked loop according to any one of claims 1-6. 9. A clock synchronization device using a digital double-chain delay-locked loop according to any one of claims 1-6.