CN103779234A - Semiconductor device packaging structure and preparing method - Google Patents
Semiconductor device packaging structure and preparing method Download PDFInfo
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- CN103779234A CN103779234A CN201210399320.XA CN201210399320A CN103779234A CN 103779234 A CN103779234 A CN 103779234A CN 201210399320 A CN201210399320 A CN 201210399320A CN 103779234 A CN103779234 A CN 103779234A
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- 238000000034 method Methods 0.000 title claims abstract description 62
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004806 packaging method and process Methods 0.000 title abstract 2
- 229910052751 metal Inorganic materials 0.000 claims abstract description 226
- 239000002184 metal Substances 0.000 claims abstract description 226
- 238000002161 passivation Methods 0.000 claims abstract description 68
- 230000004888 barrier function Effects 0.000 claims abstract description 58
- 238000003475 lamination Methods 0.000 claims description 37
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 17
- 238000000059 patterning Methods 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 12
- 230000008021 deposition Effects 0.000 claims description 12
- 238000002360 preparation method Methods 0.000 claims description 12
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 9
- 238000005137 deposition process Methods 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 239000002131 composite material Substances 0.000 claims description 2
- 238000012858 packaging process Methods 0.000 abstract 1
- 238000005240 physical vapour deposition Methods 0.000 description 20
- 238000005229 chemical vapour deposition Methods 0.000 description 14
- 239000000428 dust Substances 0.000 description 10
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 10
- 239000000758 substrate Substances 0.000 description 6
- 238000005538 encapsulation Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000000407 epitaxy Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 238000000608 laser ablation Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000013400 design of experiment Methods 0.000 description 1
- 238000012940 design transfer Methods 0.000 description 1
- 239000003085 diluting agent Substances 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to a semiconductor device packaging structure and preparing method. The method comprises the following steps: a metal laminated layer provided with a top metal layer and top through holes are provided; a first passivation layer is deposited on the metal laminated layer to cover the top metal layer; the first passivation layer is patterned to form openings so as to expose the top metal layer; a first metal barrier layer, a first pad metal layer, a second metal barrier layer and a second pad metal layer are deposited successively to form a pad metal laminated layer, wherein the pad metal laminated layer is connected with the top metal layer through the openings; the pad metal laminated layer is patterned to expose the first passivation layer; and a second passivation layer is deposited, and then the second passivation layer is patterned to expose the pad metal laminated layer. According to the structure and method of the invention, the problem that pads are cracked and damaged in the packaging process at present can be well solved to make the wire bonding pads more stable in the back-end process so as to further improve the product yield.
Description
Technical field
The present invention relates to semiconductor applications, particularly, the present invention relates to a kind of package structure of semiconductor device and preparation method.
Background technology
Along with semiconductor fabrication constantly in progressive, transistor grid size constantly dwindle, make constantly dwindling of integrated circuit (IC) apparatus size.At back-end process (The back end of line, BEOL) in, sealing wire combination technology is a kind of widely used method, for the semiconductor element with circuit being connected to the pin in original paper encapsulation, realize I/O(in/out) connect, the size of wherein said line bond pad (wire bond pads) and the setting of described lead-in wire and layout have determined the final size of integrated circuit (IC) apparatus.Active area can make wire bond pad below active device, electrostatic discharge circuit (Electro-Static discharge, ESD), power supply and earth bus guarantee the size reduction of mould in conjunction with (Bond Over Active, BOA) technology.
Copper lead material and copper wire bond process be due to good mechanical performance, electric conductivity and the price more cheap with respect to Precious Metals-Gold, and be widely used in carrying out in integrated antenna package field the packing of high-end integrated circuit.
Copper is larger than golden hardness, therefore in encapsulation process, need larger power and combination power (bond force) just can make metallic copper be combined with metal pad, but larger power and combination power (bond force) bring more challenges to line bond pad, for example, easily cause metal pad (for example aluminium) extruding, extrude, pad cracked and coming off, the damage of metal lead wire, even damage is caused in conjunction with (Bond OverActive, BOA) district in the active area below metal.
For example, conventionally there are two kinds of solutions for described problem (bonding damage and pad are peeled off) at present, one is by DOE(Design Of Experiments) method optimizes bonding parameter, extruding force pad being caused to reduce metallic copper, but the method has significant limitation, for example, after bonding force reduces, will inevitably cause ball to rise (ball lift), and can not meet the demands.Another method is the mechanical strength that increases pad, for example select the damage to active area below metal with opposing of solid pad, Fig. 1 is the composition of solid pad described in prior art, described solid pad comprises the first metal layer 101, metal layer at top 103, through hole 102 between the two, and be positioned at the barrier layer 105 in metal layer at top and be positioned at the aluminum pad metal level 106 on described barrier layer, described pad also comprise be positioned at the first passivation layer 104 in metal layer at top and be positioned at described aluminum metal layer and the first passivation layer on the second passivation layer 107, described preparation method forms first according to a conventional method the first metal layer and metal layer at top as shown in the figure and is positioned at through hole 102 between the two, then in described metal layer at top, form the first passivation layer patterning, then deposited barrier layer, heavy metallic aluminium on described barrier layer, and carry out planarization, form pad metal layer, finally form the second passivation layer, structure as described in Figure 1 and method can reduce the impact of the problems referred to above to a certain extent, but its effect is still not ideal enough, product yield is very low.
Therefore, in preparation method, still exist at present bonding damage and pad the problem such as to peel off, need to improve existing method, to eliminate described problem, improve product yield.
Summary of the invention
In summary of the invention part, introduced the concept of a series of reduced forms, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
The present invention, in order to overcome the problem existing at present in integrated antenna package process, provides a kind of preparation method of package structure of semiconductor device, comprising:
Provide and there is the metal laminated of metal layer at top and top through hole;
Deposit the first passivation layer described on metal laminated, to cover described metal layer at top;
The first passivation layer described in patterning, forms opening to expose described metal layer at top;
Deposit successively the first metal barrier, the first pad metal layer, the second metal barrier, the second pad metal layer, to form pad metal lamination, described pad metal lamination is connected with described metal layer at top by described opening;
Pad metal lamination described in patterning, to expose described the first passivation layer;
Deposit the second passivation layer, then the second passivation layer described in patterning, to expose described pad metal lamination.
As preferably, described method, before described the second passivation layer of deposition, can also further form the composite bed that multilayer is formed by metal barrier, pad metal layer alternating deposit.
As preferably, described the first metal barrier is one or more in TaN, TiN and TaN.
As preferably, described the second metal barrier is one or more in TaN, TiN and TaN.
As preferably, the deposition process of described the first metal barrier and described the second metal barrier is PVD.
As preferably, described the first pad metal layer is Al.
As preferably, described the second pad metal layer is Al.
As preferably, the hardness of described the first metal barrier and described the second metal barrier is greater than described the first pad metal layer and described the second pad metal layer.
As preferably, the deposition process of described the first pad metal layer and described the second pad metal layer is PVD.
The present invention also provides a kind of package structure of semiconductor device, comprising:
Metal laminated, at least comprise metal layer at top and the top through hole that is positioned at described metal layer at top below;
Be positioned at first passivation layer in described metal layer at top with the first opening;
Be positioned at the pad metal lamination on described the first passivation layer, described pad metal lamination at least comprises the first metal barrier, the first pad metal layer, the second metal barrier and the second pad metal layer that stack gradually, and described pad metal lamination is connected with described metal layer at top by described the first opening;
Be positioned at the second passivation layer on described the first passivation layer and pad metal lamination, described the second passivation layer has the second opening, to expose described pad metal lamination.
As preferably, described the first metal barrier and described the second metal barrier are one or more in TaN, TiN and TaN.
As preferably, described the first pad metal layer and described the second pad metal layer are Al.
As preferably, described the first passivation layer and described the second passivation layer are one or more in PESIN, PETEOS, SiN and TEOS.
The present invention also provides a kind of package structure of semiconductor device and preparation method; in encapsulating structure of the present invention, in pad metal lamination, formed by multiple layer metal barrier layer and pad metal layer; the hardness of wherein said metal barrier is greater than the hardness of described pad metal layer; in the time forming line connection, can better protect the active area under metal level and metal level; strengthen the intensity of described pad, well solved the problem that current pad cracks and damages in encapsulation process.Meanwhile, by the described bonding force arranging can further improve described pad line and connect time, expand the Performance And Reliability of technique for sticking window, make back-end process center line bond pad more stable, further improve the yield of product.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining device of the present invention and principle.In the accompanying drawings,
Fig. 1 is package structure of semiconductor device schematic diagram in prior art;
Fig. 2 is package structure of semiconductor device schematic diagram of the present invention;
Fig. 3-6 package structure of semiconductor device preparation process of the present invention schematic diagram;
Fig. 7 is package structure of semiconductor device preparation technology flow chart of the present invention.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.But, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
In order thoroughly to understand the present invention, by propose detailed description in following description, so that package structure of semiconductor device of the present invention and preparation method thereof to be described.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should give attention, the term that used is here only in order to describe specific embodiment, but not intention restriction is according to exemplary embodiment of the present invention.As used herein, unless context explicitly points out in addition, otherwise singulative is also intended to comprise plural form.In addition, it is to be further understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, entirety, step, operation, element and/or assembly, exists or additional one or more other features, entirety, step, operation, element, assembly and/or their combination but do not get rid of.
Now, describe in more detail with reference to the accompanying drawings according to exemplary embodiment of the present invention.But these exemplary embodiments can multiple different form be implemented, and should not be interpreted as being only limited to the embodiments set forth herein.To should be understood that, to provide these embodiment of the present inventionly to disclose thoroughly and complete in order making, and the design of these exemplary embodiments is fully conveyed to those of ordinary skills.In the accompanying drawings, for the sake of clarity, exaggerated the thickness in layer and region, and used the identical Reference numeral to represent identical element, thereby will omit description of them.
A kind of package structure of semiconductor device is provided in the present invention, particularly, pad of the present invention can be line bond pad, probe pad and test point or need other encapsulation or the test pad structure of supporting construction below, in next execution mode and example, all take bond pad, line bond pad as example, but be not limited only to line bond pad.
The invention provides a kind of manufacture method of package structure of semiconductor device.Fig. 7 is the process chart of making pad according to one embodiment of the present invention, and Fig. 3-6 are for making the cutaway view of the device that in pad technical process, each step obtains according to one embodiment of the present invention.
First,, with reference to Fig. 3, provide and there is the metal laminated of metal layer at top and top through hole;
Particularly, as shown in Figure 3, provide metal laminated, describedly metal laminatedly at least comprise the first metal layer 201, metal layer at top 203 and be positioned at the top through hole 202 of realizing linkage function between the two, below described the first metal layer 201, can also comprise multiple similar metal-layer structures as shown in Figure 3, described pad is connected with the substrate of integrated circuit.
Wherein, described substrate is semiconductor substrate, on this substrate, can form one or more active devices, described active device can be transistor, diode and the known active device described in other, described passive device can be resistor, capacitor and inductor and other known various passive devices, described substrate is connected and fetches formation integrated circuit with pad of the present invention, but described substrate can't bring crucial impact to pad structure of the present invention, does not therefore repeat them here.
With reference to Fig. 4, deposit the first passivation layer described on metal laminated, to cover described metal layer at top, the first passivation layer described in patterning, forms opening to expose described metal layer at top;
Particularly, first deposit the first passivation layer 204 described on metal laminated, described passivation layer comprises that plasma enhanced silicon nitride layer PESIN layer, plasma strengthen one or more the combination in tetraethoxysilane PETEOS layer, SiN layer and tetraethoxysilane TEOS layer.
In the specific embodiment of the invention, the combination that described the first passivation layer is above-mentioned various materials, described the first passivation layer comprises the PESIN layer, PETEOS layer, SiN layer and the TEOS layer that stack gradually, as preferably, the thickness of described PESIN layer is 650-850 dust, the thickness of described PETEOS layer is 3800-4200 dust, and the thickness of described SiN layer is 650-850 dust, and the thickness of described TEOS layer is 2400-2600 dust; As further preferably, the thickness of described PESIN layer is 750 dusts, described PETEOS(Plasma Enhanced TEOS) thickness of layer is 4000 dusts, and the thickness of described SiN layer is 750 dusts, and the thickness of described TEOS layer is 2500 dusts.
As preferably, the deposition process of described the first passivation layer can be selected the one in low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and the selective epitaxy growth (SEG) that chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method or ald (ALD) method etc. form.Preferred chemical vapor deposition (CVD) method in the present invention.
Then described in etching the first passivation layer to form opening, expose described metal layer at top, particularly, in the specific embodiment of the present invention, above described the first passivation layer, form photoetching agent pattern, carry out etching take described photoetching agent pattern as mask, design transfer, to described the first passivation layer, is formed to opening and exposes described metal layer at top, and described engraving method is not limited only to above-mentioned example, those skilled in the art can select as required, do not repeat them here.
With reference to Fig. 5, deposit successively the first metal barrier, the first pad metal layer, the second metal barrier, the second pad metal layer, to form pad metal lamination, described pad metal lamination is connected with described metal layer at top by described opening;
Particularly; first deposit the first metal barrier 205; described the first metal barrier is one or more in TaN, TiN and TaN; the hardness of described the first metal barrier will be far longer than described pad metal layer; forming the impact that can resist external force in the process connecting, better protect the metal laminated and active device that is positioned at below.
As preferably, the thickness of described the first metal barrier is 600-800 dust, the one that the deposition of described the first metal barrier can select low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and the selective epitaxy of the formation such as chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method or ald (ALD) method to grow in (SEG), further, more preferably physical vapor deposition (PVD) method in the present invention.
Then, deposition the first pad metal layer 206, described the first pad metal layer can be Al layer, described pad metal layer can be smaller than metal layer thickness of the prior art in the present invention.In a kind of embodiment of the present invention, the thickness of described the first pad metal layer is 4-20 thousand dusts.
As preferably, the deposition process of described the first pad metal layer can be the one that low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and the selective epitaxy of the formation such as chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method or ald (ALD) method grown in (SEG), is preferably in the present invention physical vapor deposition (PVD) method.
Carry out planarisation step, to form smooth surface, adhesion when increase toe-in closes, described planarisation step is selected chemical mechanical planarization method (CMP).
Then, deposit the second metal barrier 207, wherein, described the second metal barrier 207 is one or more in TaN, TiN and TaN, the hardness of described the first metal barrier will be far longer than described pad metal layer, the thickness of described the second metal barrier is 600-800 dust, the preferred physical vapor deposition (PVD) method of deposition of described the second metal barrier.
Preferably material and the thickness the same with described the first metal barrier of described the second metal barrier in the present invention, its formation method all can be with reference to the method for operation of described the first metal barrier, do not repeat them here, but be not limited only to the method, those skilled in the art can select conventional additive method.
Finally, deposition the second pad metal layer 208, to form pad metal lamination, described the second pad metal layer can be Al layer, in a kind of embodiment of the present invention, the thickness of described the first pad metal layer is 4-20 thousand dusts.
As preferably, the deposition process of described the second pad metal layer can be the one that low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and the selective epitaxy of the formation such as chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method or ald (ALD) method grown in (SEG), is preferably in the present invention physical vapor deposition (PVD) method.Then carry out planarisation step, to form smooth surface, adhesion when increase toe-in closes, described planarisation step is selected chemical mechanical planarization method (CMP).
With reference to Fig. 6, pad metal lamination described in patterning, to expose described the first passivation layer;
Particularly, first form photoresist mask layer, take described photoresist mask layer as pad metal lamination described in mask etch, remove the two side portions of described pad metal lamination, to expose described the first passivation layer, in this step, can select pad metal lamination described in dry etching, in described dry etching, can select CF
4, CHF
3, add in addition N
2, CO
2, O
2in one as etching atmosphere, wherein gas flow is CF
410-200sccm, CHF
310-300sccm, N
2or CO
2or O
210-300sccm, described etching pressure is 30-250mTorr, etching period is 5-180s, is preferably 5-60s, more preferably 5-30s, described dry etching can also select Ar as diluent gas.
With reference to Fig. 2, deposition the second passivation layer, then the second passivation layer described in patterning, to expose described pad metal lamination;
Particularly, particularly, described the second passivation layer comprises that plasma enhanced silicon nitride layer PESIN layer, plasma strengthen one or more the combination in tetraethoxysilane PETEOS layer, SiN layer and tetraethoxysilane TEOS layer.
In the specific embodiment of the invention, the combination that described the second passivation layer is above-mentioned various materials, described the first passivation layer comprises the PESIN layer, PETEOS layer, SiN layer and the TEOS layer that stack gradually, as preferably, the thickness of described PESIN layer is 650-850 dust, the thickness of described PETEOS layer is 3800-4200 dust, and the thickness of described SiN layer is 650-850 dust, and the thickness of described TEOS layer is 2400-2600 dust; As further preferably, the thickness of described PESIN layer is 750 dusts, described PETEOS(Plasma Enhanced TEOS) thickness of layer is 4000 dusts, and the thickness of described SiN layer is 750 dusts, and the thickness of described TEOS layer is 2500 dusts.
As preferably, the deposition process of described the second passivation layer can be selected the one in low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and the selective epitaxy growth (SEG) that chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method or ald (ALD) method etc. form.Preferred chemical vapor deposition (CVD) method in the present invention.
Then described in patterning, the second passivation layer, to form opening, exposes described the second pad metal layer, obtains device as shown in Figure 2.
It should be noted that, before forming described the second passivation layer, can also continue as required metal barrier and described pad metal layer described in alternating deposit multilayer, be not limited only to form two-layer, but at least to form two-layer, to guarantee that it has enough hardness and adhesion, in formation line cohesive process, apply under the effect of external force, described pad metal layer can be not chipping, and the active device that is positioned at below can not damage.
The present invention also provides a kind of package structure of semiconductor device, as shown in Figure 2, comprising:
Metal laminated, at least comprise metal layer at top 203 and the top through hole 202 that is positioned at described metal layer at top below, can further include the first metal layer 201, and be positioned at multiple metal levels of the first metal layer below, between described metal level, all connect by through hole;
Be positioned at first passivation layer 204 in described metal layer at top with the first opening;
Be positioned at the pad metal lamination on described the first passivation layer, described pad metal lamination at least comprises the first metal barrier 205, the first pad metal layer 206, the second metal barrier 207 and the second pad metal layer 208 that stack gradually, and described pad metal lamination is connected with described metal layer at top by described the first opening;
Be positioned at the second passivation layer 209 on described the first passivation layer and pad metal lamination, described passivation layer has the second opening, to expose described pad metal lamination.
Wherein, described the first metal barrier and described the second metal barrier are one or more in TaN, TiN and TaN, described the first pad metal layer and described the second pad metal layer are Al, and described the first passivation layer and described the second passivation layer are one or more in PESIN, PETEOS, SiN and TEOS.
Fig. 7 is package structure of semiconductor device preparation technology flow chart of the present invention, comprises the following steps:
Step 201 provides has the metal laminated of metal layer at top and top through hole;
Step 202 deposits the first passivation layer described on metal laminated, to cover described metal layer at top;
The first passivation layer described in step 203 patterning, forms opening to expose described metal layer at top;
Step 204 deposits the first metal barrier, the first pad metal layer, the second metal barrier, the second pad metal layer successively, and to form pad metal lamination, described pad metal lamination is connected with described metal layer at top by described opening;
Pad metal lamination described in step 205 patterning, to expose described the first passivation layer;
Step 206 deposits the second passivation layer, and then the second passivation layer described in patterning, to expose described pad metal lamination.
The present invention also provides a kind of package structure of semiconductor device and preparation method; in encapsulating structure of the present invention, in pad metal lamination, formed by multiple layer metal barrier layer and pad metal layer; the hardness of wherein said metal barrier is greater than the hardness of described pad metal layer; in the time forming line connection, can better protect the active area under metal level and metal level; strengthen the intensity of described pad, well solved the problem that current pad cracks and damages in encapsulation process.Meanwhile, by the described bonding force arranging can further improve described pad line and connect time, expand the Performance And Reliability of technique for sticking window, make back-end process center line bond pad more stable, further improve the yield of product.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition, it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (13)
1. a preparation method for package structure of semiconductor device, comprising:
Provide and there is the metal laminated of metal layer at top and top through hole;
Deposit the first passivation layer described on metal laminated, to cover described metal layer at top;
The first passivation layer described in patterning, forms opening to expose described metal layer at top;
Deposit successively the first metal barrier, the first pad metal layer, the second metal barrier, the second pad metal layer, to form pad metal lamination, wherein, described pad metal lamination is connected with described metal layer at top by described opening;
Pad metal lamination described in patterning, to expose described the first passivation layer;
Deposit the second passivation layer, then the second passivation layer described in patterning, to expose described pad metal lamination.
2. method according to claim 1, is characterized in that, described method, before described the second passivation layer of deposition, also comprises the composite bed that further formation multilayer is formed by described metal barrier, pad metal layer alternating deposit.
3. method according to claim 1, is characterized in that, described the first metal barrier is one or more in TaN, TiN and TaN.
4. method according to claim 1, is characterized in that, described the second metal barrier is one or more in TaN, TiN and TaN.
5. method according to claim 1, is characterized in that, the deposition process of described the first metal barrier and described the second metal barrier is PVD.
6. method according to claim 1, is characterized in that, described the first pad metal layer is Al.
7. method according to claim 1, is characterized in that, described the second pad metal layer is Al.
8. according to the method described in claim 6 or 7, it is characterized in that, the hardness of described the first metal barrier and described the second metal barrier is greater than described the first pad metal layer and described the second pad metal layer.
9. method according to claim 1, is characterized in that, the deposition process of described the first pad metal layer and described the second pad metal layer is PVD.
10. a package structure of semiconductor device, comprising:
Metal laminated, at least comprise metal layer at top and the top through hole that is positioned at described metal layer at top below;
Be positioned at first passivation layer in described metal layer at top with the first opening;
Be positioned at the pad metal lamination on described the first passivation layer, described pad metal lamination at least comprises the first metal barrier, the first pad metal layer, the second metal barrier and the second pad metal layer that stack gradually, and described pad metal lamination is connected with described metal layer at top by described the first opening;
Be positioned at the second passivation layer on described the first passivation layer and pad metal lamination, described the second passivation layer has the second opening, to expose described pad metal lamination.
11. encapsulating structures according to claim 10, is characterized in that, described the first metal barrier and described the second metal barrier are one or more in TaN, TiN and TaN.
12. encapsulating structures according to claim 10, is characterized in that, described the first pad metal layer and described the second pad metal layer are Al.
13. encapsulating structures according to claim 10, is characterized in that, described the first passivation layer and described the second passivation layer are one or more in PESIN, PETEOS, SiN and TEOS.
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| CN201210399320.XA CN103779234A (en) | 2012-10-18 | 2012-10-18 | Semiconductor device packaging structure and preparing method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105384140A (en) * | 2014-08-31 | 2016-03-09 | 天工方案公司 | Stack structures in electronic devices |
| CN111200046A (en) * | 2020-01-13 | 2020-05-26 | 广东省半导体产业技术研究院 | LED chip structure and manufacturing method thereof |
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|---|---|---|---|---|
| KR20030091448A (en) * | 2002-05-28 | 2003-12-03 | 삼성전자주식회사 | Bonding pad structure of a semiconductor device and a method of fabricating the same |
| US20050280149A1 (en) * | 2004-06-18 | 2005-12-22 | Nec Electronics Corporation | Semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20030091448A (en) * | 2002-05-28 | 2003-12-03 | 삼성전자주식회사 | Bonding pad structure of a semiconductor device and a method of fabricating the same |
| US20050280149A1 (en) * | 2004-06-18 | 2005-12-22 | Nec Electronics Corporation | Semiconductor device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105384140A (en) * | 2014-08-31 | 2016-03-09 | 天工方案公司 | Stack structures in electronic devices |
| CN105384140B (en) * | 2014-08-31 | 2021-11-26 | 天工方案公司 | Improved stacking structure in electronic device |
| US11257774B2 (en) | 2014-08-31 | 2022-02-22 | Skyworks Solutions, Inc. | Stack structures in electronic devices including passivation layers for distributing compressive force |
| US11804460B2 (en) | 2014-08-31 | 2023-10-31 | Skyworks Solutions, Inc. | Devices and methods related to stack structures including passivation layers for distributing compressive force |
| CN111200046A (en) * | 2020-01-13 | 2020-05-26 | 广东省半导体产业技术研究院 | LED chip structure and manufacturing method thereof |
| CN111200046B (en) * | 2020-01-13 | 2022-06-03 | 广东省半导体产业技术研究院 | LED chip structure and manufacturing method thereof |
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