CN103762202B - Chip packaging method and structure - Google Patents

Abstract

A chip packaging method and packaging structure, the chip packaging method includes: providing a base, the base includes: a substrate and a client layer on the surface of the substrate, the surface of the client layer is the first surface of the substrate, opposite to the first surface The surface of the substrate is the second surface, and several pads are formed in the customer layer; the second surface of the substrate is etched to form a groove, and the groove has a first sub-groove and is located on both sides of the first sub-groove. The protruding second sub-groove, the first sub-groove communicates with the second sub-groove, the second sub-groove exposes part of the surface of the pad, and the second sub-groove only exposes the solder pad One side of the pad; form an insulating layer on the inner wall of the groove and the second surface of the substrate; form a through hole in the pad, penetrate the insulating layer and the pad; form a wiring metal layer; form a solder resist layer, inside the solder resist layer There is an opening, and the opening exposes part of the surface of the wiring metal layer; solder balls are formed in the opening. The above method can improve the reliability of the packaging structure.

Description

Chip packaging method and packaging structure

technical field

The invention relates to the technical field of semiconductors, in particular to a chip packaging method and packaging structure.

Background technique

Wafer Level Chip Size Packaging (WLCSP) technology is a technology that performs packaging and testing on the entire wafer and then cuts it to obtain a single finished chip. The size of the packaged chip is the same as that of the bare chip. Wafer-level chip-scale packaging technology has changed traditional packaging such as ceramic leadless chip carrier (Ceramic Leadless ChipCarrier), organic leadless chip carrier (Organic Leadless Chip Carrier) and digital camera module mode, conforming to the market demand for microelectronics products Increasingly light, small, short, thin and low-cost requirements. The size of the chip packaged by the wafer-level chip size packaging technology has reached a high degree of miniaturization, and the cost of the chip is significantly reduced with the reduction of the chip size and the increase of the wafer size. Wafer-level chip-scale packaging technology is a technology that can integrate IC design, wafer manufacturing, packaging testing, and substrate manufacturing. It is a hot spot in the current packaging field and a future development trend.

The existing wafer-level chip-scale packaging method mainly includes the following steps:

First, press the semiconductor wafer with the substrate. The client layer refers to the material layer on which the device is formed. The device part on the surface of the wafer is protected by the substrate to reduce external pollution and damage; After thinning, the wafer is etched using photolithography technology and plasma dry etching process to form grooves and expose several welding pads.

Then, an insulating layer is formed on the surface of the groove, and laser drilling is performed on the welding pad.

Finally, a metal layer is deposited on the back of the wafer, and the metal layer is patterned to form a metal circuit to complete the wiring; a solder resist layer is formed on the metal circuit to fill the groove, and an opening is formed at the soldering place, and an opening is formed on the metal circuit. Solder balls are formed in the openings; then the wafer is cut along the center of the dicing line to obtain chips; the chips are electrically connected to the PCB board through solder balls to realize signal input and output.

For more wafer-level chip size packaging methods, please refer to the Chinese patent with publication number CN101419952A.

The reliability of the packaging structure formed by the existing chip packaging method needs to be further improved.

Contents of the invention

The problem to be solved by the present invention is to provide a chip packaging method and a packaging structure to improve the reliability of the packaging structure.

In order to solve the above problems, the present invention provides a chip packaging method, including: providing a substrate, the substrate includes a first surface and a second surface opposite to the first surface, the first surface has a customer layer and is located on the customer Welding pads in the layer; etching the second surface of the substrate to form a groove, the groove has a first sub-groove and protruding second sub-grooves located on both sides of the first sub-groove, so The first sub-groove communicates with the second sub-groove, the second sub-groove exposes part of the surface of the pad, and the second sub-groove exposes at most one side of the pad; An insulating layer is formed on the inner wall surface of the groove and the second surface of the base; a through hole is formed, and the through hole is located in the pad and penetrates the insulating layer and the pad; and a wiring metal is formed on the surface of the groove and the through hole layer; forming a solder resist layer on the surface of the wiring metal layer, the solder resist layer has an opening, and the opening exposes part of the surface of the wiring metal layer; forming solder balls on the surface of the wiring metal layer in the opening.

Optionally, the first sub-groove is located on the surface of the client layer between adjacent pads.

Optionally, the second sub-groove includes a first part and a second part, the first part is located on the surface of the pad, the second part is located on the surface of the client layer, and communicates with the first part and the first groove.

Optionally, a laser drilling process is used to form the through holes.

Optionally, the method further includes: providing a substrate, and forming the groove after pressing the first surface of the substrate and the substrate.

Optionally, the material of the insulating layer includes a polymer organic insulating polymer or an inorganic insulating dielectric material.

Optionally, the insulating layer is formed by using a spray coating process, a spin coating process or a chemical vapor deposition process.

In order to solve the above problems, the technical solution of the present invention also provides a packaging structure formed by the above method, including: a base, the base includes a first surface and a second surface opposite to the first surface, the first The surface has a client layer and pads located in the client layer; a groove located in the second surface of the substrate, the groove has a first sub-groove and protruding second grooves positioned on both sides of the first sub-groove A sub-groove, the first sub-groove communicates with the second sub-groove, the second sub-groove exposes part of the surface of the pad, and the second sub-groove exposes at most the surface of the pad One edge; the insulating layer located on the inner wall surface of the groove and the second surface of the base; the through hole located in the pad, and the through hole penetrates the insulating layer and the pad; the groove located on the surface of the through hole The wiring metal layer; the solder resist layer located on the surface of the wiring metal layer, the solder resist layer has an opening, and the opening exposes part of the surface of the wiring metal layer; the solder mask located on the surface of the wiring metal layer in the opening ball.

Optionally, the first sub-groove is located on the surface of the client layer between adjacent pads.

Optionally, the second sub-groove includes a first part and a second part, the first part is located on the surface of the pad, the second part is located on the surface of the client layer, and communicates with the first part and the first groove.

Optionally, it also includes: a substrate, the first surface of the substrate is press-bonded with the substrate.

Optionally, the material of the insulating layer includes a polymer organic insulating polymer or an inorganic insulating dielectric material.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the technical solution of the present invention, the second surface of the substrate is etched to form a groove, the groove has a first sub-groove and protruding second sub-grooves located on both sides of the first sub-groove, the The first sub-groove communicates with the second sub-groove, the second sub-groove exposes part of the surface of the pad, and the second sub-groove only exposes one side of the pad. Since the second sub-groove only exposes one side of the welding pad, the remaining three sides of the welding pad are covered by the substrate above the welding pad, and the substrate can effectively support the welding pad The role of offsetting the stress on the pads and avoiding the disconnection of the connection between the pads and the substrate due to excessive stress on the pads can improve the reliability of the formed packaging structure and the reliability of the packaged chip.

Description of drawings

1 to 10 are schematic views of the forming process of the package structure according to the embodiment of the present invention.

detailed description

As mentioned in the background art, the reliability of the packaging structure formed by the existing chip packaging method is low.

On the one hand, because the thickness of the solder resist layer filled in the groove is relatively large, during the thermal curing process of forming the solder resist layer, due to the difference in thermal expansion coefficient between the solder resist layer and the wafer, a larger The stress is transmitted to the customer layer, and a large stress is generated in the customer layer; and in the process of forming solder balls in the reflow soldering process, due to the difference in thermal expansion coefficient between the solder resist layer and the wafer, the high temperature during the reflow soldering process is also Will create stress in the client layer.

On the other hand, after the wafer packaging is completed, it is necessary to electrically connect the solder balls on the chip to the PCB board by means of reflow soldering, and then fill them with glue. Since the material of the solder resist layer is different from that of the glue material used for filling the glue, during the thermal cycle test, stress will be generated due to the thermal mismatch between the two and transmitted to the customer layer, because the customer layer is As a whole, the stress cannot be released, and because the connection between the silicon wafer and the pad at the bottom of the groove is relatively fragile, under the action of stress, the connection between the pad and the silicon will be disconnected, making the reliability of the package structure reduce.

In the embodiment of the present invention, during the process of forming the groove, the bottom of the groove only exposes part of the surface of the pad, so that the base of the side wall of the groove can sufficiently protect and support the pad, The disconnection of the connection between the pad and the substrate under stress is avoided, thereby improving the reliability of the package structure.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

Please refer to FIG. 1 , a substrate is provided, the substrate includes: a substrate 100 and a client layer 110 positioned on the surface of the substrate 100, the surface of the client layer 110 is the first surface 11 of the substrate, opposite to the first surface 11 The surface of the substrate 100 is the second surface 12, and several welding pads 120 are formed in the client layer 110.

The second surface 12 of the substrate is a surface without devices, while the first surface 11 is a surface with devices. The semiconductor device 10 is formed in the client layer 110 , and the number of the bonding pads 120 is multiple, which are discretely arranged on the periphery of the semiconductor device 10 . In this embodiment, the shape of the welding pad 120 is a rectangle. In other embodiments of the present invention, the shape of the welding pad 120 can also be other suitable shapes. Input/output terminals for circuit connections. The semiconductor device 10 may be an image sensor, a photodiode, or a micro-electro-mechanical system or the like.

FIG. 1 shows a schematic cross-sectional view of two continuous chips, with two chips on both sides of the dotted line. After the encapsulation structure is subsequently formed, cutting is performed at the position of the dotted line to obtain the packaged chip, and the dotted line is the cutting line.

Referring to FIG. 2 , a substrate 200 is provided, and the first surface 11 of the substrate 100 is pressed against the substrate 200 .

The size of the substrate 200 is the same as that of the base 100 , and the substrate 200 includes a bottom plate 201 and a cavity wall 202 .

Specifically, the bottom plate 201 may be glass, and the cavity wall 202 is formed by spin-coating a photoresist on the surface of the bottom plate 201, exposing and developing. On the side of the cavity wall 202 on the substrate 200 away from the bottom plate 201, an adhesive layer (not shown) is formed. The adhesive layer can be a polymer adhesive material, such as silica gel, epoxy resin, benzocyclidine, etc. ene etc. The adhesive layer can not only realize the bonding function, but also play the role of insulation and sealing.

The substrate 200 is pressed against the first surface 11 of the base 100, the cavity surrounded by the cavity wall 202 and the customer layer 110 corresponds to the semiconductor device 10 formed on the wafer 100, and the bonding pad 120 is located in the cavity. On the surface of the cavity wall 202 , the semiconductor device 10 is located in the cavity.

Subsequent FIGS. 3 to 10 are partial schematic diagrams of the area I in FIG. 2 .

Please refer to FIG. 3 and FIG. 4, the second surface 12 of the substrate is etched to form a groove 101, the groove 101 has a first sub-groove 111 and protruding second grooves located on both sides of the first sub-groove 111. A sub-groove 121, the first sub-groove 111 communicates with the second sub-groove 121, the second sub-groove 121 exposes part of the surface of the pad 120, and the second sub-groove 121 only exposes out of one side of the pad 120. Fig. 3 is a schematic cross-sectional view of a secant line along the AA' direction of Fig. 4 .

Before forming the groove 101, the second surface 12 of the substrate may also be thinned. Specifically, the second surface 12 of the substrate may be thinned to a desired thickness by using a chemical mechanical polishing process.

A mask layer with an opening is formed on the second surface 12 ; the substrate 100 is etched along the opening to form a groove 101 . The mask layer may be a photoresist layer, and the groove 101 may be formed by a plasma etching process. The inclination angle of the sidewall and the width of the bottom of the groove 101 can be controlled by the parameters of the plasma etching process.

The groove 101 can be arranged along the cutting line 20 (please refer to FIG. 4 ) between adjacent chips, and is symmetrical about the cutting line 20 , serving as a dicing line for subsequent mechanical dicing process. Several pads 120 at the bottom of the groove 101 respectively correspond to different semiconductor chips.

Specifically, in this embodiment, the groove 101 includes a first sub-groove 111 and second sub-grooves 121 located on both sides of the first sub-groove 111 . The first sub-groove 111 communicates with the second sub-groove 121 , and the extending directions are perpendicular to each other. The top view of the groove 101 is in the shape of a rib hole.

In this embodiment, the substrate is subsequently cut along the first sub-groove 111 , and the first sub-groove 111 is located on the surface of the client layer 110 between adjacent pads 120 . The second sub-groove 111 is located on the pad 120 for exposing part of the surface of the pad 120 .

The second sub-groove 121 includes a first part and a second part, the first part is located on the surface of the pad 120 , the second part is located on the surface of the client layer 110 , and communicates with the first part and the first groove 111 . The second sub-groove 121 only exposes one side of the welding pad 120 near the position of the first sub-groove 111, so that the other three sides of the welding pad 120 and part of the welding pad 120 on the edge are covered by the upper lining. The bottom 100 covers, so that the substrate 100 can provide support for the bonding pad 120 .

Compared with the prior art, the embodiment of the present invention can improve the reliability of the connection between the pad 120 and the substrate 100, and the substrate 100 and the pad 120 will not be connected under the stress generated by the subsequent process involving heat treatment. It can improve the reliability of the packaging structure.

In this embodiment, the second sub-groove 121 only exposes one side of the solder pad 120 close to the first sub-groove 111 , and the other sides are covered by the substrate 100 above the solder pad. The vertical distance between the sidewall of the second sub-groove 121 and the unexposed side of the welding pad 120 is relatively low, so that the exposed area of the welding pad 120 is relatively large, so as to reduce the subsequent formation of vias on the welding pad 120. Alignment difficulty of holes.

The welding pad 120 is pressed against more parts by the substrate 100 above it, so that the substrate 100 provides effective support for the welding pad 120, and the substrate 100 covers the three sides of the welding pad 120, so that the welding pad 120 is The positions where the substrate 100 is pressed are distributed in a wide range, and have a strong offsetting effect on the stress applied to the bonding pad 120 .

Referring to FIG. 5 , an insulating layer 102 is formed on the inner wall surface of the groove 101 and the second surface 12 of the substrate.

The material of the insulating layer 102 can be high molecular organic insulating polymer materials such as photoresist and silica gel, and the material of the insulating layer 102 can also be inorganic insulating dielectric materials such as silicon nitride and silicon oxide. The insulating layer 102 is formed by a chemical vapor deposition process, a spin coating process, and the like. The thickness of the insulating layer 102 may be 2um˜20um.

The insulating layer 102 serves as an isolation layer between the subsequently formed wiring metal layer and the substrate 100 .

Referring to FIG. 6 and FIG. 7 , a via hole 103 is formed. The via hole 103 is located in the pad 120 and penetrates the insulating layer 102 and the pad 120 . FIG. 7 is a schematic top view after forming the through hole 103 (wherein, the insulating layer is not shown). Fig. 6 is a schematic cross-sectional view along the secant line AA' in Fig. 7 .

The through hole 103 is formed by a laser drilling process, the cross section of the through hole 103 can be circular or oval, etc., and the through hole 103 is completely located in the welding pad 120, penetrating the surface of the welding pad 120 The insulating layer 102 and the pad 120. After the through hole 103 is formed, the sidewall of the through hole 103 exposes the pad 120 .

Referring to FIG. 8 , a wiring metal layer 104 is formed on the surface of the groove 101 and the through hole 103 .

The method for forming the wiring metal layer 104 includes: forming a metal layer on the surface of the groove 101 , the through hole 103 and the insulating layer 102 ; and patterning the metal layer to form the wiring metal layer 104 .

The thickness of the metal layer should not be too large, so as to avoid blocking the top opening of the through hole 103 during the formation of the metal layer, and form holes in the second groove 103, which will affect the contact quality between the metal layer and the welding pad 120 .

The metal layer can be formed by a sputtering process, so that the metal layer has high uniformity, and the material of the metal layer can be copper, tungsten, aluminum, titanium, aluminum-nickel alloy, gold and other metal materials.

After the metal layer is patterned, the wiring metal layer 104 is formed, and the wiring metal layer 104 includes the under-ball metal layer part on the second surface 12 of the substrate and the outer lead part connected to the pad 120 in the groove 101; The part of the outer lead is electrically connected to the part of the metal layer under the ball and the pad 120 .

The process of patterning the metal layer is to divide the metal layer into a plurality of mutually disconnected outer leads and under-ball metal layer parts.

Specifically, a photolithography process and a wet etching process may be used to pattern the metal layer to form the wiring metal layer 104 .

Referring to FIG. 9 , a solder resist layer 106 is formed on the surface of the wiring metal layer 104 , the solder resist layer 106 has an opening 107 therein, and the opening 107 exposes part of the surface of the wiring metal layer 104 .

The solder resist layer 106, the solder resist layer 106 covers the wiring metal layer, the solder resist layer 106 can be made of the same material as the insulating layer 102, can be photoresist, silica gel and other polymer organic insulating polymer materials, can be The solder resist layer 106 is formed by spin coating or spray coating.

The positions of the openings 107 in the solder resist layer 106 are the positions of the solder balls connected to the wiring metal layer to be subsequently formed.

The method of forming the solder resist layer 106 may be to pattern the solder resist layer material after forming the solder resist layer material on the surface of the wiring metal layer 104, and form openings 107 at positions where solder balls need to be formed subsequently.

The solder resist layer 106 can protect the wiring metal layer 104 from subsequent processes, and can reduce the exposure of metal other than solder joints, which may cause short circuit problems during the process of forming solder balls.

Referring to FIG. 10 , solder balls 108 on the surface of the wiring metal layer 104 are formed in the opening 107 (please refer to FIG. 9 ).

The solder balls 108 are electrically connected to the solder pads 120 through the wiring metal layer 104 .

Specifically, the solder balls 108 may be formed by screen printing technology and reflow technology.

Subsequently, the substrate can be cut along the first sub-groove 111 through a cutting process to obtain a chip-scale packaged chip with a ball grid array, and the chip is reflowed through solder balls and a PCB board. Electrical connection, then glue filling, signal input and output, and thermal cycle test.

Since the glue material used in the glue filling process is different from the material of the solder resist layer, thermomechanical stress will be generated due to the difference in thermal expansion coefficient between the two during the thermal cycle test. The thermomechanical stress is transmitted to the solder pad and the client layer through the solder resist layer. Since the client layer is a whole, the stress cannot be released in time, so that the solder pad will be subject to greater stress.

In the prior art, only a small part of the solder pad is covered by the substrate above it, and the solder pad is relatively fragile at the connection between the root of the groove and the substrate 100. Under the stress generated in the thermal cycle test, the substrate The connection between 100 and pad 120 is easily disconnected, which reduces the reliability of the packaged chip.

However, in an embodiment of the present invention, a groove in the shape of a rib hole is formed on the second surface of the substrate, the groove has a first sub-groove and a second sub-groove, and the second sub-groove exposes the solder pad Part of the surface of the pad, and only one side of the pad is exposed, so that the remaining three sides of the pad are covered by the substrate above the pad, and the substrate can effectively support the pad and offset The stress effect on the pads in the subsequent process can avoid the problem of disconnection of the connection between the pads and the substrate during the thermal cycle test, and improve the reliability of the packaging structure and the reliability of the packaged chip.

To solve the above problems, the present invention also provides a packaging structure formed by the above method.

Please refer to FIG. 10 , which is a schematic cross-sectional view of the packaging structure.

The packaging structure includes: a base, the base includes: a substrate 100 and a client layer 110 located on the surface of the substrate 100, the surface of the client layer 110 is the first surface 11 of the substrate, opposite to the first surface 11 The surface of the substrate 100 is the second surface 12, and several welding pads 120 are formed in the customer layer 110; the groove 101 located in the second surface 12, the groove 101 has a first sub-groove 111 and the protruding second sub-groove 121 located on both sides of the first sub-groove 111, the first sub-groove 111 communicates with the second sub-groove 121, and the second sub-groove 121 exposes the solder Part of the surface of the pad 120, and the second sub-groove 121 only exposes one side of the pad 120; the insulating layer 102 located on the inner wall surface of the groove 101 and the second surface 12 of the substrate 100; The through hole in the pad 120, the through hole penetrates the insulating layer 102 and the pad 120; the wiring metal layer 104 on the surface of the groove 101 and the through hole; the solder resist layer on the surface of the wiring metal layer 104 106 , there is an opening in the solder resist layer 106 , and the opening exposes part of the surface of the wiring metal layer 104 ; and the solder ball 108 on the surface of the wiring metal layer 104 is located in the opening.

The packaging structure further includes: a substrate 200 , and the first surface 11 of the substrate 100 is pressed against the substrate 200 . The size of the substrate 200 is the same as that of the base 100 , and the substrate includes a bottom plate 201 and a cavity wall 202 .

Please refer to FIG. 7 , which is a schematic top view of the groove 101 , the through hole 103 , the pad 120 and the substrate 100 in the package structure.

In this embodiment, the first sub-groove 111 is located on the surface of the client layer between adjacent pads 120 .

The second sub-groove 121 exposes a side of the pad 120 .

The vertical distance between the sidewall of the second sub-groove 121 and the unexposed side of the welding pad 120 is small, so that the exposed area of the welding pad 120 is large, so that the through hole 103 can be completely located on the welding pad. Within 120.

In the package structure, the solder pad 120 is covered by the substrate above it on three sides, which improves the support of the substrate to the solder pad 120, and exposes more of the solder pad surface, which can effectively offset the thermal cycle test. The effect of thermomechanical stress on the pad prevents the disconnection of the connection between the pad and the substrate, thereby improving the reliability of the packaging structure and the reliability of the packaged chip.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (12)

1. A chip packaging method, characterized in that, comprising: A base is provided, the base includes: a substrate and a client layer located on one surface of the substrate, the other surface of the client layer is the first surface of the substrate, and the other surface of the substrate opposite to the first surface is the substrate The second surface of the client layer is a material layer with several welding pads formed inside; Etching the second surface of the base to form a groove, the groove has a first sub-groove and protruding second sub-grooves located on both sides of the first sub-groove, the first sub-groove Communicating with the second sub-groove, the second sub-groove exposes part of the surface of the pad, and the second sub-groove only exposes one side of the pad; forming an insulating layer on the inner wall surface of the groove and the second surface of the base; forming a via hole within the pad and penetrating the insulating layer and the pad; forming a wiring metal layer on the surface of the groove and the through hole; A solder resist layer is formed on the surface of the wiring metal layer, and an opening is formed in the solder resist layer, and the opening exposes part of the surface of the wiring metal layer; A solder ball on the surface of the wiring metal layer is formed in the opening. 2 . The chip packaging method according to claim 1 , wherein the first sub-groove is located on the surface of the client layer between adjacent pads. 3 . 3. The chip packaging method according to claim 1, wherein the second sub-groove includes a first part and a second part, the first part is located on the surface of the pad, and the second part is located on the surface of the client layer, communicating with the The first part and the first groove. 4. The chip packaging method according to claim 1, wherein the through hole is formed by a laser drilling process. 5. The chip packaging method according to claim 1, further comprising: providing a substrate, and forming the groove after pressing the first surface of the substrate to the substrate. 6 . The chip packaging method according to claim 1 , wherein the material of the insulating layer comprises a polymer organic insulating polymer or an inorganic insulating dielectric material. 7 . The chip packaging method according to claim 1 , wherein the insulating layer is formed by a spray coating process, a spin coating process or a chemical vapor deposition process. 8. A packaging structure, characterized in that, comprising: A substrate, the substrate comprising: a substrate and a client layer positioned on one surface of the substrate, the other surface of the client layer being the first surface of the substrate, and the opposite surface of the substrate being the first surface of the substrate On the second surface, the client layer is a material layer with several welding pads formed inside; A groove located on the second surface of the base, the groove has a first sub-groove and protruding second sub-grooves located on both sides of the first sub-groove, the first sub-groove and the second sub-groove The sub-grooves are connected, the second sub-groove exposes part of the surface of the pad, and the second sub-groove only exposes one side of the pad; an insulating layer located on the inner wall surface of the groove and the second surface of the base; a via in the pad that penetrates the insulating layer and the pad; The wiring metal layer located on the surface of the groove and the through hole; A solder resist layer located on the surface of the wiring metal layer, the solder resist layer has an opening, and the opening exposes part of the surface of the wiring metal layer; Solder balls located on the surface of the wiring metal layer within the opening. 9. The package structure according to claim 8, wherein the first sub-groove is located on the surface of the client layer between adjacent pads. 10. The package structure according to claim 8, wherein the second sub-groove comprises a first part and a second part, the first part is located on the surface of the pad, and the second part is located on the surface of the customer layer, communicating with the second part. A part and the first groove. 11 . The package structure according to claim 8 , further comprising: a substrate, the first surface of the substrate is press-bonded with the substrate. 12 . The package structure according to claim 8 , wherein the insulating layer is made of an organic polymer or an inorganic insulating dielectric material. 13 .