CN103745742A

CN103745742A - Differential floating gate DRAM (dynamic random access memory) storage unit

Info

Publication number: CN103745742A
Application number: CN201310723105.5A
Authority: CN
Inventors: 李力南; 翁宇飞
Original assignee: SUZHOU KUANWEN ELECTRONIC TECHNOLOGY Co Ltd
Current assignee: SUZHOU KUANWEN ELECTRONIC TECHNOLOGY Co Ltd
Priority date: 2013-12-25
Filing date: 2013-12-25
Publication date: 2014-04-23

Abstract

The invention discloses a differential floating gate DRAM (dynamic random access memory) storage unit, which comprises a single floating gate dynamic storage unit transistor M1 and a single floating gate dynamic storage unit transistor M2, wherein an SL (source line) control circuit module is arranged above the M1 and the M2, and a BL (bit line) control circuit module and a sensitive amplification circuit module are arranged below the M1 and the M2; the sources of the M1 and the M2 are used as two source lines SL1 and SL2 of the storage unit, the drains of the M1 and the M2 are used as two bit lines BL1 and BL2 of the storage unit, and the second-layer gates of the M1 and the M2 are used as control gates CG1 and CG2 of the storage unit. The process of the differential floating gate DRAM storage unit is the same as that of a single-transistor floating gate dynamic memory, and the design difficulty and the design cost are low; due to the adoption of a differential input scheme, a reference circuit with high complexity and sensitivity is omitted, a distinguishable current range during read operation can be widened by differential input, and the reliability of read operation is remarkably enhanced.

Description

A kind of floating gate type DRAM storage unit of difference

Technical field

The present invention relates to semiconductor memory field, what be specifically related to is a kind of floating gate type DRAM storage unit of difference.

Background technology

Along with the high speed development of integrated circuit technology, technique integrated level allows the more storer of Embedded.In-line memory is in the progressively increase of the area of System on Chip/SoC (SoC), and storer is also increasing on the impact of chip performance.Dynamic RAM (DRAM) possesses the advantages such as speed is fast, low in energy consumption, density is high, in SoC chip, is widely used.

Traditional DRAM elementary cell consists of 1T1C, and namely transistor adds the structure of an electric capacity.Because its electric capacity need to keep certain quantity of electric charge, effectively store information, cannot as MOSFET, continue minification.Industry is manufactured special construction conventionally electric capacity by digging means such as " deep trouths " dwindles the area that it takies, but along with storage density promotes, technical difficulty and the cost of electric capacity processing increase substantially.

Therefore, finding can be for the manufacture of the capacitorless part technology of DRAM always for industry.

Patent CN102969278 A has proposed to utilize floater effect transistor (FBC, Floating Body Cell) to replace the method for DRAM, has realized the DRAM storer of single tube framework.Its mechanism is the floater effect that utilizes the buffer action of oxygen buried regions in SOI device to bring, and using segregate buoyancy aid (Floating Body) as memory node, realizes one writing and writes " 0 ".Memory cell structure figure as shown in Figure 1.

In patent CN102683418 A, Tsing-Hua University has proposed a kind of FINFET dynamic RAM.Its structure as shown in Figure 2.It is in the tagma by the charge carrier of generation being stored in to transistor below, utilizes transistorized substrate bias effect, by the electric charge in modulation tagma, makes the threshold voltage of device change to reach the effect of storage information.

In recent research, researchist has proposed a kind of single tube dynamic storage unit (as shown in Figure 3) of new floating gate type.When the voltage of the add-2V of control gate CG end in storage unit, drain terminal D end adds 2V voltage, during source S suspension joint, there is BTBT (band-to-band-tunneling) in the TFET in device, electronics is injected in floating boom, is expressed as the reduction of device threshold voltage in macroscopic view, and data " 1 " are written into; When loading the voltage of 2V at CG, D end load 0V or-1V voltage, during S end suspension joint, due to CG and the direct forward voltage drop of D, the PN junction forward bias in device, thereby in floating boom, electric charge flows out toward D end, threshold voltage unchanged or slightly change are large, and we are referred to as " 0 " and are written into.When adding 2V at CG, D end adds 2V, during S end suspension joint, the cell threshold voltage of depositing " 1 " is low, shows as pipe conducting in macroscopic view, and it is high to deposit the cell threshold voltage of " 0 ", in macroscopic view, show as pipe and turn-off, we can determine by metering circuit reading current the store status of storage unit.

But because the operating voltage of device is very little in this storage unit, this power consumption for storer is advantage, but in physical storage design, operating voltage is little directly has influence on the can differentiate range very little of different operating state, particularly during read operation, between " 0 " state of storer and one state, electric current difference is very little, and in storer, our conventional difference sense amplifier carrys out reading out data.An input of difference sense amplifier meets bit line BL(Bit Line), reference circuit of another termination.The current value (or voltage) of this reference circuit must be read between storer " 0 " state and read between one state electric current (voltage).So must need very accurate sensitive reference circuit guarantee its to read function normal.Even if we have designed reference circuit very accurately, but under different service condition (PVT: technique process, voltage voltage, temperature t emperature), will inevitably there is certain fluctuation deviation in reference circuit, so just design has been proposed to higher challenge.

Therefore,, on the basis of Novel single tube floating gate type dynamic storage, we propose a kind of improved storage unit and improve the reliability and stability of its read operation.

Summary of the invention

The object of the invention is to overcome the above problem that prior art exists, a kind of floating gate type DRAM storage unit of difference is provided, improve the reliability and stability of its read operation.

For realizing above-mentioned technical purpose, reach above-mentioned technique effect, the present invention is achieved through the following technical solutions:

A kind of floating gate type DRAM storage unit of difference, comprise single tube floating boom dynamic storage cell transistor M1 and single tube floating boom dynamic storage cell transistor M2, described transistor M1 and transistor M2's is source line SL control circuit module above, below described transistor M1 and transistor M2, be bit line BL control circuit module and sensitive amplifier circuit module, the source electrode of described transistor M1 and described transistor M2 is respectively as two root line SL1 and SL2 of storage unit; The drain electrode of described transistor M1 and described transistor M2 is respectively as two bit line BL1 and the BL2 of storage unit; The second layer grid of described transistor M1 and described transistor M2 is as control gate CG1 and the CG2 of storage unit.

Described transistor M1 and transistor M2 are symmetrical, form difference type floating gate memory cell.

Described source line SL control circuit module comprises the first coding and decoding circuit, the first coding and decoding circuit is by address signal control, power supply is provided simultaneously, and described bit line BL control circuit amplification module comprises the second coding and decoding circuit, the task of described sensitive amplifier circuit module reading out data.

The invention has the beneficial effects as follows:

The present invention is on the basis of single tube floating boom dynamic storage, adopt differential configuration, two branch roads contrast input difference amplifiers while reading, have optimized and have adopted the accuracy problem of reading that reference circuit input sense amplifier brings, and have greatly improved the stability reading.

Accompanying drawing explanation

Fig. 1 is 1T FBC dynamic storage unit;

Fig. 2 is 1T FINFET DRAM cell;

Fig. 3 is Novel single tube floating gate type dynamic storage storage unit;

Fig. 4 is storage unit of the present invention.

Embodiment

Below with reference to the accompanying drawings and in conjunction with the embodiments, describe the present invention in detail.

Shown in Fig. 4, a kind of floating gate type DRAM storage unit of difference, comprise single tube floating boom dynamic storage cell transistor M1 and single tube floating boom dynamic storage cell transistor M2, described transistor M1 and transistor M2's is source line SL control circuit module above, below described transistor M1 and transistor M2, be bit line BL control circuit module and sensitive amplifier circuit module, the source electrode of described transistor M1 and described transistor M2 is respectively as two root line SL1 and SL2 of storage unit; The drain electrode of described transistor M1 and described transistor M2 is respectively as two bit line BL1 and the BL2 of storage unit; The second layer grid of described transistor M1 and described transistor M2 is as control gate CG1 and the CG2 of storage unit.

Principle of the present invention:

During programming operation, at CG1 end, add a negative voltage VN (2V), CG2 termination positive voltage VP (2V), BL1 meets VP, and BL2 is floating empty, and SL1, SL2 are floating empty.At this moment for the M1 branch road on the left side, because CG1 and BL1 have met respectively VN and VP, according to raceway groove band-to-band-tunneling principle, electronics is optionally injected the floating boom FG1 of M1, and data 1 are written into; Meanwhile, because CG2 has met VP, BL2 connects 0, the biasing of diode forward in storage tube, and electric charge in FG is constant or reduce, and data 0 are written into.At this moment we define overall difference storage architecture and are written into 0.In like manner, if CG1 applies voltage VP, CG2 meets VN, and BL1 meets 0, BL2 and meets VP, and SL1, SL2 are floating empty, and M1 is written into 0 and M2 is written into 1, and we define overall difference storage architecture and are written into 1.

During read operation, apply a voltage VP on CG1, CG2, SL1, SL2 connect 0, BL1, BL2 end and also meet VP.The pipe work of storage 1, the very large electric current of flowing through in circuit, and the pipe electric current of storage 0 is very little, two branch current I1 and I2 input sense amplifier, if I1>I2 reads 0; If I1<I2, reads 1.

The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.

Claims

1. the floating gate type DRAM storage unit of a difference, it is characterized in that: comprise single tube floating boom dynamic storage cell transistor M1 and single tube floating boom dynamic storage cell transistor M2, described transistor M1 and transistor M2's is source line SL control circuit module above, below described transistor M1 and transistor M2, be bit line BL control circuit module and sensitive amplifier circuit module, the source electrode of described transistor M1 and described transistor M2 is respectively as two root line SL1 and SL2 of storage unit; The drain electrode of described transistor M1 and described transistor M2 is respectively as two bit line BL1 and the BL2 of storage unit; The second layer grid of described transistor M1 and described transistor M2 is as control gate CG1 and the CG2 of storage unit.

2. the floating gate type DRAM storage unit of difference according to claim 1, is characterized in that: described transistor M1 and transistor M2 are symmetrical, forms difference type floating gate memory cell.

3. the floating gate type DRAM storage unit of difference according to claim 1, it is characterized in that: described source line SL control circuit module comprises the first coding and decoding circuit, the first coding and decoding circuit is by address signal control, power supply is provided simultaneously, described bit line BL control circuit amplification module comprises the second coding and decoding circuit, the task of described sensitive amplifier circuit module reading out data.