CN103744210A - Display panel - Google Patents

Abstract

The invention relates to a display panel including: a first scan line, a first data line, a first pixel, a second scan line, a switching transistor and a second pixel. The first scan line is used to provide a first scan signal; the first data line is used to provide a data signal; the first pixel is electrically coupled to the first scan line and the first data line to receive the data signal and the first scan signal. ; The second scan line is used to provide a second scan signal; the switching transistor is electrically coupled to the second scan line and is used to receive the second scan signal; the second pixel is electrically coupled to the first scan line and the switching transistor is used to receive The first scan signal; wherein the switching transistor is used to control whether the second pixel is updated according to the data signal according to the second scan signal. The present invention reduces the number of data lines in the display panel, thereby allowing the display panel to have more area for pixel display.

Description

display panel

technical field

The present invention relates to a display panel, in particular to a structure of a display panel.

Background technique

With the development of display technology, the demand for the resolution of the display panel is also increasing day by day. Correspondingly, the number of pixels in the same unit area of the display panel also increases accordingly. The number of data lines for providing pixel data signals must also be increased accordingly.

In order to provide space for the arrangement of these driving circuits, the area actually used for displaying images in the display panel is reduced accordingly, resulting in problems such as reduced luminous efficiency of pixels and insufficient brightness of the panel.

Contents of the invention

In order to overcome the defects of the prior art, an embodiment of the present invention provides a display panel, which has fewer data lines under the same number of pixels, thereby reducing the area required for the data line arrangement and leaving more Space is used to display images as pixels.

The above display panel includes: a first scan line, a first data line, a first pixel, a second scan line, a switching transistor and a second pixel. The first scan line is used to provide a first scan signal; the first data line is used to provide a data signal; the first pixel is electrically coupled to the first scan line and the first data line for receiving the data signal and the first scan signal The second scan line is used to provide the second scan signal; the switch transistor is electrically coupled to the second scan line and used to receive the second scan signal; the second pixel is electrically coupled to the first scan line and the switch transistor is used to receive the first scan line A scanning signal; wherein the switching transistor is used to control whether the second pixel is updated according to the data signal according to the second scanning signal.

Optionally, wherein the switching transistor is used to control whether the second pixel is updated according to the data signal according to the second scanning signal: the switching transistor is used to control whether the data signal is transmitted to the second pixel through the first pixel and the switching transistor in sequence according to the second scanning signal two pixels.

Optionally, the switching transistor has a first terminal, a second terminal and a gate terminal, the first terminal of the switching transistor is electrically coupled to the first pixel, the second terminal of the switching transistor is electrically coupled to the second pixel, and the gate of the switching transistor The terminal is electrically coupled to the second scan line for receiving the second scan signal.

Optionally, the first pixel includes a first pixel capacitor and a first transistor. The first transistor has a first terminal, a second terminal and a gate terminal, the first terminal of the first transistor is electrically coupled to the first data line for receiving data signals, and the gate terminal of the first transistor is electrically coupled to the first The scan line is used to receive the first scan signal, and the second end of the first transistor is electrically coupled to the first pixel capacitor and the first end of the switching transistor.

Optionally, the second pixel includes a second pixel capacitor and a second transistor. The second transistor has a first terminal, a second terminal and a gate terminal, the first terminal of the second transistor is electrically coupled to the second terminal of the switching transistor, the second terminal of the second transistor is electrically coupled to the second pixel capacitor, and the second transistor is electrically coupled to the second pixel capacitor. The gate terminals of the two transistors are electrically coupled to the first scan line for receiving the first scan signal.

Optionally, the first scan signal has a first enable period in a frame period, and when the first scan signal is enabled in the first enable period, the second scan signal has a second enable period and a disable period.

Furthermore, the switching transistor, the first transistor and the second transistor are also used for conducting in the second enabling period, and updating the potentials stored in the first pixel capacitor and the second pixel capacitor according to the data signal.

Furthermore, the first transistor is also used to be turned on during the disabled period, so as to update the potential of the first pixel capacitor according to the data signal, and the switching transistor is also used to be turned off during the disabled period.

Furthermore, the second transistor is also used for turning on during the disabled period.

Optionally, the second scanning signal also has a third enabling period in the frame period, and in the third enabling period, the first scanning signal is disabled.

Optionally, the potentials of the data signal in the second enabling period and the disabling period are different and the display panel is a liquid crystal display panel.

In the embodiment of the present invention, by switching the transistor, it is determined whether the second pixel that receives the signal of the same first data line as the first pixel is updated according to the data signal of the first data line, and then the first data is time-multiplexed. One line can drive two pixels, so the number of data lines in the display panel is reduced, so that the display panel can have more area for the pixels to display images.

Description of drawings

FIG. 1 is a schematic diagram of an equivalent circuit of a first embodiment of a display panel of the present invention;

Fig. 2 is the driving waveform diagram of the display of Fig. 1;

3 is a schematic diagram of an equivalent circuit of the second embodiment of the display panel of the present invention;

FIG. 4 is a schematic diagram of an equivalent circuit of a third embodiment of the display panel of the present invention.

Wherein, the reference signs are explained as follows:

100, 300, 400 display panel

110, 112, 114 scan lines

S1～S3 scan signal

120, 122, 124 data lines

D1～D3 Data signal

130, 132 first pixel

134 first transistor

136 first pixel capacitance

150 switching transistors

160, 162 second pixel

164 second transistor

166 Second pixel capacitance

P110 First enabling period

P112 Second enabling period

P114 Disabled period

P210 Third enabling period

D12, D14 voltage

FR frame cycle

Detailed ways

Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings, but the provided embodiments are not intended to limit the scope of the present invention.

FIG. 1 is a schematic diagram of an equivalent circuit of a first embodiment of a display panel of the present invention. The display panel 100 includes a plurality of scan lines 110 , 112 , 114 ; a plurality of data lines 120 , 122 , 124 ; a plurality of first pixels 130 , 132 ; a plurality of switching transistors 150 , 152 and a plurality of second pixels 160 , 162 .

The scan lines 110, 112, 114 are respectively used to provide the corresponding scan signals S1-S3, the data lines 120, 122, 124 are respectively used to provide the corresponding data signals D1-D3, and the first pixels 130, 132 are electrically coupled to the corresponding The scan lines 110, 112 and the data lines 120, 124 are used to receive corresponding scan signals S1, S2 and data signals D1, D3. The second pixels 160, 162 are electrically coupled to the corresponding scan lines 110, 112 for receiving corresponding scan signals S1, S2. The switching transistors 150 , 152 are electrically coupled between the corresponding first pixels 130 , 132 and the second pixels 160 , 162 , and are electrically coupled to the corresponding scan lines 112 , 114 .

Since the structure, function, and operation of the display panel 100 have the characteristics of repeated cycles, only the first scan line 110, the second scan line 112, the first data line 120, the first pixel 130, and the switching transistor of the display panel 100 are used below. 150 and the second pixel 160 for a further description. And FIG. 1 only shows a part of pixels of the display panel 100 .

The first scan line 110 is used to provide the first scan signal S1, and when the first scan signal S1 is enabled, it can start the refresh action of the electrically coupled pixels; the first data line 120 is used to provide the data signal D1, and the data signal D1 is based on The gray scale required by a pixel to adjust the content of its signal. The first pixel 130 is electrically coupled to the first scan line 110 and the first data line 120 for receiving the data signal D1 through the first data line 120 and for receiving the first scan signal S1 through the first scan line 110 . The second scan line 112 is used to provide the second scan signal S2; the switch transistor 150 is electrically coupled to the first pixel 130, the second pixel 160 and the second scan line 112, and is used for receiving the second scan signal S2 from the second scan line 112 Signal S2 ; the second pixel 160 is electrically coupled to the first scan line 110 and the switching transistor 150 , and the second pixel 160 is used for receiving the first scan signal S1 from the first scan line 110 .

Since the switching transistor 150 is electrically coupled between the first pixel 130 and the second pixel 160 , the switching transistor 150 can determine whether the conduction path between the first pixel 130 and the second pixel 160 is turned off or turned on. Therefore, when the first pixel receives the data signal D1, it can be determined whether the data signal D1 can continue to be transmitted to the second pixel 160 according to whether the switching transistor 150 is turned on or off. In short, the switch transistor 150 can be used to control the switch transistor 150 to be turned on or off according to the second scan signal S2, thereby controlling whether the second pixel 160 is updated according to the data signal D1. In other words, the switching transistor 150 is used to control whether the data signal D1 is sequentially transmitted to the second pixel 160 via the first pixel 130 and the switching transistor 150 according to the second scan signal S2 .

Further, the switching transistor 150 has a first terminal (one of the transistor drain or source), a second terminal (the other of the transistor drain or source) and a gate terminal, and the first terminal of the switching transistor 150 is electrically The second terminal of the switch transistor 150 is electrically coupled to the second pixel 160 , and the gate terminal of the switch transistor 150 is electrically coupled to the second scan line 112 for receiving the second scan signal S2 .

Besides, in a specific implementation manner, the first pixel 130 includes a first pixel capacitor 136 and a first transistor 134 . The first transistor 134 has a first terminal, a second terminal and a gate terminal. The first terminal of the first transistor 134 is electrically coupled to the first data line 120 for receiving the data signal D1. The gate terminal of the first transistor 134 is electrically connected to the first data line 120. is electrically coupled to the first scan line 110 for receiving the first scan signal S1 to determine whether the first transistor 134 is turned on or off, and the second end of the first transistor 134 is electrically coupled to the first pixel capacitor 136 and the switching transistor The first end of 150 is used to transmit the data signal D1 to the first pixel capacitor 136 and the switching transistor 150 to control the gray scale of the first pixel 130 .

Furthermore, in a specific implementation manner, the second pixel 160 includes a second pixel capacitor 166 and a second transistor 164 . The second transistor 164 has a first terminal, a second terminal and a gate terminal. The first terminal of the second transistor 164 is electrically coupled to the second terminal of the switching transistor 150 for receiving the data signal D1 transmitted through the switching transistor 150. The second terminal of the second transistor 164 is electrically coupled to the second pixel capacitor 166 for transmitting the data signal D1 to the second pixel capacitor 166, thereby changing the gray scale of the second pixel 160. The gate terminal of the second transistor 164 is electrically connected to the second pixel capacitor 166. Sexually coupled to the first scan line 110 for receiving the first scan signal S1 for determining whether the second transistor 164 is turned on or off.

The connection relationship of the display panel 100 is roughly introduced as above. FIG. 2 is a driving waveform diagram of the display in FIG. 1 . 2 is a waveform diagram of the scanning signals S1 - SN and a waveform diagram of the data signal D1 from top to bottom, SN is the scanning signal of the Nth row of the display panel 100 , and the horizontal axis is the time axis. The high level H indicates that the scanning signal is enabled, and the low level L indicates that the scanning signal is disabled.

The operation of the display panel 100 will be described below with reference to FIG. 2 and FIG. 1 . Similarly, since the structure, function, and operation of the display panel 100 have the characteristics of repeated cycles, only the first scan line 110, the second scan line 112, the first data line 120, and the first pixel 130 of the display panel 100 are used below. , the switching transistor 150 and the second pixel 160 are further described.

In a frame period (Frame Period) FR, the first scan signal S1 has a first enabling period P110. In the first enable period P110 , in response to the first scan signal S1 , the first transistor 134 and the second transistor 164 are turned on. In addition, when the first scan signal S1 is enabled in the first enable period P110 , the second scan signal S2 has a second enable period P112 and a disable period P114 . That is to say, when the first scan signal S1 is enabled, the second scan signal S2 is first enabled and then disabled. In addition, since the switching transistor 150 is controlled by the second scanning signal S2, the switching transistor 150 is turned on during the second enabling period P112, and is turned off during the disabling period P114. . It is supplemented that the second enabling period P112 does not need to start simultaneously with the first enabling period P110 , and the first enabling period P110 does not need to end simultaneously with the disabling period P114 .

1, in the first enabling period P110 and the second enabling period P112, since the first transistor 134, the switching transistor 150 and the second transistor 164 are all in the on state, the first Both the pixel 130 and the second pixel 160 can update the displayed gray scale. But at this time, the data signal D1 provides the voltage D12 corresponding to the gray scale required by the second pixel 160 .

Specifically, in the first enabling period P110 and the second enabling period P112, by simultaneously turning on the first transistor 134, the switching transistor 150, and the second transistor 164, the current voltage D12 of the data signal D1 can be sequentially passed through the first The transistor 134, the switching transistor 150, and the second crystal 164 are written into the second pixel capacitor 166, thereby updating the gray scale of the second pixel 160. In other words, the voltage stored in the second pixel capacitor 166 is in the second enabling period P112 according to the data signal D1 The voltage D12 at that time changes. It is supplemented that those skilled in the art should know that the voltage D12 may have non-ideal voltage drop during transmission through multiple transistors.

In the first enabling period P110 and the disabling period P114 , the first transistor 134 and the second transistor 164 are still in the on state, but the switch transistor 150 is switched from the on state to the off state. Correspondingly, during this period, the data signal D1 provides the voltage D14 corresponding to the gray scale required by the first pixel 130. Since the switching transistor 150 has been switched to an off state, the voltage D14 will only be written through the first transistor 134 The first pixel capacitor 130 is used to update the gray scale of the first pixel. In other words, during the disabled period P114, the first pixel capacitance 130 changes according to the voltage D14 of the data signal D1 at that time.

In detail, the switch transistor 150 , the first transistor 134 and the second transistor 164 are used to conduct during the second enabling period P112 and update the potentials stored in the first pixel capacitor 130 and the second pixel capacitor 160 according to the data signal D1 . In addition, the first transistor 134 is also used to be turned on during the disabled period P114 to update the potential of the first pixel capacitor 130 according to the data signal D1, and the switching transistor is also used to be turned off during the disabled period P114 to prevent the updated second The pixel capacitor 160 receives an erroneous signal.

After the disable period P114, the second scan signal S2 also has a third enable period P210 in the frame period FR, and in the third enable period P210, the first scan signal S1 is disabled. Since the second scanning signal S2 not only drives the switching transistor 150, but also drives the corresponding first and second transistors in the next row of pixels, the pixels in the next row of pixels in the third enabling period P210 repeatedly perform the above-mentioned pixel updating. action. Since the first scan signal S1 is disabled during the third enabling period P210, although the switching transistor 150 is turned on, it does not allow the data signal D1 required by the next row of pixels to be transmitted to the pixels of this row.

FIG. 3 is a schematic diagram of an equivalent circuit of a second embodiment of the display panel of the present invention. The difference between the display panel 300 and the display panel 100 is that the first end of the switching transistor 150 is not electrically coupled to the second end of the first transistor 134, but (directly) electrically coupled to the first data line 120, Therefore, the switching transistor 150 can directly receive the data signal D1 from the first data line 120 , and other pixels of the display panel 300 also have corresponding settings. In addition, the display panel 300 is the same as the display panel 100 in terms of equivalent circuits, so details are not repeated here.

Please refer to Figure 2 and Figure 3 together. The display 300 can also be driven using the driving waveforms shown in FIG. 2 . In the second enabling period P112 in the first enabling period P110, since the first scanning signal S1 and the second scanning signal S2 are both enabled, the gray scales of the first pixel 130 and the second pixel 160 are both according to the data The voltage D12 provided by the signal D1 is updated, but preferably, what the data signal D1 provides at this time is the voltage D12 corresponding to the gray scale required by the second pixel 160 . Then comes the disabled period P114 in the first enabled period P110, because the first transistor 134 and the second transistor 164 are still in the on state at this time, but the switching transistor 150 is switched from the on state to the off state . Correspondingly, during this period, the data signal D1 provides the voltage D14 corresponding to the gray scale required by the first pixel 130. Since the switching transistor 150 has been switched to an off state, the voltage D14 will only be written through the first transistor 134 The first pixel capacitor 136, thereby updating the gray scale of the first pixel.

FIG. 4 is a schematic diagram of an equivalent circuit of a third embodiment of the display panel of the present invention. The difference between the display panel 400 and the display panel 100 is that the first end of the second transistor 164 is electrically coupled to the first data line 120 , the second end of the second transistor 164 is electrically coupled to the first end of the switching transistor 150 , The second terminal of the switching transistor 150 is electrically coupled to the second pixel capacitor 166 , and other pixels of the display panel 300 also have corresponding settings. In this embodiment, the second transistor 164 can directly receive the data signal D1 provided by the first data line 120 , but whether the data signal D1 can be provided to the second pixel capacitor 166 to achieve the purpose of updating the second pixel 160 , It is affected by whether the switching transistor 150 is turned on or not.

The display panel 400 can also be driven with the driving waveform shown in FIG. 2 , please refer to FIG. 2 together. During the disabled period P114 , the switch transistor 150 is controlled by the second scan signal S2 to be turned off, so the data signal D1 cannot be used to update the second pixel capacitor 166 after passing through the second transistor 164 . In the second enabling period P112, since the switching transistor 150 is turned on under the control of the second scanning signal S2, the voltage stored in the second pixel capacitor 166 can be updated according to the data signal D1. In addition, the voltage D12 of the data signal D1 is the voltage D12 corresponding to the gray scale required by the second pixel 160, the voltage D14 of the data signal D1 is the voltage D14 corresponding to the gray scale required by the first pixel 130, and other The driving principle is similar to that of the above two display panels 100 and 300 , so it will not be repeated here.

In addition, if the display panels 100, 300, and 400 are liquid crystal display panels, in an application, the first pixel 130 and the second pixel 160 can be used as two sub-pixels of a main pixel, that is, The gray scale displayed by the main pixel is determined by the two sub-pixels, and the potentials of the data signals D12 and D14 of the data signal D1 in the first enable period p110 and the disable period P114 can be different, in other words, different gray levels can be written respectively. Level values are assigned to the first pixel 130 and the second pixel 160 . Since the liquid crystal molecules are in different gray scales, the brightness of large angles compensates each other, so the viewing angle of the display can be increased.

In summary, the embodiment of the present invention determines whether the second pixel 160 is updated according to the data signal of the first data line 120 by switching the transistor 150, and the first pixel 130 also receives the data signal D1 provided by the first data line 120, Furthermore, by means of time multiplexing, the first data line 120 can drive two pixels, thus reducing the number of data lines in the display panel 100, and further enabling the display panel 100 to have more area for pixel display screens. use.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (12)

1. a display panel, comprising:

One first sweep trace, in order to provide one first sweep signal;

One first data line, in order to provide a data-signal;

One first pixel, this first sweep trace of electric property coupling and this first data line, in order to receive this data-signal and this first sweep signal;

One second sweep trace, in order to provide one second sweep signal;

One switching transistor, this second sweep trace of electric property coupling, and in order to receive this second sweep signal; And

One second pixel, this first sweep trace of electric property coupling and this switching transistor, in order to receive this first sweep signal;

Wherein whether this switching transistor upgrades according to this data-signal in order to control this second pixel according to this second sweep signal.

2. display panel as claimed in claim 1, wherein whether this switching transistor is updated to according to this data-signal in order to control this second pixel according to this second sweep signal: whether this switching transistor sequentially passes to this second pixel via this first pixel and this switching transistor in order to control this data-signal according to this second sweep signal.

3. display panel as claimed in claim 1, this switching transistor has a first end, one second end and a gate terminal, this first pixel of the first end electric property coupling of this switching transistor, this second pixel of the second end electric property coupling of this switching transistor, this second sweep trace of the gate terminal electric property coupling of this switching transistor, in order to receive this second sweep signal.

4. display panel as claimed in claim 3, wherein this first pixel comprises:

One first pixel capacitance; And

One the first transistor, there is a first end, one second end and a gate terminal, this first data line of the first end electric property coupling of this first transistor, in order to receive this data-signal, this first sweep trace of the gate terminal electric property coupling of this first transistor, in order to receive this first sweep signal, this first pixel capacitance of the second end electric property coupling of this first transistor and the first end of this switching transistor.

5. display panel as claimed in claim 4, wherein this second pixel comprises:

One second pixel capacitance; And

One transistor seconds, there is a first end, one second end and a gate terminal, the second end of this switching transistor of first end electric property coupling of this transistor seconds, this second pixel capacitance of the second end electric property coupling of this transistor seconds, this first sweep trace of the gate terminal electric property coupling of this transistor seconds, in order to receive this first sweep signal.

6. display panel as claimed in claim 1, wherein this switching transistor has a first end, one second end and a gate terminal, this first data line of the first end electric property coupling of this switching transistor, this second pixel of the second end electric property coupling of this switching transistor, this second sweep trace of the gate terminal electric property coupling of this switching transistor, in order to receive this second sweep signal.

7. display panel as claimed in claim 1, wherein

This switching transistor has a first end, one second end and a gate terminal, a little these second sweep traces of the electrical coupling of gate terminal of this switching transistor; And

This second pixel comprises:

One second pixel capacitance, the second end of this switching transistor of electric property coupling; And

One transistor seconds, there is a first end, one second end and a gate terminal, this first data line of the first end electric property coupling of this transistor seconds, the first end of second this switching transistor of end electric property coupling of this transistor seconds, this first sweep trace of the gate terminal electric property coupling of this transistor seconds, in order to receive this first sweep signal.

8. the display panel as described in claim 1 to 7 any one, this first sweep signal had for one first activation period in a picture cycle, in this first sweep signal, during in this first activation period activation, this second sweep signal has one second activation period and a forbidden energy period.

9. display panel as claimed in claim 8, wherein this switching transistor, this first transistor and this transistor seconds be also in order in this second activation period conducting, and according to this data-signal, upgrade the current potential of this first pixel capacitance and the storage of this second pixel capacitance.

10. display panel as claimed in claim 8, wherein this first transistor is also in order in this forbidden energy period conducting, and to upgrade the current potential of this first pixel capacitance according to this data-signal, and this switching transistor is also in order in this forbidden energy period cut-off.

11. display panels as claimed in claim 8, wherein this second sweep signal also had for one the 3rd activation period in this picture cycle, and in the 3rd activation period, this first sweep signal is forbidden energy.

12. display panels as claimed in claim 8, wherein at the data-signal current potential of this second activation period and this forbidden energy period, different and this display panel is display panels to this data-signal.

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