CN103715956B - A kind of two level three-phase space vector pulse-width modulation and SVPWM optimization method thereof - Google Patents

Abstract

The invention discloses a two-level three-phase space vector pulse width modulator and its SVPWM optimization method. Aiming at the influence of dead time and narrow pulse width limitation, the actual linear modulation area is expanded, the overmodulation algorithm is optimized, and the method is simple and convenient. The linearization process of the overmodulation region is realized effectively. The two-level three-phase space vector pulse width modulator includes a given reference voltage correction module, a voltage coordinate transformation module, a voltage interval calculation module, a vector time calculation module, a modulation algorithm optimization module, and a PWM comparison point time calculation module Six modules. The invention realizes the full utilization of the busbar voltage with the most convenient algorithm, improves the linearity of the output fundamental wave voltage, and reduces the total harmonic distortion of the output voltage.

Description

A two-level three-phase space vector pulse width modulator and its SVPWM optimization method

technical field

The invention relates to the technical field of AC motor control, in particular to a two-level three-phase space vector pulse width modulator and its SVPWM optimization method considering dead zone and narrow pulse width limitation.

Background technique

Pulse width modulation (PWM, pulsewidthmodulation) is an important part of the motor control system. Due to the characteristics of high voltage utilization, low voltage harmonics and easy digital implementation of vector pulse width modulation (SVPWM, spacevectorPWM) technology, it is widely used in motor vector control.

In the two-level three-phase inverter system, the 8 states of the switching tube can generate 6 basic voltage vectors v ₁ /v ₂ /…/v ₆ and 2 zero vectors v ₀ /v ₇ , the basic voltage vectors constitute The regular hexagonal area (including the boundary) is the range (voltage space) that the output voltage can reach. Any voltage vector in the voltage space can be synthesized by two adjacent basic vectors and a zero vector, which is the SVPWM technology.

Set the given reference voltage U _r (U _r ∠θ) to the maximum phase voltage (the radius of the inscribed circle of the regular hexagon formed by the basic voltage vector) is the standard per unitization, and the per unitization result u _r (u _r ∠θ)(θ∈[0,2π)), u _r is recorded as the modulation degree, that is Then, the maximum output voltage is the basic voltage vector (amplitude is ), the modulation degree is When u _r ≤ 1, the trajectory of the output voltage vector u _r is within the regular hexagon (not exceeding the inscribed circle), and the circular flux linkage can be output normally, which is the linear modulation area; when , the output voltage vector u _r has part of the trajectory beyond the regular hexagonal range (beyond the inscribed circle), and the circular flux linkage cannot be output normally, which is an over-modulation area.

A variety of over-modulation methods have been proposed so far in order to reduce the harmonics in the over-modulation area, reduce the amount of over-modulation calculations, and improve the linearity of the over-modulation area.

As shown in Figure 5a, the voltage space can be divided into six regions S1/S2/S3/S4/S5/S6 by the basic vector as the boundary, and the voltage vector u _r in each region can pass through the forward adjacent basic voltage vector v _k , backward adjacent basic voltage vector v _k+1 and zero vector v _z (v ₀ or v ₇ ), namely

$\left\{\begin{array}{c}{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; t</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; k</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; t</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}}\\ \mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; t</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; t</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; t</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}\end{array}\right.$

Where T _s , T ₁ , T ₂ and T ₀ are PWM period, forward adjacent basic vector time, backward adjacent basic vector time and zero vector time respectively, t ₁ =T ₁ /T _s , t ₂ =T ₂ /T _s , t ₀ =T ₀ /T _s . The implementation of SVPWM generally adopts a seven-segment symmetrical modulation method, as shown in Figure 5b. Among them, T _a , T _b and T _c are the PWM comparison point time (high level conduction) of phase A, phase B and phase C of the upper bridge arm respectively.

However, in the actual application of the two-level three-phase inverter system, the upper and lower bridge arm complementary PWM output mode is generally adopted. In order to ensure that the upper and lower tubes will not be directly connected, an appropriate dead time must be inserted; at the same time, in order to reduce switching losses, usually Limits the minimum output pulse width. Due to the influence of dead time and narrow pulse width limitation, the PWM output duty cycle is limited and can only work in the range of [t _lim ,1-t _lim ]∪(0)∪(1), that is, in [t _lim , 1-t _lim ] is continuously adjustable or constant high level or constant low level, but cannot be adjusted between (0,t _lim ) and (1-t _lim ,1), where t _lim is the dead time and the sum of the narrow pulse width limit time. The limitation of dead time and narrow pulse width narrows the actual voltage space range that can be reached, which makes the actual linear modulation area narrow, and the performance of the currently proposed overmodulation algorithm is greatly reduced.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies in the prior art, provide a kind of two-level three-phase space vector pulse width modulator and its SVPWM optimization method considering dead zone and narrow pulse width limitation, expand the actual linear modulation area, optimize The overmodulation algorithm is adopted, and the linearization processing of the overmodulation area is easily realized.

In order to achieve the above object, the two-level three-phase space vector pulse width modulator of the technical solution provided by the present invention includes:

The given reference voltage correction module does not change the voltage phase angle according to the given reference voltage u _r (u _r ∠θ), when ur>1, according to Correct the voltage amplitude to obtain the corrected reference voltage u _m (u _m ∠θ);

The voltage coordinate transformation module is used to transform the corrected reference voltage u _m (u _m ∠θ) from the polar coordinate representation to the two-phase stationary coordinate system u _m (u _a ,u _β ), that is, u _α =u _m cosθ and u _β = u _m sin θ;

The voltage interval calculation module is used to calculate the interval position in the voltage space corresponding to u _m in the two-phase stationary coordinate system, that is, the voltage interval number sector;

The vector time calculation module obtains the adjacent basic vector time t ₁ , t ₂ and the zero vector time t ₀ =1-t ₁ according to the two-phase stationary coordinate system u _m (u _a , u _β ) and the corresponding voltage interval number sector -t ₂ ;

Modulation algorithm optimization module, according to the adjacent basic vector time t ₁ , t ₂ and zero vector time t ₀ , according to the optimized modulation algorithm, calculate the optimized adjacent basic vector time t ₁ ', t ₂ ' and zero vector time Vector time t ₀ ′, and the first trigger PWM comparison point time τ ₀ ;

PWM comparison point time calculation module, according to the t ₁ ′, t ₂ ′, τ ₀ and the corresponding voltage interval number sector to obtain the PWM comparison point time under the high level conduction of the upper bridge arm of each phase of A phase, B phase and C phase T _a , T _b , T _c .

The optimized modulation algorithm comprises the following steps:

1) If t ₀ ≥ 2t _lim , t ₁ ′=t ₁ , t ₂ ′=t ₂ , t ₀ ′=t ₀ ;

2) If t _lim ≤t ₀ <2t _lim , t ₁ ′=t ₁ , t ₂ ′=t ₂ , t ₀ ′=t ₀ ; when t ₁ >t ₂ , τ ₀ =0, otherwise τ ₀ = t ₀ ';

3) When t _lim /2≤t ₀ <t _lim , use the proportional compression method, t ₀ ′=t _lim ; when t ₁ >t ₂ , τ ₀ =0, otherwise τ ₀ =t ₀ ′;

4) When t ₀ <t _lim /2, the output voltage works on the boundary of the regular hexagon in the voltage space, that is, t ₀ ′=0, τ ₀ =0. At this time, the calculation methods of t ₁ ′ and t ₂ ′ are as follows:

4.1) When 0≤t ₀ <t _lim /2 or when t ₀ <0∩t ₁ +t ₂ /2<1∩t ₁ /2+t ₂ <1, the proportional scaling method is adopted, namely When t ₁ ′<t _lim , t ₁ ′=0, t ₂ ′=1; when t ₂ ′<t _lim , t ₁ ′=1, t ₂ ′=0;

4.2) When t ₁ ≥t ₂ ∩t ₁ +t ₂ /2≥1, output the forward basic vector v _k , that is, t ₁ ′=1, t ₂ ′=0;

4.3) When t ₁ <t ₂ ∩t ₁ /2+t ₂ ≥1, output the backward basic vector v _k+1 , that is, t ₁ ′=0, t ₂ ′=1;

Wherein, the t _lim is the sum of the dead time and the narrow pulse width limit time.

The SVPWM optimization method of the two-level three-phase space vector pulse width modulator in the present invention is as follows: if t _{0 ≥ 2t lim} , adopt the seven-segment SVPWM _; five-segment PWM; if t ₀ <t _lim , convert the voltage vector to DPWM1, three-segment PWM or one-segment PWM voltage space; among them,

The t _lim is the sum of the dead time and the narrow pulse width limit time; there is no constant level in the seven-segment SVPWM, and there are two duty cycle limits of τ ₀ and τ ₇ ; in the DPWM1, $\left\{\begin{array}{cc}{\mathrm{\&tau;}}_0=0,{\mathrm{\&tau;}}_7=t_0,& t_1\&Greater\; Equal;t_2\\ {\mathrm{\&tau;}}_0=t_0,{\mathrm{\&tau;}}_7=0,& el\mathrm{the\; s}e\end{array}\right.,$ That is, a certain phase is at a constant level, and there is only a duty ratio limit of τ0 or _τ7 ; in the three _- stage PWM, a certain two phases are at a constant level, and only the voltage of the other phase can be adjusted, and the actual voltage space is only The non-continuous boundary of the regular hexagon; the one-stage PWM means that the three phases are all at a constant level, and the actual voltage can only work on the basic vector and zero vector;

Due to the limitation of dead time and narrow pulse width, in the actual overmodulation area, some areas cannot be directly reached, so an optimized overmodulation method needs to be used for processing, including the following steps:

1) Modify the given reference voltage so that the original given reference voltage range with the corrected given reference voltage range Correspondence, that is, the mapping relationship between u _r and u _m is established: the phase angle remains unchanged; when (1-t _lim )<u _r ≤1, the amplitude remains unchanged, that is, u _m = u _r ; when When , the amplitude is corrected linearly, that is, $u_m=(\frac{2}{\sqrt{3}}+1)(u_r-1)+1\&Element;(1,4/3\&rsqb;;$

2) The modified given reference voltage u _m is modulated according to the optimized modulation algorithm to obtain the actual output voltage u _p , including the following steps:

2.1) When t ₀ ≥t _lim , directly output u _m , that is, u _p = _um ;

2.2) When t _lim /2≤t ₀ <t _lim , process u _m according to the proportional compression method to get u _p , namely $\begin{array}{cc}{t}_1^{\&prime;}=\frac{t_1}{t_1+t_2}\&Center\; Dot;(1-t_{\lim }),& t_2^{\&prime;}=\frac{t_2}{t_1+t_2}\&CenterDot;(1-t_{\lim })\end{array},$ t ₀ ′=t _lim ;

2.3) When t ₀ <t _lim /2, as follows:

2.3.1) When 0≤t ₀ <t _lim /2, process u _m according to the proportional stretching method to get u _p , namely $t_2^{\&prime;}=\frac{t_2}{t_1+t_2},$ t ₀ '=0;

2.3.2) When t ₀ <0∩t ₁ +t ₂ /2<1∩t ₁ /2+t ₂ <1, process u _m according to the proportional compression method to get u _p , namely $\begin{array}{cc}{t}_1^{\&prime;}=\frac{t_1}{t_1+t_2},& t_2^{\&prime;}=\frac{t_2}{t_1+t_2}\end{array},$ t ₀ '=0;

2.3.3) When t ₁ ≥t ₂ ∩t ₁ +t ₂ /2≥1, output the forward basic vector v _k ;

2.3.4) When t ₁ <t ₂ ∩t ₁ /2+t ₂ ≥1, output the backward basic vector v _k+1 ;

2.3.5) The operating point that cannot be reached on the boundary of the regular hexagon in the voltage space after the proportional stretching and compression is replaced by the adjacent basic voltage vector v _k or v _k+1 .

Compared with the prior art, the present invention has the following advantages and beneficial effects:

1. The actual linear modulation area is expanded. Due to the limitation of dead time and narrow pulse width, the linear modulation area of the seven-segment SVPWM loses 2t _lim , that is, the actual linear modulation area is u _r ∈ [0,(1-2t _lim )], and after adopting the present invention, the actual linear modulation area can be extended to u _r ∈ [0,(1-t _lim )];

2. Using the linear mapping method, the linearization processing of the overmodulation area is easily realized;

3. The over-modulation algorithm is optimized, and the modulation algorithms of the new actual linear modulation area and the over-modulation area are comprehensively processed, which simplifies the modulation operation and is convenient for engineering implementation;

4. Realize the full utilization of the bus voltage, reduce the difference between the output voltage and the reference voltage, reduce the harmonics of the output voltage, and improve the linearity of the output fundamental voltage relative to the reference voltage.

Description of drawings

Fig. 1 is a structural block diagram of the two-level three-phase space vector pulse width modulator of the present invention.

Fig. 2 is a flow chart of the optimized modulation algorithm of the present invention.

Figure 3a is the actual voltage space diagram of the seven-segment SVPWM.

Fig. 3b is the actual voltage space diagram of the present invention.

Fig. 4a is a schematic diagram of the trajectory of the output voltage when t _lim /2≤t ₀ <t _lim in the overmodulation method of the present invention.

Fig. 4b is a schematic diagram of the trajectory of the output voltage when 0≤t ₀ <t _lim /2 in the overmodulation method of the present invention.

FIG. 4c is a schematic diagram of the trajectory of the output voltage when t ₀ <0∩t ₁ +t ₂ /2<1∩t ₁ /2+t ₂ <1 in the overmodulation method of the present invention.

Figure 4d is the trajectory of the output voltage when t ₁ ≥ t ₂ ∩ t ₁ + t ₂ /2 ≥ 1 or t ₁ < t ₂ ∩ t ₁ /2 + t ₂ ≥ 1 in the overmodulation method of the present invention schematic diagram.

Fig. 5a is a voltage space partition diagram in the background technology.

Fig. 5b is the output diagram of the PWM duty cycle of the seven-segment SVPWM.

detailed description

The present invention will be further described below in conjunction with specific examples.

This embodiment discloses a two-level three-phase space vector pulse width modulator and its SVPWM optimization method considering dead zone and narrow pulse width limitation, taking into account the influence of dead zone time and narrow pulse width limitation, the most convenient The method realizes the full utilization of the bus voltage, improves the linearity of the output fundamental voltage relative to the reference voltage, and reduces the total harmonic distortion of the output voltage.

As shown in Figure 1, the two-level three-phase space vector pulse width modulator described in this embodiment includes a given reference voltage correction module 1, a voltage coordinate transformation module 2, a voltage interval calculation module 3, and a vector time calculation module 4. Modulation algorithm optimization module 5. PWM comparison point time calculation module 6, wherein,

The given reference voltage correction module 1, according to the given reference voltage u _r (u _r ∠θ), does not change the voltage phase angle, corrects the voltage amplitude according to the following formula (1), and obtains the corrected reference voltage u _m ( u _m ∠θ);

${\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}}<span\; class="notranslate">\; =</span>\left\{\begin{array}{cc}{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}<span\; class="notranslate">\; ,</span>& {\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}<span\; class="notranslate">\; \&le;</span>\mathrm{<span\; class="notranslate">\; 1</span>}\\ <span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}}{\sqrt{\mathrm{<span\; class="notranslate">\; 3</span>}}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; ,</span>& {\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}<span\; class="notranslate">\; ></span>\mathrm{<span\; class="notranslate">\; 1</span>}\end{array}\right.<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

The voltage coordinate transformation module 2 transforms the corrected reference voltage u _m (u _m ∠θ) from a polar coordinate representation to a two-phase stationary coordinate system u _m (u _a , u _β ), as shown in the following formula (2): Show:

$\left\{\begin{array}{c}{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; \&alpha;</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}}\mathrm{<span\; class="notranslate">\; cos</span>}\mathrm{<span\; class="notranslate">\; \&theta;</span>}\\ {\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; \&beta;</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}}\mathrm{<span\; class="notranslate">\; sin</span>}\mathrm{<span\; class="notranslate">\; \&theta;</span>}\end{array}\right.<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

The voltage interval calculation module 3, according to u _m (u _a , u _β ) in the two-phase stationary coordinate system, calculates that u _m corresponds to the interval position in the voltage space, that is, the interval number sector, and the interval number sector=4c +2b+a; define intermediate variables V _ref1 , V _ref2 , and V _ref3 as shown in formula (3):

V _ref1 =u _β

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}\mathrm{<span\; class="notranslate">\; e</span>}\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; (</span>\sqrt{\mathrm{<span\; class="notranslate">\; 3</span>}}{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; \&alpha;</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; \&beta;</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}\mathrm{<span\; class="notranslate">\; e</span>}\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; (</span><span\; class="notranslate">\; -</span>\sqrt{\mathrm{<span\; class="notranslate">\; 3</span>}}{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; \&alpha;</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; \&beta;</span>}}<span\; class="notranslate">\; )</span>$

If V _ref1 >0, then a=1, otherwise, a=0; if V _ref2 >0, then b=1, otherwise, b=0; if V _ref3 >0, then c=1, otherwise, c=0 ;

The vector time calculation module 4, according to u _m (u _a , u _β ) in the two-phase stationary coordinate system, calculates X, Y, Z according to the following formula (4), and then presses the corresponding voltage interval number sector from the following look-up table The adjacent basic vector times t ₁ and t ₂ are found in 1, then the zero vector time is t ₀ =1-t ₁ -t ₂ ;

X＝u _β

$\mathrm{<span\; class="notranslate">\; Y</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; (</span>\sqrt{\mathrm{<span\; class="notranslate">\; 3</span>}}{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; \&alpha;</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; \&beta;</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$

$\mathrm{<span\; class="notranslate">\; Z</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; (</span><span\; class="notranslate">\; -</span>\sqrt{\mathrm{<span\; class="notranslate">\; 3</span>}}{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; \&alpha;</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; \&beta;</span>}}<span\; class="notranslate">\; )</span>$

Voltage interval number sector query table 1

sector S1 S2 S3 S4 S5 S6 t ₁ Y -X -Z Z x -Y t ₂ Z Y x -X -Y -Z v _k /v _k+1 v ₂ /v ₃ v ₆ /v ₁ v ₁ /v ₂ v ₄ /v _{5 v3} / _{v4 v5} / _v6 T _a /(T _s /2) τ ₀ +t ₂ ′ τ ₀ τ ₀ τ ₀ +t ₁ ′+t ₂ ′ τ ₀ +t ₁ ′ τ ₀ +t ₁ ′+t ₂ ′ T _b /(T _s /2) τ ₀ τ ₀ +t ₁ ′+t ₂ ′ τ ₀ +t ₁ ′ τ ₀ +t ₂ ′ τ ₀ +t ₁ ′+t ₂ ′ τ ₀ T _c /(T _s /2) τ ₀ +t ₁ ′+t ₂ ′ τ ₀ +t ₂ ′ τ ₀ +t ₁ ′+t ₂ ′ τ ₀ τ ₀ τ ₀ +t ₁ ′

_The modulation algorithm optimization module ₅ calculates the optimized adjacent basic vector times _{t 1 ′} , t ₂ ′ and Zero vector time t ₀ ′, and the first trigger PWM comparison point time τ ₀ ; as shown in Figure 2, the details of the optimized modulation algorithm are as follows:

1) If t ₀ ≥ 2t _lim , t ₁ ′=t ₁ , t ₂ ′=t ₂ , t ₀ ′=t ₀ ;

2) If t _lim ≤t ₀ <2t _lim , t ₁ ′=t ₁ , t ₂ ′=t ₂ , t ₀ ′=t ₀ ; when t ₁ >t ₂ , τ ₀ =0, otherwise τ ₀ = t ₀ ';

3) When t _lim /2≤t ₀ <t _lim , use the proportional compression method, t ₀ ′=t _lim ; when t ₁ >t ₂ , τ ₀ =0, otherwise τ ₀ =t ₀ ′;

4) When t ₀ <t _lim /2, the output voltage works on the boundary of the regular hexagon in the voltage space, that is, t ₀ ′=0, τ ₀ =0. At this time, the calculation methods of t ₁ ′ and t ₂ ′ are as follows:

4.1) When 0≤t ₀ <t _lim /2 or when t ₀ <0∩t ₁ +t ₂ /2<1∩t ₁ /2+t ₂ <1, the proportional scaling method is adopted, namely When t ₁ ′<t _lim , t ₁ ′=0, t ₂ ′=1; when t ₂ ′<t _lim , t ₁ ′=1, t ₂ ′=0;

4.2) When t ₁ ≥t ₂ ∩t ₁ +t ₂ /2≥1, output the forward basic vector v _k , that is, t ₁ ′=1, t ₂ ′=0;

4.3) When t ₁ <t ₂ ∩t ₁ /2+t ₂ ≥1, output the backward basic vector v _k+1 , that is, t ₁ ′=0, t ₂ ′=1;

The above t _lim is the sum of dead time and narrow pulse width limit time;

The PWM comparison point time calculation module 6, according to t ₁ ′, t ₂ ′, τ ₀ , finds the high level of the upper bridge arm of each phase of the A phase, B phase, and C phase according to the voltage interval number sector from the upper look-up table 1 PWM comparison point time T _a , T _b , T _c under conduction.

In addition, the SVPWM optimization method described in this embodiment is to improve the traditional seven-segment SVPWM into a comprehensive discontinuous PWM (GDPWM, Generalized DiscontinuousPWM), and the actual voltage space is expanded from the area shown in the dark part of Figure 3a to the deep area of Figure 3b The area shown in the colored part is as follows:

If t ₀ ≥ 2t _lim , use seven-segment SVPWM; if t _lim ≤t ₀ <2t _lim , use DPWM1, that is, a five-segment PWM; if t ₀ <t _lim , use a certain modulation rule to convert the voltage vector Convert to DPWM1, 3-segment PWM or 1-segment PWM voltage space.

The t _lim is the sum of the dead time and the narrow pulse width limit time; there is no constant level in the seven-segment SVPWM, and there are two duty cycle limits of τ ₀ and τ ₇ (that is, the zero vector time t ₀ ≥ 2t _lim ); in the DPWM1, $\left\{\begin{array}{cc}{\mathrm{\&tau;}}_0=0,{\mathrm{\&tau;}}_7=t_0,& t_1\&Greater\; Equal;t_2\\ {\mathrm{\&tau;}}_0=t_0,{\mathrm{\&tau;}}_7=0,& el\mathrm{the\; s}e\end{array}\right.,$ That is, a certain phase is at a constant level, and there is only one duty ratio limit of τ ₀ or τ ₇ (that is, the zero vector time t ₀ ≥ t _lim ); in the three-stage PWM, a certain two phases are at a constant level, and only The voltage of another phase can be adjusted, and the actual voltage space has only the discontinuous boundary of the regular hexagon; the one-stage PWM means that the three phases are all at a constant level, and the actual voltage can only work on the basic vector and zero vector.

Due to the limitation of dead time and narrow pulse width, the linear modulation area of seven-segment SVPWM loses 2t _lim , that is, the actual linear modulation area is u _r ∈ [0,(1-2t _lim )]. After adopting the integrated discontinuous PWM of the present invention, the actual linear modulation area can be extended to u _r ∈ [0,(1-t _lim )]. As shown in Figure 3b, the inside of the inscribed circle is the new linear modulation region (0≤u _r ≤(1-t _lim )), and the outside of the inscribed circle is the actual overmodulation region ( ). In the new linear modulation area, the smooth switching from seven-segment SVPWM to DPWM1 is sufficient; in the actual over-modulation area, since some areas cannot be directly reached, an optimized over-modulation method needs to be used for processing.

In the actual overmodulation region, Note that u _r is the original given reference voltage (reference voltage), u _m is the revised given reference voltage (modifiedreference voltage), up is the actual output voltage (practicalvoltage) after _{overmodulation} processing. The above-mentioned overmodulation process includes the following two steps:

1) Modify the given reference voltage so that the original given reference voltage range with the corrected given reference voltage range Correspondence, that is, the mapping relationship between u _r and u _m is established: the phase angle remains unchanged; when (1-t _lim )<u _r ≤1, the amplitude remains unchanged, that is, u _m = u _r ; when When , the amplitude is corrected linearly, that is, $u_m=(\frac{2}{\sqrt{3}}+1)(u_r-1)+1\&Element;(1,4/3\&rsqb;.$

2) The modified given reference voltage u _m is modulated according to the optimized modulation algorithm to obtain the actual output voltage u _p :

2.1) When t ₀ ≥t _lim , directly output u _m , that is, u _p = _um ;

2.2) When t _lim /2≤t ₀ <t _lim , process u _m according to the proportional compression method shown in Figure 4a to get up _p , namely $\begin{array}{cc}{t}_1^{\&prime;}=\frac{t_1}{t_1+t_2}\&Center\; Dot;(1-t_{\lim }),& t_2^{\&prime;}=\frac{t_2}{t_1+t_2}\&Center\; Dot;(1-t_{\lim })\end{array},$ t ₀ ′=t _lim ;

2.3) When t ₀ <t _lim /2, as follows:

2.3.1) When 0≤t ₀ <t _lim /2, process u _m according to the proportional stretching method shown in Figure 4b to obtain up _p , namely $\begin{array}{cc}{t}_1^{\&prime;}=\frac{t_1}{t_1+t_2},& t_2^{\&prime;}=\frac{t_2}{t_1+t_2}\end{array},$ t ₀ '=0;

2.3.2) When u _m ∈ BCD, that is, t ₀ <0∩t ₁ +t ₂ /2<1∩t ₁ /2+t ₂ <1, process u _m according to the proportional compression method shown in Figure 4c get u _p , ie t ₀ '=0;

2.3.3) When u _m ∈ BDF, that is, when t ₁ ≥ t ₂ ∩ t ₁ + t ₂ /2 ≥ 1, output the forward basic vector v _k as shown in Figure 4d;

2.3.4) When u _m ∈ CDE, that is, when t ₁ <t ₂ ∩t ₁ /2+t ₂ ≥ 1, output the backward basic vector v _k+1 as shown in Figure 4d;

2.3.5) For the operating points that cannot be reached on the boundary of the regular hexagon in the voltage space after the equal-proportional stretching in Figure 4b and the equal-proportional compression in Figure 4c, replace them with the adjacent basic voltage vector v _k or v _k+1 .

The implementation examples described above are only preferred embodiments of the present invention, and are not intended to limit the scope of the present invention. Therefore, all changes made according to the shape and principle of the present invention should be covered within the scope of protection of the present invention.

Claims (3)

1. A two-level three-phase space vector pulse width modulator, comprising:

a given reference voltage modification module (1) for modifying the given reference voltage u according to the given reference voltage u_r(u_rAngle theta), without changing the voltage phase angle, when u_rWhen > 1, according toCorrecting the voltage amplitude to obtain a corrected reference voltage u_m(u_m∠θ)；

A voltage coordinate transformation module (2) for transforming the modified reference voltage u_m(u_mAngle theta) is transformed to a two-phase stationary coordinate system u by a polar coordinate representation mode_m(u_a,u_β) I.e. u_α＝u_mcos θ and u_β＝u_msinθ；

A voltage interval calculation module (3) for calculating u in the two-phase static coordinate system_m(u_a,u_β) Corresponding to the interval position in the voltage space, namely the voltage interval number sector;

a vector time calculation module (4) for calculating a vector time from the two-phase stationary coordinate system u_m(u_a,u_β) Obtaining adjacent basic vector time t by using the corresponding voltage interval number sector₁、t₂And zero vector time t₀＝1-t₁-t₂；

A modulation algorithm optimization module (5) for optimizing said time t of said adjacent basis vectors₁、t₂And zero vector time t₀Calculating the optimized adjacent basic vector time t 'according to the optimized modulation algorithm'₁、t′₂And zero vector time t'₀And first trigger PWM compare point time tau₀；

A PWM comparison point time calculation module (6) according to the t'₁、t′₂、τ₀Obtaining the PWM comparison point time T under the high-level conduction of the upper bridge arm of each phase of A phase, B phase and C phase by the corresponding voltage interval number sector_a、T_b、T_c。

2. A two-level three-phase space vector pulse width modulator according to claim 1 wherein said optimized modulation algorithm comprises the steps of:

1) if t₀≥2t_lim，t′₁＝t₁，t′₂＝t₂，t′₀＝t₀；

2) If t_lim≤t₀＜2t_lim，t′₁＝t₁，t′₂＝t₂，t′₀＝t₀(ii) a When t is₁＞t₂Time, τ₀0, otherwise τ₀＝t′₀；

3) When t is_lim/2≤t₀＜t_limWhen in use, the equal proportion compression method is adopted, t′₀＝t_lim(ii) a When t is₁＞t₂Time, τ₀0, otherwise τ₀＝t′₀；

4) When t is₀＜t_limAt/2, the output voltage operates on the regular hexagonal boundary of the voltage space, i.e. t'₀＝0，τ₀T 'at this time'₁、t′₂The calculation method of (2) is as follows:

4.1) when t is more than or equal to 0₀＜t_limAt/2 or when t₀＜0∩t₁+t₂/2＜1∩t₁/2+t₂When < 1, the scaling method is adopted, i.e.When t'₁＜t_limOf is t'₁＝0，t′₂1 is ═ 1; when t'₂＜t_limOf is t'₁＝1，t′₂＝0；

4.2) when t is₁≥t₂∩t₁+t₂When/2 is more than or equal to 1, outputting the forward basic vector v_kI.e. t'₁＝1，t′₂＝0；

4.3) when t₁＜t₂∩t₁/2+t₂When the vector is more than or equal to 1, outputting a backward basic vector v_k+1I.e. t'₁＝0，t′₂＝1；

Wherein, thet_limIs the sum of the dead time and the narrow pulse width limit time.

3. A SVPWM optimization method of the two-level three-phase space vector pulse width modulator according to claim 1, wherein: if t₀≥2t_limAdopting seven-segment SVPWM; if t_lim≤t₀＜2t_limA DPWM1 mode, namely a five-segment PWM mode is adopted; if t₀＜t_limConverting the voltage vector to a DPWM1, three-segment PWM or one-segment PWM voltage space; wherein,

said t is_limIs the sum of the dead time and the narrow pulse width limit time; there is no constant level and τ in the seven-segment SVPWM₀And τ₇Two duty cycle limits; in the DPWM1, the DPWM is, <math> <mrow> <mfenced open = '{' close = ''> <mtable> <mtr> <mtd> <mrow> <msub> <mi>&tau;</mi> <mn>0</mn> </msub> <mo>=</mo> <mn>0</mn> <mo>,</mo> <msub> <mi>&tau;</mi> <mn>7</mn> </msub> <mo>=</mo> <msub> <mi>t</mi> <mn>0</mn> </msub> <mo>,</mo> </mrow> </mtd> <mtd> <mrow> <msub> <mi>t</mi> <mn>1</mn> </msub> <mo>&GreaterEqual;</mo> <msub> <mi>t</mi> <mn>2</mn> </msub> </mrow> </mtd> </mtr> <mtr> <mtd> <mrow> <msub> <mi>&tau;</mi> <mn>0</mn> </msub> <mo>=</mo> <msub> <mi>t</mi> <mn>0</mn> </msub> <mo>,</mo> <msub> <mi>&tau;</mi> <mn>7</mn> </msub> <mo>=</mo> <mn>0</mn> <mo>,</mo> </mrow> </mtd> <mtd> <mrow> <mi>e</mi> <mi>l</mi> <mi>s</mi> <mi>e</mi> </mrow> </mtd> </mtr> </mtable> </mfenced> <mo>,</mo> </mrow> </math> i.e. a certain phase is a constant level, only tau₀Or τ₇A duty cycle limit; in the three-stage PWM, a certain two phases are constant levels, only the other phase voltage can be regulated, and the actual voltage space only has a discontinuous boundary of a regular hexagon; the one-stage PWM is that three phases are all constant levels, and the actual voltage can only work on a basic vector and a zero vector;

due to the dead time and narrow pulse width limitations, some regions cannot actually be reached directly in the actual overmodulation region, and therefore an optimized overmodulation method is required for processing, which comprises the following steps:

1) correcting the given reference voltage so that the range of the given reference voltage is withinAnd the corrected given reference voltage rangeCorrespond to, i.e. u_rAnd u_mThe mapping relation is established between the following steps: the phase angle remains unchanged; when (1-t)_lim)＜u_rWhen the amplitude is less than or equal to 1, the amplitude is unchanged, i.e. u_m＝u_r(ii) a When in useThe amplitude being linearly modified, i.e. <math> <mrow> <msub> <mi>u</mi> <mi>m</mi> </msub> <mo>=</mo> <mrow> <mo>(</mo> <mfrac> <mn>2</mn> <msqrt> <mn>3</mn> </msqrt> </mfrac> <mo>+</mo> <mn>1</mn> <mo>)</mo> </mrow> <mrow> <mo>(</mo> <msub> <mi>u</mi> <mi>r</mi> </msub> <mo>-</mo> <mn>1</mn> <mo>)</mo> </mrow> <mo>+</mo> <mn>1</mn> <mo>&Element;</mo> <mo>(</mo> <mn>1</mn> <mo>,</mo> <mn>4</mn> <mo>/</mo> <mn>3</mn> <mo>&rsqb;</mo> <mo>;</mo> </mrow> </math>

2) Corrected given reference voltage u_mModulating according to the optimized modulation algorithm to obtain the actual output voltage u_pThe method comprises the following steps:

2.1) when t₀≥t_limThen directly output u_mI.e. u_p＝u_m；

2.2) when t is_lim/2≤t₀＜t_limThen, processing u according to an equal proportion compression method_mTo obtain u_pI.e. by <math> <mrow> <mtable> <mtr> <mtd> <mrow> <msubsup> <mi>t</mi> <mn>1</mn> <mo>&prime;</mo> </msubsup> <mo>=</mo> <mfrac> <msub> <mi>t</mi> <mn>1</mn> </msub> <mrow> <msub> <mi>t</mi> <mn>1</mn> </msub> <mi>+</mi> <msub> <mi>t</mi> <mi>2</mi> </msub> </mrow> </mfrac> <mo>&CenterDot;</mo> <mrow> <mo>(</mo> <mn>1</mn> <mo>-</mo> <msub> <mi>t</mi> <mi>lim</mi> </msub> <mo>)</mo> </mrow> <mo>,</mo> </mrow> </mtd> <mtd> <mrow> <msubsup> <mi>t</mi> <mn>2</mn> <mo>&prime;</mo> </msubsup> <mo>=</mo> <mfrac> <msub> <mi>t</mi> <mn>2</mn> </msub> <mrow> <msub> <mi>t</mi> <mn>1</mn> </msub> <mi>+</mi> <msub> <mi>t</mi> <mi>2</mi> </msub> </mrow> </mfrac> <mo>&CenterDot;</mo> <mrow> <mo>(</mo> <mn>1</mn> <mo>-</mo> <msub> <mi>t</mi> <mi>lim</mi> </msub> <mo>)</mo> </mrow> </mrow> </mtd> <mtd> <mrow> <msubsup> <mi>t</mi> <mn>0</mn> <mo>&prime;</mo> </msubsup> <mo>=</mo> <msub> <mi>t</mi> <mrow> <mi>l</mi> <mi>i</mi> <mi>m</mi> </mrow> </msub> </mrow> </mtd> </mtr> </mtable> <mo>;</mo> </mrow> </math>

2.3) when t₀＜t_limAt/2, the following:

2.3.1) when t is more than or equal to 0₀＜t_limAt 2, treating u by stretching in equal proportion_mTo obtain u_pI.e. by <math> <mrow> <msubsup> <mi>t</mi> <mn>2</mn> <mo>&prime;</mo> </msubsup> <mo>=</mo> <mfrac> <msub> <mi>t</mi> <mn>2</mn> </msub> <mrow> <msub> <mi>t</mi> <mn>1</mn> </msub> <mo>+</mo> <msub> <mi>t</mi> <mn>2</mn> </msub> </mrow> </mfrac> <mo>,</mo> </mrow> </math> t′₀＝0；

2.3.2) when t₀＜0∩t₁+t₂/2＜1∩t₁/2+t₂When the rate is less than 1, processing u according to an equal proportion compression method_mTo obtain u_pI.e. by <math> <mrow> <mtable> <mtr> <mtd> <mrow> <msubsup> <mi>t</mi> <mn>1</mn> <mo>&prime;</mo> </msubsup> <mo>=</mo> <mfrac> <msub> <mi>t</mi> <mn>1</mn> </msub> <mrow> <msub> <mi>t</mi> <mn>1</mn> </msub> <mo>+</mo> <msub> <mi>t</mi> <mn>2</mn> </msub> </mrow> </mfrac> <mo>,</mo> </mrow> </mtd> <mtd> <mrow> <msubsup> <mi>t</mi> <mn>2</mn> <mo>&prime;</mo> </msubsup> <mo>=</mo> <mfrac> <msub> <mi>t</mi> <mn>2</mn> </msub> <mrow> <msub> <mi>t</mi> <mn>1</mn> </msub> <mo>+</mo> <msub> <mi>t</mi> <mn>2</mn> </msub> </mrow> </mfrac> <mo>,</mo> </mrow> </mtd> <mtd> <mrow> <msubsup> <mi>t</mi> <mn>0</mn> <mo>&prime;</mo> </msubsup> <mo>=</mo> <mn>0</mn> </mrow> </mtd> </mtr> </mtable> <mo>;</mo> </mrow> </math>

2.3.3) when t₁≥t₂∩t₁+t₂When/2 is more than or equal to 1, outputting the forward basic vector v_k；

2.3.4) when t₁＜t₂∩t₁/2+t₂When the vector is more than or equal to 1, outputting a backward basic vector v_k+1；

2.3.5) dropping the working point which can not be reached on the regular hexagon boundary of the voltage space after the equal proportion stretching and the equal proportion compression, and using the adjacent basic voltage vector v_kOr v_k+1And (4) replacing.