CN103714860B - Fast dynamic register, register method, integrated circuit - Google Patents

Abstract

A fast dynamic register includes a data block, a precharge circuit, a transparent latch, and an output logic gate. The precharge circuit precharges the first and second precharge nodes in response to a clock and then releases the first precharge node. The data block evaluates the data by pulling the first pre-charge node low or by not pulling it low in response to the clock, in which case the second pre-charge node is discharged. The transparent latch passes the state of the second pre-charge node to the storage node when the transparent latch is transparent, otherwise the storage node is latched. The output logic gate drives the output node to a state dependent on the states of the second precharge node and the storage node. The transparent latch may be implemented with relatively small devices to reduce size and power consumption and thereby increase efficiency.

Description

Fast dynamic register, register method, integrated circuit

Cross References to Applications

This application claims priority to the following United States Provisional Patent Application, which is hereby incorporated by reference in its entirety for all intents and purposes.

This application is related to the following co-pending US patent applications, each having a common assignee and a common inventor.

technical field

The present invention relates to latch and register circuits, and more particularly, to fast dynamic registers with transparent latches for improved efficiency and methods of registering them, scannable fast dynamic registers, fast dynamic registers containing fast dynamic registers or scannable fast Integrated circuit with dynamic registers.

Background technique

Dynamic logic circuits often exhibit relatively long setup and/or hold times to ensure proper operation. It is desirable to increase the efficiency of fast dynamic register circuits with minimal settling time without the overhead of pulsed clock circuits. Scan capability is desirable for fast dynamic register circuits with minimal settling time and no pulse clock circuit overhead.

Contents of the invention

A fast dynamic register according to one embodiment includes a data block, a precharge circuit, a transparent latch, and an output logic gate. The data block is coupled between a first precharge node and a discharge node, receives at least one data input, and when the clock node transitions from a first clock state to a second clock state, by pulling the first precharge node to to the discharge node for evaluation. When the clock node is in the first clock state, the precharge circuit precharges the first and second precharge nodes, and when the clock node transitions to the second clock state, the precharge circuit releases the first precharge node and discharges the node pulled low, and after the clock node transitions to the second clock state, the precharge circuit discharges the second precharge node to low while the first precharge node remains high. The transparent latch has a latch input coupled to the second precharge node and an output coupled to the storage node. The transparent latch is transparent to passing the state of the second precharge node to the storage node when the clock node is in the second clock state, and latches the Storage nodes. An output logic gate drives an output node to a state based on the states of the second precharge node and the storage node.

The transparent latch may include first and second transistors, and a keeper circuit. Each of the transistors has a pair of current terminals coupled between the latch input and the latch output, wherein the first transistor has a control input coupled to the clock node, and wherein the second transistor has a control input coupled to an inverting clock node. The keeper circuit is coupled to a clock node, an inverting clock node, and a latch output, and operates to maintain a state of an output node when the clock node is in a first clock state.

Fast dynamic register circuits can be implemented in scan mode. In this case, the register circuit includes a scan enable block, a select gate, and a second transparent latch. a scan enable block coupled between the first precharge node and the discharge node to receive a scan enable input, and when the scan enable input is set and when the clock node transitions from the first clock state to the second clock state, The scan enable block pulls the first precharge node to the discharge node. The select gate is interposed between the second precharge node and the transparent latch, wherein the select gate has a first input coupled to the second precharge node, a first input coupled to the scan data node Two inputs and an output coupled to the latch input of the transparent latch. The second transparent latch has an input receiving a scan data input and an output coupled to a scan data node. The second transparent latch is transparent for passing the scan data input to the scan data node when the clock node is in the first clock state and when the scan enable input is asserted, and when the scan enable input is deasserted and when the clock The second transparent latch forces the scan data node bit high when the node is in the first clock state, and holds the last state of the scan data node when the clock node is in the second clock state.

An integrated circuit according to one embodiment comprises combinational logic providing at least one data input and a clock node, and a fast dynamic register as described above.

A method of registering data according to an embodiment includes: when the clock signal is in a first clock state, precharging a first precharge node to a high potential; when the at least one data input is not expected, and when the clock signal transitions to After the second clock state, at least one data input is evaluated and the first precharge node is held high; and when the clock signal transitions to the second clock state and when the at least one data input is evaluated, the first precharged node is asserted The charging node is discharged low; when the clock signal is in the first clock state, precharge the second precharge node is high; if the first precharge node remains high after the clock signal transitions to the second logic state, discharge The second precharge node is low potential, otherwise keep the second precharge node high potential; when the clock signal is in the first clock state, latch the state of the storage node; and when the clock signal is in the second clock state, set the second The state of the second precharge node is communicated to the storage node; and the output node is set based on the state of the second precharge and storage node.

The method may include: inverting the clock signal and providing the inverted clock signal; turning on a first pass transistor coupled between the second precharge node and the storage node controlled by the clock signal; turning on passing through a second pass transistor coupled between the second precharge node and the storage node controlled by the inverted clock signal; and maintaining the state of the storage node when the clock signal is in the first clock state. The method may further comprise: receiving a scan enable input value when the scan enable input is set; bypassing the data set value by forcing the first precharge node to discharge to a low potential when the clock signal transitions to the second clock state and when said scan enable input is set, injecting a scan data input value in place of the state of the second precharge node, and passing the state of the scan data input to the storage node when the clock signal is in the second clock state.

A scannable fast dynamic register according to one embodiment, comprising: a data and scan enable circuit coupled between a first precharge node and a discharge node, and receiving at least one data input value and a scan enable input value, wherein , when the clock node transitions from the first clock state to the second clock state, and when the data block is estimated or when the scan enable input is set, the data and scan enable circuit sets the first precharge node value pulled to the value of the discharge node, in addition, the data and scan enable circuit does not pull the first precharge node to the discharge node; precharge circuit, when the clock When the node is in the first clock state, precharge both the second precharge node and the first precharge node to a high potential, and when the clock node transitions to the second clock state, release the the first pre-charge node and pull the discharge node low, and after the clock node transitions to the second clock state and while the first pre-charge node remains high, pull the The second pre-charge node is discharged to a low potential; a selection circuit having a first input coupled to the second pre-charge node, having a second input coupled to the scan data node, and having a selected an output; a storage circuit having a storage input receiving a value of the selected output and having an output coupled to a storage node, wherein when the clock node is in the second clock state, the a storage circuit communicates the state of the selected output value to the storage node, and when the clock node is in the first clock state, the storage circuit maintains the last state of the storage node; a scan enable circuit , when the scan enable input is set and when the clock node is in the first clock state, pass the state of the scan input to the scan data node, when the scan enable signal is deasserted and when the forcing the scan data node to a high potential when the clock node is in the first clock state, and maintaining the last state of the scan data node when the clock node is in the second clock state; and outputting a logic gate , driving an output node to a state based on the states of the second precharge node and the storage node.

An integrated circuit according to an embodiment, comprising: a clock node and a scan enable node, wherein the scan enable node receives a scan enable signal indicating a scan mode; and at least one scannable fast dynamic latch. Each scannable fast dynamic latch includes: a data and scan enable circuit, coupled between the first precharge node and the discharge node, and receiving at least one data input value and having a function of receiving the scan enable signal A scan enable input value, where the data and scan an enable circuit that pulls the first precharge node value to the discharge node value, and in addition the data and scan enable circuits do not pull the first precharge node value to the discharge node The value of the pre-charge circuit, when the clock node is in the first clock state, pre-charge both the second pre-charge node and the first pre-charge node to a high potential, when the clock node transitions When the second clock state is reached, the first precharge node is released and the discharge node is pulled low, and after the clock node transitions to the second clock state, only the first precharge node When the charging node maintains a high potential, the second pre-charge node is discharged to a low potential; the selection circuit has a first input terminal coupled to the second pre-charge node, and has a first input terminal coupled to the scan data node a second input and having a selected output; a storage circuit having a storage input receiving said selected output value and having an output coupled to a storage node, wherein when said clock node is at said In the second clock state, the storage circuit transfers the state of the selected output terminal to the storage node, and when the clock node is in the first clock state, the storage circuit maintains the state of the storage node Last state; scan enable circuit, when the scan enable input is set and when the clock node is in the first clock state, passes the state of the scan input to the scan data node, when the scan is deasserted enable signal and force the scan data node high when the clock node is in the first clock state, and hold the scan data node high when the clock node is in the second clock state a final state; and an output logic gate driving an output node to a state based on states of the second precharge node and the storage node.

Description of drawings

The benefits, features and advantages of the present invention will become better understood with reference to the following description and accompanying drawings, in which:

Figure 1 is a schematic diagram of a fast dynamic register implemented according to one embodiment;

2-5 illustrate different configurations of the data block of FIG. 1 comprising one or more N-channel transistors;

FIG. 6 is an architectural diagram of a latch according to one embodiment, which can be used as the latch of FIG. 1;

FIG. 7 is an architectural diagram of a scannable fast dynamic register realized according to one embodiment;

FIG. 8 is an architectural diagram of an alternative embodiment of either or both of the transparent latches of FIG. 7 using multiplexers; and

FIG. 9 is a block diagram of an integrated circuit incorporating each of the scannable fast dynamic registers implemented according to the scannable fast dynamic registers of FIG. 7 .

detailed description

The description given below is to enable those skilled in the art to make and use the present invention according to the applications and requirements disclosed in the specification. However, various modifications to the embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the specific embodiments shown and described here, and any broadest scope consistent with the principles disclosed in the specification and novel features should be included in the patent scope of the present invention.

Fig. 1 is a structural diagram of a fast dynamic register 100 implemented according to an embodiment. One or more data inputs are provided to respective inputs of the input data block 102 and are collectively denoted DN, the designation "DN" representing any suitable integer "N" of one or more data inputs, where N is an integer greater than zero . A single input data value (eg, D or D1 ) is also contemplated and included within the embodiments. The input data block 102 is coupled between a precharge (PC1 ) node 103 and a discharge (DCH) node 101 . When CK goes high, the input data block 102 evaluates the collective state of one or more data inputs DN according to the desired logic function. When CK goes high and data block 102 "evaluates", then it creates a current path between nodes 103 and 101 with low enough resistance to effectively pull down the voltage of PC1 towards VSS via the DCH node. If data block 102 is not being evaluated, no current path is provided or a high impedance path is presented between nodes 103 and 101 so that node PC1103 remains at a high potential. At least one reason the fast dynamic register 100 is fast is because it has near-zero setup requirements for non-scanning data inputs.

N-channel transistor N1 has: a drain coupled to DCH node 101; a source coupled to power supply node VSS; and a gate coupled to clock node 104 receiving an input clock signal CK. Clock node 104 is coupled to the gates of N-channel transistors N1, N4, and N6, to the gates of P-channel devices P1 and P2, to the inputs of inverters 105 and 123, and to To the non-inverting clock input "C" of latch 117. P1 and P2 have sources coupled to power supply node VDD. The drain of P1 is coupled to PC1 node 103 , and the drain of P2 is coupled to a second precharge ( PC2 ) node 109 . The output of inverter 105 is coupled to node 107, which is coupled to the source of N-channel transistor N2. N2 has a gate coupled to PC1 node 103 and a drain coupled to PC2 node 109 .

The PC2 node 109 is coupled to one input of a two-input NAND logic gate 111 which provides an inverted data output QB at the output. Please note that in alternative embodiments, the NAND logic gate 111 may be replaced by an AND logic gate (for the non-inverting output) in certain applications. PC2 node 109 is coupled to the input of another inverter 113, the output of inverter 113 is coupled to the input of inverter 115, and the output of inverter 115 is coupled to the Data "D" input. The output of inverter 123 is coupled to node CB 124 of the inverted clock input "CB" of latch 117 to provide an inverted clock signal, and the output of latch 117 is coupled to storage node 120 to provide signal ST Output. The storage node 120 is coupled to the other input terminal of the NAND logic gate 111 .

PC1 node 103 is coupled to keeper circuit 116 comprising P-channel devices P3 and P4 , N-channel transistors N3 and N4 , and inverter 119 . The source of P3 is coupled to VDD, its gate is coupled to VSS, and its drain is coupled to the source of P4. The drain of P4 is coupled to PC1 node 103, which is further coupled to the input of inverter 119 and to the drain of N3. The source of N3 is coupled to the drain of N4, which has a source coupled to VSS. The output terminal of inverter 119 is coupled to the gates of N3 and P4.

PC2 node 109 is further coupled to keeper circuit 118 comprising P-channel devices P5 and P6 , N-channel transistors N5 and N6 , and inverter 121 . The source of P5 is coupled to VDD, its gate is coupled to PC1 node 103, and its drain is coupled to the source of P6. The drain of P6 is coupled to PC2 node 109, which is further coupled to the input of inverter 121 and to the drain of N5. The source of N5 is coupled to the drain of N6 , the source of N6 is coupled to VSS and the gate of N6 is coupled to CK node 104 . The output terminal of the inverter 121 is coupled to the gates of N5 and P6.

Please note that the N-channel and P-channel devices described here are MOS type devices or field effect transistors (FETs) or MOSFETs, etc., such as NMOS, PMOS, NFET, PFET and other types of transistor devices. In general, each transistor device includes first and second current terminals (eg, drain, source, emitter, collector, etc.) and a control node (eg, gate, base, etc.). Any logic gate described here, including inverters and logic gates (AND, NAND, OR, NOR, etc.), and any latch described here, can also be used with N-channel and P-channel devices or transistors, etc. Wait for it to come true.

In one embodiment, the latch 117 is configured as a transparent latch comprising pass logic gates, etc., where the D input is passed to the Q output when the C input is high and the CB input is low, and when When the C input is low and the CB input is high, the Q output is isolated from the D input. The power supply node VSS has an appropriate reference voltage (eg, ground) relative to another power supply node VDD. The power supply voltage between VDD and VSS is any suitable voltage level (eg, 1V, 1.5V, 3V, 5V, etc.) depending on the particular architecture or technology used.

Clock signal CK may be generated locally (eg, a local oscillator, etc., not shown) or provided on CK node 104 from an external source. The CK signal is set on positive logic, where it provides setup time when low and hold time when high for data evaluation. Therefore, the operating clock edge is the rising edge of the clock. Negative logic clock signals are also applicable in the present invention. Generally, the clock signal toggles between the first and second states for purposes of timing and synchronization, among other things.

During normal operation, when CK is set low, both precharge nodes PC1103 and PC2109 are precharged to high potential via P1 and P2 respectively. N4 and N6 of keeper circuits 116 and 118 are respectively turned off, while P3 and P4 of keeper circuit 116 are turned on to keep PC1 node 103 high. N1 is turned off and inverter 105 pulls node 107 high to turn N2 off.

When CK is low, the data input DN normally changes or transitions state. Assuming that when CK goes high and data signal DN does not cause data block 102 to be evaluated, P1 and P2 will be off and N4, N6 and N1 will be on. PC1 node 103 is held high by keeper circuit 116 (via P3 and P4), while inverter 105 pulls node 107 low to turn on N2 and discharge PC2 node 109 low . In response to PC2 going low, NAND logic gate 111 pulls QB high (or holds QB high). After a very small delay, inverters 113 and 115 pull the D input of latch 117 low. Since CK is high and inverter 123 pulls CB low, latch 117 is in a transparent state passing the D input in a low state to pull storage node 120 low (or hold ST low ). N5 and N6 of keeper circuit 118 conduct and hold PC2 node 109 low until CK goes low.

When CK returns low, latch 117 switches to its isolated state to hold storage node 120 low. At this time, regardless of any changes in the state of the PC2 node 109 , the NAND logic gate 111 keeps QB pulled high. CK turns off N4 and N6 and turns on P1 and P2 so that both PC1 and PC2 are precharged to high potential again. The QB output signal is latched high and the fast dynamic register 100 is ready to be evaluated for another data in the next CK cycle.

In the next cycle, data block 102 is evaluated assuming the data input DN changes. When CK returns high, P1 turns off, N1 turns on and data block 102 evaluates to pull PC1 node 103 low. The devices within block 102 and N1 are sized sufficiently to overcome the operation of P3 and P4 (since the keeper circuits are generally smaller and conduct less current, so that the current through block 102 is greater than The current flowing through P3 and P4 can overcome the potential of node 103 affected by the operation of P3 and P4). With PC1 node 103 pulled low, N3 and N4 are turned on to keep PC1 low. PC1 going low turns on P5 and keeps PC2 node 109 pulled high via P5 and P6. Note that N2 may be turned on slightly for a moment because node 107 is pulled low and PC1 node 103 is pulled low. However, P5 and P6 keep PC2 node 109 high.

When CK is high, latch 117 is transparent to pass the high value of PC2 node 109 to storage node 120, so both inputs of NAND logic gate 111 are high, which in turn pulls QB low . When CK next goes low, storage node 120 at the output of latch 117 will latch high until the next CK cycle.

Inverter 105 (and keeper circuits 116 and 118) collectively perform precharge circuit operations in response to CK, P1, P2, N1, N2. When CK is low, the precharge circuit precharges both nodes 103 and 109 high. When CK goes high, one of nodes 103 and 109 will go low based on whether input data block 102 is evaluated.

2-5 illustrate different configurations of data blocks 102 for performing the required logical functions. Figure 2 shows a simple configuration in which the data block 102 contains a single N-channel transistor ND1 with a drain coupled to PC1 node 103, a source coupled to DCH node 101, and a gate receiving a single data input D1. In this case, because ND1 conducts when D1 is high, data block 102 evaluates when CK goes high. ND1 remains off when D1 is low, so data block 102 is not evaluated, so PC1 node 103 remains high when CK goes high.

FIG. 3 is an architectural diagram of an alternative embodiment of a data block 102 comprising N N-channel transistors ND1 , ND2 , . . . NDN (ND1-NDN) coupled in parallel. Specifically, each of N-channel transistors ND1-NDN has a source coupled to DCH node 101, a drain coupled to PC1 node 103, and receives N data inputs D1, D2, . . . DN (D1 -DN) to the gate of the corresponding one. In this case, data block 102 is evaluated when any one of data inputs D1-DN is high, such as according to a logical OR function.

FIG. 4 is an architectural diagram of an alternative embodiment of a data block 102 comprising N N-channel transistors ND1 , ND2 , . . . NDN (ND1-NDN) coupled in series. Specifically, the first N-channel transistor ND1 has a drain coupled to PC1 node 103, the second N-channel transistor ND2 has a drain coupled to the source of ND1, and so on, until the final N-channel Channel transistor NDN has a source coupled to DCH node 101 . The gates of N-channel transistors ND1-NDN receive respective ones of N data inputs D1, D2, . . . DN (D1-DN). In this case, the data block 102 is only evaluated if each of the data inputs D1-DN is high, such as according to a logical AND function.

FIG. 5 is an architectural diagram of an alternative embodiment of a data block 102 comprising N N-channel transistors ND1 , ND2 , . . . NDN ( ND1 -NDN ) coupled in any suitable combination of series and parallel coupling. In this case, the first set of M devices ND1-NDM are connected in parallel to each other to be coupled between PC1 node 103 and intermediate node 501, and the remaining devices NDM+1, NDM+2, . . . NDN are coupled in parallel at Between the intermediate node 501 and the DCH node 101. Furthermore, the gates of the N-channel transistors ND1-NDN receive respective ones of the N data inputs D1, D2, . . . DN (D1-DN). In this case, the data block 102 is evaluated only if one of the data inputs D1-DM is high and one of the data inputs DM+1-DN is high, such as according to a logical OR-AND function. Any suitable number of devices coupled in parallel in each layer, along with corresponding additional intermediate nodes to add additional layers, is contemplated by the present invention and may be employed in suitable embodiments.

FIG. 6 is an architectural diagram of a latch 600 that may be used as latch 117 according to one embodiment. In this case, latch 600 includes N-channel transistors NL1 , NL2 and NL3 , P-channel devices PL1 , PL2 and PL3 , and inverter 603 . The non-inverted clock C is supplied to the gates of NL1 and PL3, and the inverted clock CB is supplied to the gates of PL1 and NL2. Data input D is provided to input node 601 which is further coupled to the sources of NL1 and PL1. The drains of NL1 and PL1 are coupled together at an output node 605 that provides an output signal Q. PL2, PL3, NL2, and NL3 are coupled to implement a stack configuration of keeper circuits. Specifically, PL2 has a source coupled to VDD, a drain coupled to the source of PL3, and PL3 has a drain coupled at output node 605 and the drain of NL2. The source of NL2 is coupled to the drain of NL3, which has a source coupled to VSS. Node 605 is coupled to the input of inverter 603, which has an output coupled to the gates of NL3 and PL2.

In operation, when C is high and CB is low, latch 600 is in its transparent state. In the transparent state, PL3 and NL2 remain off or are turned off to isolate the Q output node 605 from the operation of the keeper. Further, both PL1 and NL1 are turned on to provide a low impedance path from input node 601 to output node 605 in order to drive output Q to the state of input D. When C is low and CB is high, latch 600 is in its isolation state, where PL1 and NL1 will be off to isolate Q and D. If Q is low, turn both NL2 and NL3 on to keep Q latched low. If Q is high, both PL2 and PL3 are turned on to keep Q latched high. When used as latch 117 , CK is provided to clock input C, CB is provided to clock input CB, the output of inverter 115 is provided to data input D, and output Q drives storage node 120 .

Latch 600 can be implemented in an efficient manner using smaller devices that consume less space and power. NL1 and PL1 are sized sufficiently (eg, larger) to ensure fast transitions between D inputs and Q outputs. However, in one embodiment, the remaining devices PL2, PL3, NL2, NL3 and inverter 603 are made small because they only perform keeper operations. As shown by the dotted arrow, the inverter 603 is configured as an N-channel transistor NI and a P-channel device PI coupled in series, and the N-channel transistor NI and the P-channel device PI have gates commonly coupled to the input IN and are commonly coupled to the drain of the output OUT. In one embodiment, devices PI and NI are very small devices to consume less space and power. Inverters 105, 123, 113, and 115 can be fabricated in a similar manner, but using larger devices to perform faster switching operations. NL1 and PL1 perform the primary switching operation driven by an external logic gate (e.g., the output of inverter 115), however, in response to switching of inverter 603, devices PL2 and PL3 or NL2 and NL3 switch to maintain the switched Q's status.

Consider the first case when QB transitions from low to high potential. In this case, when CK is low, ST is latched high from the previous cycle, PC2 is precharged high and QB is initially low. In this case, when CK goes high and data block 102 cannot be evaluated, the delay includes the delay of inverter 105 pulling node 107 low which turns on N2 to pull PC2 low, and NAND logic gate 111 responsively sets its output high for a delay. After a delay by inverters 113 and 115 and latch 117, storage node 120 goes low to keep QB high. Inverter 113 can be scaled down to minimize the load on PC2 node 109 . Once the storage node 120 goes low, CK can switch back to low to start the next cycle.

Consider the second case when QB transitions from a high potential to a low potential. Since it is a continuation from the first case, ST is latched low from the previous cycle so that QB is initially high. When CK returns low, the PC2 node 109 is precharged high again. Since the data input changes when CK is low, inverters 113 and 115 toggle to bring the data input D of latch 117 high. When the next high setting of CK causes data block 102 to be evaluated on the next cycle, then PC2 node 109 remains high when latch 117 becomes transparent so that inverter 115 sets the stored Node 120. In response to ST going high, NAND logic gate 111 pulls QB low.

There is a delay of approximately 2.5 logic gates from CK going high to the first instance of QB going high. Since the gate of N2 has been precharged high, as the output of inverter 105 goes low in response to the CK transition, PC2 node 109 is simultaneously pulled low, which will be detected by the NAND logic gate 111 perceived.

For the second case, referring to the latch 600 shown in Figure 6, the D input is already high when CK transitions high. As CK goes high pulling the C input high, NL1 turns on to initiate pulling the Q output high, thus pulling storage node 120 high. NAND logic gate 111 pulls QB low in response, which appears as a delay of only 2 logic gates. However, please note that NL1 by itself is not sufficient to fully pull storage node 120 high. As CK goes high, CB goes low through inverter 123 with a delay of 1 logic gate. CB going low turns on PL1 to complete the transition of the Q output going high to pull storage node 120 fully high. Although this appears as a delay of 3 logic gates, the combination of NL1 and PL1 of latch 600 used as latch 117 induces a transition of QB faster than the 3 logic gate delay. Therefore, the overall delay from CK going high to QB going low is also about a 2.5 logic gate delay. For the second case, the configuration and placement of the latch 117 as close as possible to the final NAND logic gate 111 serves to minimize the delay of the second case, preventing this delay from becoming a critical delay for the circuit.

FIG. 7 is an architectural diagram of a scannable fast dynamic register 700 implemented according to one embodiment. Scannable fast dynamic register 700 includes the same components with the same reference numbers, except that inverter 113 is replaced by NAND logic gate 701 . PC2 node 109 is coupled to one input of NAND logic gate 701 . NAND logic gate 701 provides an additional input for injecting scan-in data for scan operations (further described below). Scannable fast dynamic register 700 includes an additional N-channel transistor NS coupled in parallel with data block 102 . Specifically, the drain of NS is coupled to PC1 node 103, its source is coupled to DCH node 101, and its gate receives scan enable signal SE. NS can be implemented as a single transistor with sufficient size to pull PC1 to DCH when CK goes high, or it can be implemented as multiple transistors in parallel. The input data block 102 and NS together form the data and scan enable circuitry.

The scannable fast dynamic register 700 further includes another NAND logic gate 703 having a first input terminal receiving the SE signal, another input terminal receiving the scan input signal SI, and a data input coupled to another latch 705 The output terminal of terminal D. NAND logic gate 703 implements scan enable logic for enabling and receiving scan-in data. Latch 705 may be configured in a substantially similar manner to latch 117 , and latch 705 may also be implemented as latch 600 . Latch 705 includes a non-inverted clock input C coupled to node 124 for receiving an inverted clock signal CB, an inverted clock input CB coupled to node 104 for receiving a non-inverted clock signal CK, and The output of the inverted scan input signal SIB is provided on scan data node 707 . Coupling the scan data node 707 provides the SIB to the other input of the NAND logic gate 701 .

When the scan enable signal SE is deasserted low, then NS remains off and sets the output of the NAND logic gate 703 high. Latch 705 sets SIB high so that NAND logic gate 701 operates efficiently in the same manner as inverter 113 it replaces. In this manner, when the scan enable signal SE is deasserted low, the scan fast dynamic register 700 operates in the same manner as the fast dynamic register 100 for normal operation.

The dynamic nature of the scannable fast dynamic register 700 is somewhat bypassed during scan mode where SE is set high to enable scan-in data injection. Note that the dynamics are not completely bypassed, because in scan mode, node PC1103 discharges every CK cycle. When SE is high, the gate of NS will be pulled high to turn NS on, so that when CK goes high, NS will be turned on, providing a current path from node PC1103 to N1, so data block 102 will be short circuit or bypass. Regardless of the state of one or more data inputs DN, NS is turned on by SE simulation data evaluation to pull PC1 node 103 low when CK goes high, and continues when CK goes back low. PC1 node 103 is precharged to a high potential. PC2 node 109 remains high during successive cycles of CK, while the state of NAND logic gate 701 is determined by SIB and the state of NAND logic gate 111 is determined by ST.

When SE is set to a high potential, the NAND logic gate 703 operates as an inverter inputting the scan input signal SI. When CK is low during scan mode, the latch 705 is in a transparent mode so that the SI signal is inverted to the SIB signal and passed to the NAND logic gate 701 and then to the D input of the latch 117 . When CK is low, the latch 117 is in isolation mode. When CK goes high, latch 705 will hold the current value of SIB, and latch 117 will now pass SIB as the ST value in transparent mode. In this manner, during subsequent cycles of CK, latches 705 and 117 collectively operate in a master-slave fashion to latch scan input SI into register 700 .

Depending on the mode of operation in which the select output is provided, NAND logic gate 701 may operate as a select circuit. During normal mode with SE deasserted low, SIB remains high so that NAND logic gate 701 effectively inverts the state of PC2 node 109 as its output. The inverter 115 then inverts the output value of the NAND logic gate 701 and provides it to the D input terminal of the latch 117 . During scan mode with SE set high, PC2 node 109 is held high so that NAND logic gate 701 effectively inverts the state of SIB at its output. Again, the inverter 115 inverts the output value of the NAND logic gate 701 and provides it to the D input of the latch 117 . Thus, during scan mode with SE set, NAND logic gate 701 enables injection of scan-in data.

FIG. 8 is an architectural diagram of an alternative embodiment of either or both of transparent latches 117 and 705 generally operating as storage circuits. Either or both of the transparent latches are replaced with a multiplexer (MUX) 801 and a pair of inverters 803 and 805 . MUX 801 has a first input I1 that operates in a similar manner to the "D" input of the transparent latch, and has an output (O) that operates in a similar manner to the "Q" output of the transparent latch. MUX 801 further has a pair of select inputs S1 and S2 each receiving CK or CB based on whether latch 117 is replaced or latch 705 is replaced. The output of MUX 801 is supplied to the input of inverter 803 having an output supplied to the input of inverter 805 which has an output supplied to the second input I2 of MUX 801 .

In operation, when clock signals CK and CB have states that cause MUX 801 to select input I1 as output O, then MUX 801 operates in a "transparent" state and provides data input D as data Q as output. When the clock signal is inverted such that MUX 801 selects input I2 as output O, then MUX 801 operates in isolation and effectively "latches" output Q regardless of changes at the D input.

When replacing latch 117, the output of inverter 115 would be provided to input I1 of MUX 801, the output of MUX 801 would provide the ST signal on storage node 120, CK would be provided to the S1 select input of MUX 801, and CB would be provided to S2 selection input of MUX801. When replacing the latch 705, the output of the NAND logic gate 703 is provided to the input I1 terminal of the MUX801, the output terminal of the MUX801 provides the SIB signal on the scan data node 707, CK is provided to the S2 select input terminal of the MUX801, and the CB is provided to the S1 selection input of MUX801.

FIG. 9 shows a block diagram of an integrated circuit (IC) 900 incorporating scannable fast dynamic registers 901 , 905 , and 909 each implemented in accordance with scannable fast dynamic register 700 . Although only three scannable fast dynamic registers 901, 905, and 909 are shown, one of ordinary skill in the art may incorporate any number of registers on the IC based on the particular implementation. In addition, each of the illustrated scannable fast dynamic registers 901, 905, and 909 is used to receive a different amount of input data and output a data bit. Those of ordinary skill in the art should know that multiple registers can be provided in parallel based on the register size. registers to store any number of bits simultaneously.

One or more data inputs DNIN are provided to the data or “DN” input of scannable fast dynamic register 901 which has an output QB terminal provided to combinatorial logic circuit 903 . N is any suitable integer greater than zero and may be a single data bit as previously described. Combinational logic circuit 903 has “M” outputs provided to the DMIN input of scannable fast dynamic register 905 which has an output QB terminal provided to combinatorial logic circuit 907 . M is any suitable integer greater than zero and may be a single data bit as previously described. The P outputs of the combinatorial logic circuit 907 are provided to the DPIN input terminals of the scannable fast dynamic register 909, and the scannable fast dynamic register 909 has an output QB end provided to the combinatorial logic circuit 911, and the combinatorial logic circuit 911 has Q data output terminals provided. DQOUT output terminal. P and Q are each any suitable integer greater than zero, and either may be a single data bit as previously described. The clock signal CLK is provided to the clock input of each of the scannable fast dynamic registers 901 , 905 and 909 .

As shown, a scan enable signal SE is provided from an external source via an IC pin, terminal SE is provided to the SE enable input of each of the scannable fast dynamic registers 901 , 905 and 909 . The input scan signal SCANIN is provided to the scan input SI of the scannable fast dynamic register 901 . As shown, SCANIN can be provided from an external IC pin. The QB output of scannable fast dynamic register 901 is provided to the SI input of scannable fast dynamic register 905 , which has a QB output provided to the SI input of scannable fast dynamic register 909 . The QB output of scannable fast dynamic register 909 provides the output scan signal SCANOUT. As depicted, the SCANOUT signal can be provided externally via an IC pin.

During normal operation, SE is pulled low to effectively disable the SI input of the scannable fast dynamic registers 901 , 905 and 909 . DNIN can be generated on IC 100, or provided from an external source via a corresponding IC pin or similar. During normal operation, registers 901 , 905 and 909 and combinational logic circuits 903 , 907 and 911 perform at least one function of IC 100 . DQOUT may be provided to another device on the chip, or it may be provided to an external device via a corresponding IC pin or similar. As will be appreciated by those of ordinary skill in the art, during each cycle of CLK, each combinational logic circuit 903, 907, and 911 may incorporate combinational logic, and may scan fast dynamic registers 901, 905, and 909 to store the circuit's state.

A scanning capability may be provided for detection purposes to functionally detect the operation of IC 100 . During scan mode, setting SE high effectively disables the data input DN and enables each SI input of each scannable fast dynamic register 901 , 905 and 909 . In this manner, the fast dynamic registers 901, 905 and 909 may be scanned in a serial daisy chain between SCANIN and SCANOUT during scan mode. Test vectors or similar data are provided via the SCANIN input and clocked via CLK to load the scannable fast dynamic registers 901, 905 and 909 with the test vector values. Depending on the specific test function, SE may be temporarily pulled low and IC 100 operated for one or more CLK cycles. SE is then pulled high during the subsequent cycle of CLK, and the information stored in the scannable fast dynamic registers 901, 905 and 909 is output via SCANOUT, and the output test vectors are then checked to confirm the test results.

At least one benefit of the scannable fast dynamic register 700 configuration is that the path of the scan data to the output is static and partially bypasses the dynamic nature of the register to enable injection of scan input data. An important benefit is to minimize the interaction of scanning circuits with dynamic circuits while retaining the original high-speed characteristics for non-scanning operations. The flash registers shown and described herein combine the simple function of inverting one or more data inputs DN to register a single output QB. Many other logic functions of more complex functions can be built into fast registers, and the scan injection method disclosed in this specification can be similarly incorporated into other registers with more complex functions.

Although the invention has been described in some detail with reference to certain embodiments, other embodiments and variations are possible and contemplated. For example, circuits described herein may be implemented in any suitable manner including logic devices or circuits, etc., and any number of functions described for logic circuits may be implemented in software or firmware within an integrated device. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other embodiments for carrying out the same purposes of the present invention without departing from the spirit and scope of the present invention. structure, but these equivalent modifications should be included in the patent scope of the present invention.

Claims (38)

1. a quick dynamic register, comprising:

Data block, is coupled between the first precharge node and electric discharge node, wherein, and when clock node is from the first clock statusWhile being transformed into second clock state, described data block receives at least one data input and passes through described the first precharge jointPoint is moved described electric discharge node to assess;

Pre-charge circuit, when described clock node is during in described the first clock status, by the second precharge node and describedOne precharge node is both pre-charged to high potential, in the time that described clock node is transformed into described second clock state, stopsThe first precharge node and move described electric discharge node to electronegative potential described in precharge, and when described the first precharge nodeKeep high potential after described clock node is transformed into described second clock state time, by described the second precharge node electric dischargeTo electronegative potential;

Transparent latch, has and is couple to the latch input of described the second precharge node and is coupled to memory nodeOutput, wherein, when described clock node is during in described second clock state, described transparent latch is for by described secondThe state transfer of precharge node is transparent to described memory node, and wherein when described clock node is in described firstWhen clock status, memory node described in described transparent latch latch; And

Output logic gate, the state-driven output node based on described the second precharge node and described memory node is to a shapeState.

2. quick dynamic register as claimed in claim 1, further comprises multiple inverter buffers, is coupled in institute by serialState between the described latch input of the second precharge node and described transparent latch.

3. quick dynamic register circuit as claimed in claim 1, further comprises:

Phase inverter, has the input that is couple to described clock node and the output that is couple to inversion clock node; And

Wherein, described transparent latch comprises:

The first and second transistors, each has and is coupled between described latch input and described latch outputA pair of current terminal, wherein, described the first transistor has the control input end that is couple to described clock node, and wherein,Described transistor seconds has the control input end that is couple to described inversion clock node; And

Retainer circuit, is couple to described clock node, described inversion clock node and the output of described latch, when describedClock node is in the time of described the first clock status, and retainer circuit operation is to maintain the state of described output node.

4. quick dynamic register as claimed in claim 3, wherein, described retainer circuit comprises:

The 3rd transistor, has the first current terminal that is couple to supply voltage node, and have the second current terminal andControl terminal;

The 4th transistor, has the first current terminal that is couple to described the 3rd transistorized described the second current terminal, hasBe couple to the second current terminal of described latch output, and there is the control terminal that is couple to described clock node;

The 5th transistor, has the first current terminal that is couple to described latch output, has the second current terminal, andThere is the control terminal that is couple to described inversion clock node;

The 6th transistor, has the first current terminal that is couple to described the 5th transistorized described the second current terminal, hasBe couple to the second current terminal of lower supply voltage node, and there is control terminal; And

Phase inverter, has the input that is couple to described latch output, and is couple to the described the 3rd and the 6th transistorThe output of described control terminal.

5. quick dynamic register as claimed in claim 1, wherein, described data block comprises multiple N channel transistors, eachIndividual have the first current terminal that is couple to described the first precharge node, and each has and is couple to described precharge nodeThe second current terminal, and each has one of the corresponding control terminal that receives the input of multiple data.

6. quick dynamic register as claimed in claim 1, wherein, described data block comprises multiple N channel transistors, eachIndividual have serial and be coupled in a pair of current terminal between described the first precharge node and described electric discharge node, and eachThere is one of the corresponding control terminal that receives the input of multiple data.

7. quick dynamic register as claimed in claim 1, wherein, described pre-charge circuit comprises:

The first p channel transistor, has the first current terminal that is couple to supply voltage node, has and is couple to described firstThe second current terminal of precharge node, and there is the control terminal that is couple to described clock node;

The one N channel transistor, has the first current terminal that is couple to described electric discharge node, has and is couple to lower supply voltageThe second current terminal of node, and there is the control terminal that is couple to described clock node; And

Retainer circuit, is coupled between described upper supply voltage node and lower supply voltage node, and is further couple toDescribed the first precharge node and described clock node, wherein, when described clock node is during in described second clock state, instituteState retainer circuit operation to maintain the state of described the first precharge node.

8. quick dynamic register as claimed in claim 1, wherein, described pre-charge circuit comprises:

The first p channel transistor, has the first current terminal that is couple to supply voltage node, has and is couple to described secondThe second current terminal of precharge node, and there is the control terminal that is couple to described clock node;

The one N channel transistor, has the first current terminal that is couple to described the second precharge node, has the second current terminalSon, and there is the control terminal that is couple to described the first precharge node;

Phase inverter, has and is couple to the input of described clock node and is couple to described the of a described N channel transistorThe output of two current terminals; And

Retainer circuit, is coupled between described supply voltage node and lower supply voltage node, and is further couple to instituteState the first and second precharge nodes and described clock node, wherein, be transformed into described second clock shape at described clock nodeAfter state, described retainer circuit operation is to change the state of described the second precharge node to the phase of described the first precharge nodeOpposite state.

9. quick dynamic register as claimed in claim 1, wherein, described output logic gate comprises logic AND type logicDoor.

10. quick dynamic register circuit as claimed in claim 1, further comprises:

Scan enable piece, is coupled between described the first precharge node and described electric discharge node, wherein, and described scan enable pieceThe input of reception scan enable, and when described scan enable input being set and working as described clock node from described the first clock statusWhile being transformed into described second clock state, move described the first precharge node to described electric discharge node;

Select circuit, be inserted between the described input of described the second precharge node and described transparent latch, wherein, instituteState and select circuit to there is the first input end that is couple to described the second precharge node, have and be couple to the of scan-data nodeTwo inputs, and there is the output of the described latch input that is couple to described transparent latch; And

The second transparent latch, has the input that receives scan-data input and the output that is couple to described scan-data nodeEnd, wherein, when described clock node is in described the first clock status and in the time described scan enable is set inputs, described theIt is transparent that two transparent latch are input to described scan-data node for the described scan-data of transmission, wherein, and when cancellation is establishedPut the input of described scan enable and when described clock node is during in described the first clock status, described the second transparent latchForcing described scan-data node is high potential, and wherein, when described clock node is during in described second clock state, and instituteState the final state that the second transparent latch keeps described scan-data node.

11. 1 kinds of integrated circuits, comprising:

Combinational logic, provides at least one data input;

Clock node; And

Dynamic register fast, comprising:

Data block, is coupled between the first precharge node and electric discharge node, wherein, described data block receive described at least oneData input, and in the time that described clock node is transformed into second clock state from the first clock status, by by described firstPrecharge node is moved described electric discharge node to and is assessed;

Pre-charge circuit, when described clock node is during in described the first clock status, by the second precharge node and describedBoth are precharged as high potential one precharge node, in the time that described clock node is transformed into described second clock state, stop pre-Charge described the first precharge node and move described electric discharge node to electronegative potential, and when being transformed at described clock nodeAfter described second clock state and when described the first precharge node keeps high potential, by described the second precharge node electric dischargeFor electronegative potential;

Transparent latch, has the latch input that is couple to described the second precharge node and the output that couples memory nodeEnd, wherein, when described clock node is during in described second clock state, described transparent latch is described second pre-for transmittingThe state of charge node is transparent to described memory node, and wherein, when described clock node is in described the first clockWhen state, memory node described in described transparent latch latch; And

Output logic gate, the state-driven output node based on described the second precharge node and described memory node is to a shapeState.

12. integrated circuits as claimed in claim 11, further comprise multiple inverter buffers, and serial is coupled in described secondBetween the described latch input of precharge node and described transparent latch.

13. integrated circuits as claimed in claim 11, further comprise:

Phase inverter, has the input that is coupled in described clock node and the output that is coupled in inversion clock node; And

Wherein, described transparent latch comprises:

The first and second transistors, each has and is coupled between described latch input and described latch outputA pair of current terminal, wherein, described the first transistor has the control input end that is couple to described clock node, and wherein,Described transistor seconds has the control input end that is couple to described inversion clock node; And

Retainer circuit, is couple to described clock node, described inversion clock node and described latch output, when describedClock node is in the time of described the first clock status, and retainer circuit operation is to maintain the state of described output node.

14. integrated circuits as claimed in claim 13, wherein, described retainer circuit comprises:

The 3rd transistor, has the first current terminal that is couple to supply voltage node, and have the second current terminal andControl terminal;

The 4th transistor, has the first current terminal that is couple to described the 3rd transistorized described the second current terminal, hasBe couple to the second current terminal of described latch output, and there is the control terminal that is couple to described clock node;

The 5th transistor, has the first current terminal that is couple to described latch output, has the second current terminal, and toolThere is the control terminal that is couple to described inversion clock node;

The 6th transistor, has the first current terminal that is couple to described the 5th transistorized described the second current terminal, hasBe couple to the second current terminal of lower supply voltage node, and there is control terminal; And

Phase inverter, have be couple to the input of described latch output and be couple to the described the 3rd and the 6th transistorized described inThe output of control terminal.

15. integrated circuits as claimed in claim 11, wherein, described pre-charge circuit comprises:

The first p channel transistor, has the first current terminal that is couple to supply voltage node, has and is couple to described firstThe second current terminal of precharge node, and there is the control terminal that is couple to described clock node;

The one N channel transistor, has the first current terminal that is couple to described electric discharge node, has and is couple to lower supply voltageThe second current terminal of node, and there is the control terminal that is couple to described clock node; And

Retainer circuit, is coupled between described upper supply voltage node and lower supply voltage node, and is further couple toDescribed the first precharge node and described clock node, wherein, when described clock node is during in described second clock state, instituteState retainer circuit operation to maintain the state of described the first precharge node.

16. integrated circuits as claimed in claim 11, wherein, described pre-charge circuit comprises:

The first p channel transistor, has the first current terminal that is couple to supply voltage node, has and is couple to described secondThe second current terminal of precharge node, and there is the control terminal that is couple to described clock node;

The one N channel transistor, has the first current terminal that is couple to described the second precharge node, has the second current terminalSon, and there is the control terminal that is couple to described the first precharge node;

Phase inverter, has and is couple to the input of described clock node and is couple to described the of a described N channel transistorThe output of two current terminals; And

Retainer circuit, is coupled between described supply voltage node and lower supply voltage node, and is further couple to instituteState the first and second precharge nodes and described clock node, wherein, be transformed into described second clock shape at described clock nodeAfter state, described retainer circuit operation is to change the state of described the second precharge node to the phase of described the first precharge nodeOpposite state.

Deposit the method for data, comprising for 17. 1 kinds:

When clock signal is during in the first clock status, precharge the first precharge node is high potential;

In the time that at least one data input is not assessed, be transformed into after second clock state, at least one in clock signalData inputs is assessed and maintained described the first precharge node is high potential, and is transformed into the when described clock signalTwo clock status and in the time that the input of at least one data is assessed are electronegative potential by the first precharge node electric discharge;

When clock signal is during in the first clock status, the second precharge node is precharged as to high potential;

Be transformed into after the second logic state in clock signal, if the first precharge node keeps high potential, by the second preliminary fillingElectrical nodes electric discharge, for electronegative potential, is high potential otherwise maintain the second precharge node;

When clock signal is during in the first clock status, the state of latch stores node, when clock signal is in second clock shapeWhen state, by the state transfer of the second precharge node to memory node; And

The state of output node is set according to the state of the second precharge node and memory node.

18. methods as claimed in claim 17, wherein, the state of described transmission the second precharge node is to memory node bagDraw together:

Inversion clock signal and the clock signal being inverted is provided;

Conducting is coupled between the second precharge node and memory node, by the first transmission transistor of clock signal control;

Conducting is coupled between the second precharge node and memory node, be inverted second of clock signal control transmits crystalPipe; And

When clock signal is during in the first clock status, keep the state of memory node.

19. methods as claimed in claim 17, further comprise:

The input of reception scan enable

In the time that scan enable input is set and in the time that clock signal is transformed into second clock state, by forcing the first precharge jointPoint discharges into electronegative potential and carrys out bypass data assessment; And

In the time that scan enable input is set, inject the state that scan-data input replaces the second precharge node, wherein, work as clockSignal is in the time of second clock state, and described transmit mode comprises the state transfer of scan-data input to memory node.

20. 1 kinds can scan quick dynamic register, comprise:

Data and scan enable circuit, be coupled between the first precharge node and electric discharge node, and receive at least one numberAccording to input and scan enable input, wherein, in the time that clock node is transformed into second clock state from the first clock status, and work asDescribed data block is assessed or in the time that the input of described scan enable is set, and described data and scan enable circuit are by described theOne precharge node is moved described electric discharge node to, otherwise does not move described the first precharge node to described electric discharge node;

Pre-charge circuit, when described clock node is during in described the first clock status, by the second precharge node and describedOne precharge node is all charged to high potential in advance, in the time that described clock node is transformed into described second clock state, stops prechargeDescribed the first precharge node and move described electric discharge node to electronegative potential, and described clock node is transformed into described secondAfter clock status, in the time that described the first precharge node keeps high potential, described the second precharge node is discharged into electronegative potential;

Select circuit, there is the first input end that is coupled to described the second precharge node, there is the scan-data of being couple to jointThe second input of point, and there is selecteed output;

Memory circuit, has the storage input that receives described selected output, and has the output that is couple to memory nodeEnd, wherein, when described clock node is during in described second clock state, described memory circuit is by the shape of described selected outputState is delivered to described memory node, and wherein, when described clock node is during in described the first clock status, and described store electricityRoad keeps the final state of described memory node;

Scan enable circuit, is included in data and scan enable circuit, in the time that the input of described scan enable is set and work as instituteState clock node in the time of described the first clock status, the state transfer of scanning input is arrived to described scan-data node, when gettingDisappear when described scan enable signals is set and when described clock node is during in described the first clock status, force described scanningBack end is to high potential, and when described clock node is during in described second clock state, keeps described scan-data jointThe final state of point; And

Output logic gate, the state-driven output node of described the second precharge node of foundation and described memory node is to a shapeState.

21. as claimed in claim 20ly scan quick dynamic register, wherein, and described data and scan enable circuit bagDraw together:

Data block, is coupled between described the first precharge node and described electric discharge node, and receives described at least one numberAccording to input; And

Scan enable circuit, is coupled between described the first precharge node and described electric discharge node, and receives described scanningEnable input.

22. as claimed in claim 21ly scan quick dynamic register, and wherein, described scan enable circuit comprises at least oneIndividual N channel transistor, has the first current terminal that is couple to described the first precharge node, has and is couple to described electric discharge jointThe second current terminal of point, and there is the control inputs that receives described scan enable input.

23. as claimed in claim 21ly scan quick dynamic register, and wherein, described data block comprises multiple N raceway groove crystalline substancesBody pipe, its each controlled by one of corresponding multiple data inputs, and be couple to together to carry out logic of propositions meritEnergy.

24. as claimed in claim 20ly scan quick dynamic register, and wherein, described selection circuit comprises that AND type patrolsCollect door.

25. as claimed in claim 20ly scan quick dynamic register, and wherein, described memory circuit comprises transparent latchDevice, has and receives the latch input of described selection output and have the latch output that is couple to described memory nodeEnd.

26. as claimed in claim 25ly scan quick dynamic register, further comprise:

Phase inverter, has the input that is couple to described clock node and the output that is couple to inversion clock node; And

Wherein, described transparent latch comprises the first and second transistors, its each have and be coupled in described latch inputA pair of current terminal between end and described latch output, wherein, described the first transistor has and is couple to described clockThe control inputs of node, and wherein, described transistor seconds has the control inputs that is couple to described inversion clock node.

27. as claimed in claim 20ly scan quick dynamic register, and wherein, described scan enable circuit comprises:

Scan enable logic, has the first input end that receives the input of described scan enable, has and receives described scanning inputThe second input, and there is output; And

The second memory circuit, has the storage input of the described output that is couple to described scan enable logic and has and coupleTo the output of described scan-data node, wherein, when described clock node is during in described the first clock status, described secondMemory circuit by the state transfer of described scanning input to described scan-data node, and wherein when described clock node inWhen described second clock state, described the second memory circuit keeps the final state of described scan-data node.

28. as claimed in claim 27ly scan quick dynamic register, and wherein, described the second memory circuit comprises transparent lockStorage, has the latch input of the described output that is couple to described scan enable logic and has and be couple to described scanningThe latch output of back end.

29. as claimed in claim 28ly scan quick dynamic register, further comprise:

Phase inverter, has the input that is couple to described clock node and the output that is couple to inversion clock node; And

Wherein, described transparent latch comprises the first and second transistors, its each have and be coupled in described latch inputA pair of current terminal between end and described latch output, wherein, described the first transistor has and is couple to described clockThe control input end of node, and wherein said transistor seconds has the control inputs that is couple to described inversion clock nodeEnd.

30. 1 kinds of integrated circuits, comprising:

Clock node and scan enable node, wherein, described scan enable node receives the scan enable letter of beacon scanning patternNumber; And

At least one can scan quick dynamic latch, and each comprises:

Data and scan enable circuit, be coupled between the first precharge node and electric discharge node, and receive at least one numberAccording to input and the scan enable input with the described scan enable signals of reception, wherein, when described clock node is from firstWhen clock status is transformed into second clock state, or in the time of described data block assignment or when described scan enable signals is setTime, described data and scan enable circuit are moved described the first precharge node to described electric discharge node, otherwise not by describedOne precharge node is moved described electric discharge node to;

Pre-charge circuit, when described clock node is during in described the first clock status, by the second precharge node and describedOne precharge node is both charged to high potential in advance, in the time that described clock node is transformed into described second clock state, stops pre-Charge described the first precharge node and move described electric discharge node to electronegative potential, and be transformed into institute at described clock nodeState after second clock state, while only having described the first precharge node to keep high potential, by described the second precharge node electric dischargeTo electronegative potential;

Select circuit, there is the first input end that is couple to described the second precharge node, there is the scan-data of being couple to nodeThe second input, and there is selecteed output;

Memory circuit, has and receives the storage input of described selected output and have the output that is couple to memory node,Wherein, when described clock node is during in described second clock state, described memory circuit is by the state of described selected outputBe delivered to described memory node, and wherein, when described clock node is during in described the first clock status, described memory circuitKeep the final state of described memory node;

Scan enable circuit, is included in data and scan enable circuit, when arrange the input of described scan enable and when described inClock node, in the time of described the first clock status, to described scan-data node, is worked as cancellation by the state transfer of scanning inputDescribed scan enable signals is set and when described clock node is during in described the first clock status, forces described scan-dataNode is to high potential, and when described clock node is during in described second clock state, keeps described scan-data nodeFinal state; And

Output logic gate, the state-driven output node based on described the second precharge node and described memory node is to a shapeState.

31. integrated circuits as claimed in claim 30, further comprise:

Scanning input node and scanning output node;

Wherein, described at least one can scan quick dynamic register and comprise multiple quick dynamic registers that scan;

Wherein, described multiple first scanning that can scan quick dynamic register that scans quick dynamic register is inputtedEnd is couple to described scanning input node;

The scanning that wherein, described multiple last that scan quick dynamic register can be scanned to quick dynamic register is defeatedEnter end and be couple to described multiple previous output node that scans quick dynamic register that scans quick dynamic register;And

Wherein, by described multiple scan quick dynamic register described last can scan the defeated of quick dynamic registerEgress is couple to described scanning output node.

32. integrated circuits as claimed in claim 31, further comprise at least one combined logic block, each combinational logicPiece has and is couple to described multiple previous output joint that scans quick dynamic register that scans quick dynamic registerThe input of point, and each combined logic block has and is couple to described multiple next one that scans quick dynamic registerCan scan more corresponding data of at least one data input pin that scans quick dynamic register of quick dynamic registerAt least one output of input.

33. integrated circuits as claimed in claim 30, wherein, described data and scan enable circuit comprise scan enable electricityRoad, scan enable circuit is coupled between described the first precharge node and described electric discharge node, and is couple to described scanningEnable node.

34. integrated circuits as claimed in claim 33, wherein, described scan enable circuit comprises at least one N raceway groove crystalPipe, at least one N channel transistor has the first current terminal that is couple to described the first precharge node, has the institute of being couple toState the second current terminal of electric discharge node, and there is the control input end that is couple to described scan enable node.

35. integrated circuits as claimed in claim 30, wherein, described selection circuit comprises AND type gate.

36. integrated circuits as claimed in claim 30, wherein, described scan enable circuit comprises:

Scan enable logic, has the first input end that is couple to described scan enable node, has and receives described scanning inputThe second input, and there is output; And

The second memory circuit, the storage input with the described output that is couple to described scan enable logic is couple to havingThe output of described scan-data node, wherein, when described clock node is during in described the first clock status, described second depositsAccumulate road by the state transfer of described scanning input to described scan-data node, and wherein, when described clock node inWhen described second clock state, described the second memory circuit keeps the final state of described scan-data node.

37. integrated circuits as claimed in claim 36, wherein, described the second memory circuit comprises transparent latch, transparent lockStorage has the latch input of the described output that is couple to described scan enable logic, and has and be couple to described scanningThe latch output of back end.

38. integrated circuits as claimed in claim 37, further comprise:

Phase inverter, has the input that is couple to described clock node and the output that is couple to inversion clock node; And

Wherein, described transparent latch comprises the first transistor and transistor seconds, the first transistor and transistor seconds everyOne has a pair of current terminal being coupled between described latch input and described latch output, wherein, described inThe first transistor has the control input end that is couple to described clock node, and wherein said transistor seconds has and is couple toThe control input end of described inversion clock node.