CN103700598A - Method for supporting multiple chip packaging modes - Google Patents
Method for supporting multiple chip packaging modes Download PDFInfo
- Publication number
- CN103700598A CN103700598A CN201310665509.3A CN201310665509A CN103700598A CN 103700598 A CN103700598 A CN 103700598A CN 201310665509 A CN201310665509 A CN 201310665509A CN 103700598 A CN103700598 A CN 103700598A
- Authority
- CN
- China
- Prior art keywords
- pressure welding
- welding point
- chip
- encapsulation
- cabling
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 10
- 238000004806 packaging method and process Methods 0.000 title abstract description 6
- 238000003466 welding Methods 0.000 claims abstract description 35
- 238000012360 testing method Methods 0.000 claims abstract description 18
- 238000005538 encapsulation Methods 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000012856 packing Methods 0.000 claims description 5
- 230000008707 rearrangement Effects 0.000 claims description 4
- 239000002356 single layer Substances 0.000 claims description 2
- 230000001360 synchronised effect Effects 0.000 claims description 2
- 238000011161 development Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1412—Layout
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Measuring Fluid Pressure (AREA)
Abstract
The invention discloses a method for supporting multiple chip packaging modes. Original pressure welding points for packaging and testing a chip are preserved, and at the same time, pressure welding points for achieving other packaging are arranged and distributed, so that the purposes that multiple largest chips can be simultaneously tested at the wafer testing stage and multiple packaging modes can be supported are achieved.
Description
Technical field
The present invention is the method for ic chip package form, relates to a plurality of fields such as integrated circuit (IC) design, production, test and encapsulation.
Background technology
Along with people's variety of life, development information-based, electronicalization process is more and more rapider, and integrated circuit (IC) chip is the basic of these development.Universal along with electronic product, its cost is along with the decline of price becomes more and more harsher, and proposes constantly challenge for the cost of the links such as the production of chip, test, encapsulation.
In the test link of integrated circuit wafer, chip simultaneous test number is more multipair to be reduced manyly in testing cost, but this proposes strict requirement for arranging of chip welding spot, such as single arrangement mode and interval can not be too large.In integrated antenna package link, flip chip bonding encapsulation is just more and more applied with cheaper packaged type, but its solder joint for chip arrange require harsher, such as the spacing between solder joint requires very large.How can, by both organic combinations, for the cost that reduces whole integrated circuit, be significant.
Summary of the invention
In order to reduce the packaging cost of chip, flip chip bonding packing forms is more and more used, traditional flip chip bonding processing mode is: by increasing "one-step"process in encapsulation factory on wafer, growth layer of metal line and corresponding pressure welding point, object is spacing and the size that increases pressure welding point, reaches the requirement of flip chip bonding to pressure welding point.The present invention, in the wafer production stage, be used as specially again arranging of chip welding spot, and the pressure welding point position of the original test of chip and encapsulation remains unchanged by increasing metal level.Like this, save the process procedure of encapsulation factory rewiring, farthest reduced the cost of the front chip of encapsulation, can keep again chip multiple packing forms flexibly simultaneously.
The present invention keeps the home position of chip input and output pressure welding point, and object is for the test of support wafer level and traditional routing encapsulation, as shown in (2) in Fig. 1.At wafer-level test and the encapsulation of traditional routing, all can there is stronger pressure to pressure welding point, and pressure welding point lower floor cabling or circuit after again arranging may be more responsive to stronger pressure ratio, the pressure in the time of can not bearing wafer sort when the pressure of probe and routing encapsulation.In addition, if original pressure welding point marshalling can keep maximum chip simultaneous test examinations when wafer-level test, this will be conducive to reduce testing cost.
When pressure welding point is arranged again, cabling mode (3) is random, and according to flip chip bonding, encapsulation requires to place the pressure welding point of rearrangement (4), and placement location is random.
In the present invention, pressure welding point size, position, the shape of resetting cloth are arbitrarily on chip, and the pressure welding point to partial shape in Fig. 2 is illustrated.
Accompanying drawing explanation
Fig. 1 pressure welding point is reset schematic diagram
Fig. 2 pressure welding point figure for example
Embodiment
Below in conjunction with Figure of description, the specific embodiment of the present invention is elaborated.
As shown in schematic diagram as of the present invention in Fig. 1, (1) represent the one single chip on wafer, (2) represent the pressure welding point that chip input and output are original, from the circuit of chip input/output section close to, be mainly used in test and the encapsulation of chip, (3) represent cabling when pressure welding point is reset, pressure welding point position is afterwards reset in (4) representative.
The original pressure welding point of chip of (2) representative in Fig. 1, arranges compactness and neat, can improve wafer and produce the multi-chip synchronous detecting number of rear test, reduces largely the testing expense of wafer.
In Fig. 1, the pressure point of (3) representative is reset cabling, and it walks line process is random, plays the effect of pressure welding point after connecting the original pressure welding point of chip and resetting, and can utilize single-layer metal also can utilize multiple layer metal to realize and connect.
Pressure welding point in Fig. 1 after the rearrangement of (4) representative, object is that its position can be placed on the optional position of chip in order to support flip chip bonding encapsulation, and shape can be also arbitrary shape, can be square, rectangle, circle, polygon etc., Fig. 2 have illustrated part pressure point shape.
Claims (2)
1. support the circuit of various chips packing forms, by the original pressure welding point of chip, the cabling of resetting pressure welding point and rearrangement pressure welding point three parts, formed, in wafer production process, once complete, there are many group pressure welding point in the chip after production completes, can support multiple method for packing, comprise traditional routing encapsulation and flip chip bonding encapsulation, wherein:
Original pressure welding point is nearer apart from the circuit of chip input/output section, for test and the encapsulation of chip, improves wafer and is producing the multi-chip synchronous detecting number of rear test;
The cabling of resetting pressure welding point connects original pressure welding point and resets pressure welding point;
Rearrangement pressure welding point is placed on the optional position of chip, supports flip chip bonding encapsulation.
2. circuit as claimed in claim 1, the cabling that it is characterized in that resetting pressure welding point can be that single-layer metal can be also multiple layer metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310665509.3A CN103700598A (en) | 2013-12-10 | 2013-12-10 | Method for supporting multiple chip packaging modes |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310665509.3A CN103700598A (en) | 2013-12-10 | 2013-12-10 | Method for supporting multiple chip packaging modes |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103700598A true CN103700598A (en) | 2014-04-02 |
Family
ID=50362088
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310665509.3A Pending CN103700598A (en) | 2013-12-10 | 2013-12-10 | Method for supporting multiple chip packaging modes |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103700598A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110335827A (en) * | 2019-04-19 | 2019-10-15 | 深圳市德名利电子有限公司 | Facilitate the method and apparatus and equipment of chip pin routing by backup pressure welding point |
| WO2022134522A1 (en) * | 2020-12-21 | 2022-06-30 | 长鑫存储技术有限公司 | Testing equipment and testing method |
| US11892499B2 (en) | 2020-12-21 | 2024-02-06 | Changxin Memory Technologies, Inc. | Testing machine and testing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1435872A (en) * | 2003-03-14 | 2003-08-13 | 威盛电子股份有限公司 | Wafer grade testing and salient point process and chip struture with testing pad |
| KR20050106581A (en) * | 2004-05-04 | 2005-11-10 | 삼성전자주식회사 | Structure of flip chip semiconductor package for testing a bump and method of fabricating the same |
| TW200629438A (en) * | 2005-02-01 | 2006-08-16 | Megic Corp | Chip structure with bumps and testing pads |
-
2013
- 2013-12-10 CN CN201310665509.3A patent/CN103700598A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1435872A (en) * | 2003-03-14 | 2003-08-13 | 威盛电子股份有限公司 | Wafer grade testing and salient point process and chip struture with testing pad |
| KR20050106581A (en) * | 2004-05-04 | 2005-11-10 | 삼성전자주식회사 | Structure of flip chip semiconductor package for testing a bump and method of fabricating the same |
| TW200629438A (en) * | 2005-02-01 | 2006-08-16 | Megic Corp | Chip structure with bumps and testing pads |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110335827A (en) * | 2019-04-19 | 2019-10-15 | 深圳市德名利电子有限公司 | Facilitate the method and apparatus and equipment of chip pin routing by backup pressure welding point |
| WO2022134522A1 (en) * | 2020-12-21 | 2022-06-30 | 长鑫存储技术有限公司 | Testing equipment and testing method |
| US11892499B2 (en) | 2020-12-21 | 2024-02-06 | Changxin Memory Technologies, Inc. | Testing machine and testing method |
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| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 102209 Beijing, Beiqijia, the future of science and technology in the south area of China electronic network security and information technology industry base C building, Applicant after: Beijing CEC Huada Electronic Design Co., Ltd. Address before: 100102 Beijing City, Chaoyang District Lize two Road No. 2, Wangjing science and Technology Park A block five layer Applicant before: Beijing CEC Huada Electronic Design Co., Ltd. |
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| COR | Change of bibliographic data | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20140402 |