CN103697874A - Digital drive loop control circuit for quartz tuning fork gyroscope - Google Patents
Digital drive loop control circuit for quartz tuning fork gyroscope Download PDFInfo
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Abstract
A digital drive loop control circuit for a quartz tuning fork gyroscope relates to the field of micro electro mechanical systems and comprises an FPGA (field programmable gate array) module, a D/A chip, a low pass filter, a quartz tuning fork gyroscope drive tuning fork, an amplifying filter, an A/D chip, and a power supply module, wherein the FPGA module outputs a digital sine control signal to the D/A chip and the low pass filter to enable the quartz tuning fork gyroscope to drive the turning fork to vibrate, the quartz tuning fork gyroscope drive tuning fork converts the digital sine control signal into a digital feedback signal through the A/D chip and sends the digital feedback signal to the FPGA module after vibrating, amplifying and filtering, and the FPGA module modulates the frequency and the amplitude of the digital feedback signal so as to control a loop of the quartz tuning fork gyroscope. According to the digital drive loop control circuit for the quartz tuning fork gyroscope, the frequency control precision and the amplitude control precision of the drive loop are relatively high, and the performance of the quartz tuning fork gyroscope is improved.
Description
Technical field
The present invention relates to the quartz tuning-fork gyro in micro electronmechanical field, particularly quartz tuning-fork gyro drives loop control circuit.
Background technology
Quartz tuning-fork gyro belongs to a kind of of micromechanical gyro, has the advantages such as volume is little, low in energy consumption, cost is low, applicable batch production, is widely used in the fields such as spacecraft, platform stance control, guided missile.The signal processing circuit of quartz tuning-fork gyro has two kinds of mimic channel and digital circuits, and with respect to mimic channel, digital circuit has the advantages such as signal is processed flexibly, and noise is little, is not affected by the external environment, reproducible.
Existing quartz tuning-fork gyro digitizer, on hardware, it has adopted the bi-processor architecture of DSP+CPLD, and DSP completes digital signal processing algorithm, and CPLD realizes digital to analog converter, the control of analog to digital converter and communication interface.On algorithm, its digital signal processing algorithm is the order execution algorithm based on C language, adopt the mode of 4 frequency multiplication sparse samplings to driving signal to gather computing, driving signal for 10KHz, requiring the algorithm performance period is 25us, add in algorithm and relate to a large amount of trigonometric function operations, so its calculated performance to dsp processor has very high requirement.Improving sampling rate increases the sampling number of each sinusoidal period, can improve arithmetic accuracy, thereby improves gyro performance, but this just requires to select more high performance dsp processor or improves dsp operation dominant frequency, thereby has increased system cost and power consumption.So prior art is limited by the computing power of processor, the algorithm performance period can not be very fast, affects the precision of algorithm and the performance of gyro.
Summary of the invention
Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, provide a kind of digital quartz tuning-fork gyro to drive loop control circuit, drive the frequency control precision of loop higher, amplitude control accuracy is good, has improved gyro performance.
Technical solution of the present invention is: a kind of digital quartz tuning-fork gyro drives loop control circuit, comprises that FPGA module, D/A chip, low-pass filter, quartz tuning-fork gyro drive tuning fork, amplifilter, A/D chip, power module; Described FPGA module output digital sine controls signal to D/A chip, described D/A chip is converted to analog control signal by digital sine control signal and is sent to low-pass filter, high-frequency signal in described low-pass filter elimination analog control signal is also sent to quartz tuning-fork gyro driving tuning fork, makes quartz tuning-fork gyro drive tuning fork vibration; Quartz tuning-fork gyro driving tuning fork is passed to amplifilter by vibration to carry out after amplification filtering, obtain analog feedback signal and be sent to A/D chip, A/D chip is converted to analog feedback signal digital feedback signal and is sent to FPGA module, FPGA module is carried out Frequency And Amplitude Modulation to digital feedback signal, and send new digital sine and control signal to D/A chip, after low-pass filter, be sent to again quartz tuning-fork gyro and drive tuning fork, realize the loop of quartz tuning-fork gyro is controlled; Described power module is for powering to loop control circuit.
Described FPGA module comprises instruction module, frequency controller, sinusoidal signal generator, amplitude controller, multiplier, totalizer; Instruction module sends given frequency values to frequency controller, sends to tentering value to amplitude controller simultaneously; Described frequency control module receives given frequency values and carries out, after frequency modulation, being sent to sinusoidal signal generator, and forcing function generator produces the sine wave that amplitude unit is 1; Export target amplitude after amplitude controller receives given amplitude and carries out amplitude modulation; Described unit is that 1 sine wave and described target amplitude are sent to totalizer after multiplier multiplies each other, and totalizer obtains digital sine control signal after producing biasing, is sent to D/A chip; Instruction module receives digital feedback signal, and given frequency values, given amplitude and digital feedback signal are sent to totalizer, and totalizer is subtracted each other the practical frequency in digital feedback signal and given frequency by totalizer, obtain frequency modulation input value e
1and be sent to frequency controller and carry out frequency modulation (k); The frequency modulation result of sinusoidal signal generator receive frequency controller to produce new unit be 1 sine wave; Totalizer is subtracted each other the actual measurement amplitude in digital feedback signal and given amplitude by totalizer, obtain phase modulation input amplitude e
2(k) and be sent to amplitude controller and carry out phase modulation, obtain new target amplitude; New unit is that 1 sine wave and new target amplitude are sent to totalizer after multiplier multiplies each other, and totalizer produces and obtains new digital sine control signal after biasing and send, and is sent to D/A chip.
Described FPGA module and host computer communicate by RS422 interface, and described FPGA module is also connected with EPCS chip, for storing data.The present invention compared with prior art beneficial effect is:
(1) the present invention is based on FPGA technology, to quartz tuning-fork gyro, drive loop to carry out Design of digital, the speed restriction while having broken through traditional C language design, has improved gyro and has driven the quality of signal and frequency and the amplitude control accuracy of driving loop.
(2) the present invention is based on FPGA technology, adopt hardware description language to realize the control of A/D, D/A, the generation of sinusoidal signal, frequency control algorithm, amplitude control algolithm etc., convenient and easy, simple and reliable.With respect to the digital quartz tuning-fork gyrosystem of traditional DSP+CPLD dual processor, invention can reduce system bulk, reduces system power dissipation.
Accompanying drawing explanation
Fig. 1 circuit diagram of the present invention;
The algorithm principle figure of FPGA module in Fig. 2 the present invention;
Sinusoidal signal generator theory diagram in Fig. 3 the present invention;
In Fig. 4 the present invention, quartz tuning-fork gyro drives the input and output signal schematic diagram of tuning fork during open loop resonant condition;
The full temperature control curve of Fig. 5 frequency loop of the present invention.
Embodiment
As shown in Figure 1, the present invention includes FPGA module, D/A chip, low-pass filter, quartz tuning-fork gyro driving tuning fork, amplifilter, A/D chip, power module, described FPGA module output digital sine controls signal to D/A chip, described D/A chip is converted to analog control signal by digital sine control signal and is sent to low-pass filter, high-frequency signal in described low-pass filter elimination analog control signal is also sent to quartz tuning-fork gyro driving tuning fork, makes quartz tuning-fork gyro drive tuning fork vibration, quartz tuning-fork gyro driving tuning fork is passed to amplifilter by vibration to carry out after amplification filtering, obtain analog feedback signal and be sent to A/D chip, A/D chip is converted to analog feedback signal digital feedback signal and is sent to FPGA module, FPGA module is carried out Frequency And Amplitude Modulation to digital feedback signal, and send new digital sine and control signal to D/A chip, after low-pass filter, be sent to again quartz tuning-fork gyro and drive tuning fork, realization is controlled the loop of quartz tuning-fork gyro, the driving tuning fork that guarantees gyro is done the vibration of constant amplitude all the time with series resonance frequency.
Power module is for powering to loop control circuit.FPGA module also communicates by RS422 interface with host computer, and FPGA module is also connected with EPCS chip, and EPCS is FPGA specialized configuration chip, for storing the routine data of FPGA module.
As shown in Figure 2, FPGA module comprises instruction module, frequency controller, sinusoidal signal generator, amplitude controller, multiplier, totalizer; Instruction module sends given frequency values to frequency controller, sends to tentering value to amplitude controller simultaneously; Described frequency control module receives given frequency values and carries out, after frequency modulation, being sent to sinusoidal signal generator, and forcing function generator produces the sinusoidal wave sinx that amplitude unit is 1; Export target amplitude A after amplitude controller receives given amplitude and carries out amplitude modulation; Described unit is that 1 sine wave and described target amplitude obtain Asinx and be sent to totalizer after multiplier multiplies each other, totalizer produces biasing b, obtain digital sine control signal Asinx+b, be sent to D/A chip, obtain analog sine control signal Asinx+b, after low-pass filtering, add quartz tuning-fork gyro to drive the input end of tuning fork; Instruction module receives digital feedback signal, and given frequency values, given amplitude and digital feedback signal are sent to totalizer, and totalizer is subtracted each other the practical frequency in digital feedback signal and given frequency by totalizer, obtain frequency modulation input value e
1and be sent to frequency controller and carry out frequency modulation (k); The frequency modulation result of sinusoidal signal generator receive frequency controller to produce new unit be 1 sine wave; Totalizer is subtracted each other the actual measurement amplitude in digital feedback signal and given amplitude by totalizer, obtain phase modulation input amplitude e
2(k) and be sent to amplitude controller and carry out phase modulation, obtain new target amplitude; New unit is that 1 sine wave and new target amplitude are sent to totalizer after multiplier multiplies each other, and totalizer produces and obtains new digital sine control signal after biasing and send, and is sent to D/A chip.Wherein, FPGA module is selected the Cyclone of altera corp III Series FPGA chip, and A/D and D/A chip adopt 16 A/D of high speed and the D/A chip of TI company.
As shown in Figure 3, sinusoidal signal generator comprises phase accumulator and sinusoidal wave searching meter.Utilize the RAM resources making in FPGA to complete a sinusoidal signal look-up table, adopt the output offset of sinusoidal signal look-up table of phase accumulator to carry out addressing, through D/A chip, complete digital-to-analog conversion, then undertaken after low-pass filtering by low-pass filter, produce the adjustable sine wave signal of frequency.Because the starting point in the starting point of each cycle period of phase accumulator and output each cycle of sinusoidal signal is corresponding, so, the initial time of exporting each cycle of sinusoidal signal in FPGA inside, can accurately be caught.Phase accumulator is operated under the clock of 100MHz, and the acquisition accuracy of corresponding sinusoidal signal initial time is 10ns.
As shown in Figure 2, quartz tuning-fork gyro can be equivalent to a resistance while driving tuning fork to be operated in resonant condition, during analog sine control signal Asinx+b process tuning fork, can not produce phase shift, that is to say that phase shift that quartz tuning-fork gyro under resonant condition drives tuning fork is determined by the circuit of FPGA inside modules, the circuit parameter of supposing FPGA inside modules does not change, this phase shift is exactly certain value, so frequency control just can be converted to the control of phase shift.According to the amplitude of phase shift point, be 0, just phase shift can be controlled and is converted to Control of Voltage.Because FPGA inside modules can accurately be caught the initial time of sinusoidal signal, finally based on FPGA design philosophy, convert frequency control to Control of Voltage, by the collection of A/D chip, drive the amplitude of loop output signal phase shift place, with 0 compare, adopt the PI controller of increment type integration separation, regulate the output frequency of sinusoidal signal generator, make this amplitude all-the-time stable 0, thereby guarantee that gyro is operated in series resonance frequency.
As shown in Figure 2, adjusting through frequency controller, the phase shift of loop is certain, drive the phase place of loop output sinusoidal signal crest value accurately to measure, by the collection of A/D chip, drive the crest value of loop output sinusoidal signal, compare with setting value, adopt increment type PI controller, control this crest value and be stabilized in setting value.
Sinusoidal signal generator, utilizes formula (1) to calculate the sine value of 16384 points in 0-2 ∏,
Use 16 DA chips that external reference voltage is 4.096V, during its output 1V, corresponding digital quantity is 16000, X in (1) (n) is multiplied by 16000, after rounding downwards, with the form writing in files of complement code, a sinusoidal truth table completes, truth table is write in the inside ROM of FPGA, corresponding ROM organizational form is 214x6=26214, i.e. 14 bit address lines, 16 position datawires.As Fig. 3, with a phase accumulator, to above-mentioned ROM addressing, the input phase Φ inc of phase accumulator adopts the integer of 32bit to quantize, and input clock is FPGA work clock 14.7456MHz, and the frequency of sine wave output is:
When Φ inc=1,
The resolution of sinusoidal signal generator is 0.00343Hz, and the size of ROM resource in restricted and FPGA is carried out addressing with high 14 of phase accumulator output to ROM.So far, sinusoidal signal generator can output amplitude be 1V, the sine wave that frequency is adjustable.In addition, the sine wave producing based on Fig. 3 principle, the starting point of each cycle period of phase accumulator and the starting point in output each cycle of sinusoidal signal are corresponding, therefore, can catch the initial time in output each cycle of sinusoidal signal in FPGA inside modules.
As shown in Figure 4, assumed curve 1 is that quartz tuning-fork gyro drives the input of tuning fork, and curve 2 be under resonant condition, and quartz tuning-fork gyro drives the output waveform of tuning fork, and two curves are with frequency homophase not.Under series resonance state, curve 1 and 2 phase differential △ Φ are definite values, that is to say, under resonant condition, the amplitude of T1 curve 2 correspondences during the moment is A1=0, from the curve initial time in 1 each cycle (T0), time delay T1, starts A/D and gathers the output that gyro drives loop, if it is not 0, the input of control phase totalizer, until be output as A1=0.The process regulating adopts the PI controller of increment type integration separation, and adjustment process starts, and error is larger, use pure proportional control, suc as formula (4), when error is controlled at after certain limit, introduce integration control, suc as formula (5), the steady-state error that makes system is 0, the input that e in formula (k) is regulator, be the deviation of k moment set-point and actual value, u (k) is the k output of regulator constantly, and Kp is scale-up factor, Ti is integration time constant, and T is control cycle.
u(k)-u(k-1)+K
p[e(k)-e(k)-1] (1)
The specific gyro of take is example, it is 9346.3Hz that its quartz tuning-fork gyro drives tuning fork resonance frequency, by formula (2), drawn the input phase Φ inc=2722307 of phase accumulator, this value is as the input of phase accumulation device, sinusoidal signal generator will produce a sine wave that frequency is 9346.3Hz, this signal drives the input of tuning fork as quartz tuning-fork gyro, the sample frequency that then A/D is set is 460800Hz, gather input signal and output signal that quartz tuning-fork gyro drives tuning fork simultaneously, as shown in Figure 4, curve 1 is input sine wave, curve 2 is sine wave output.By matlab instrument, by function inline () and lsqcurvefit (), come 4 two sinusoidal curves of fitted figure to be:
Curve 1:y(t)=-sin (2 π * 9346.3 * t+1.7) 10
Curve 2:y(t)=-0.37sin (2 π * 9346.3 * t+0.9)+2.5
So phase differential ΔΦ=0.8 of the two
And then
As Fig. 4, the initial time T0 of each sinusoidal period starts, approximately 200 FPGA frequency of operation cycles of time delay 13.6229us(), start the output valve A1 that AD gathers the quartz tuning-fork gyro driving tuning fork in a T1 moment, gather after 32 times, do once on average, this value is the e (k) in (4) formula, (5) formula, and the output of (4) formula, (5) formula is the input phase Φ inc of phase accumulator.Because carry out, after 32 samplings, carry out the once calculating of (4) formula, (5) formula, so the performance period of frequency control algorithm is 32/9346.3x1000 ≈ 3.4ms.
Fig. 5 is that full temperature lower frequency is controlled design sketch, in experimentation, is first warming up to 60 ℃, is then cooled to-40 ℃, is finally warming up to 60 ℃, forms a complete temperature cycles.As seen from the figure, gyro series resonance frequency changes along with temperature change, and the output of frequency controller can be followed the series resonance frequency of gyro.
The output area of D/A chip is 0-4.096V, and formula (1) is changed as shown below:
The sinusoidal wave output area of amplitude controller is adjusted in 0-4.096, and the target amplitude of setting quartz tuning-fork gyro driving tuning fork sine wave output is 3.6V, as Fig. 5, namely regulates A value in above formula, makes the amplitude stability in the T2 moment sinusoidal wave 2 at 3.6V.Adopt increment type integration control algorithm, suc as formula (7), the input that e in formula (k) be regulator, i.e. the k deviation of set-point and actual value constantly, u (k) is the output of k moment regulator, and Ti is integration time constant, and T is control cycle.
The specific gyro of take is example, as Fig. 4, the initial time T0 of each sinusoidal period starts, approximately 595 FPGA frequency of operation cycles of time delay 40.3715us(), start the output valve A2 that A/D gathers the gyro driving loop in a T2 moment, gather after 64 times, do once on average, this value is poor with 3.6V, is the input e (k) of formula (7), the output u (k) of formula (7), is A value in formula (6).Because carry out, after 64 samplings, carry out the once calculating of (7) formula, so the performance period of amplitude control algolithm is 64/9346.3x1000 ≈ 6.8ms.Through several times evidence, under full temperature, amplitude controller can make quartz tuning-fork gyro drive tuning fork under full temperature environment, to do the vibration of constant amplitude.
The content not being described in detail in instructions of the present invention belongs to those skilled in the art's known technology.
Claims (3)
1. digital quartz tuning-fork gyro drives a loop control circuit, it is characterized in that: comprise that FPGA module, D/A chip, low-pass filter, quartz tuning-fork gyro drive tuning fork, amplifilter, A/D chip, power module; Described FPGA module output digital sine controls signal to D/A chip, described D/A chip is converted to analog control signal by digital sine control signal and is sent to low-pass filter, high-frequency signal in described low-pass filter elimination analog control signal is also sent to quartz tuning-fork gyro driving tuning fork, makes quartz tuning-fork gyro drive tuning fork vibration; Quartz tuning-fork gyro driving tuning fork is passed to amplifilter by vibration to carry out after amplification filtering, obtain analog feedback signal and be sent to A/D chip, A/D chip is converted to analog feedback signal digital feedback signal and is sent to FPGA module, FPGA module is carried out Frequency And Amplitude Modulation to digital feedback signal, and send new digital sine and control signal to D/A chip, after low-pass filter, be sent to again quartz tuning-fork gyro and drive tuning fork, realize the loop of quartz tuning-fork gyro is controlled; Described power module is for powering to loop control circuit.
2. a kind of digital quartz tuning-fork gyro according to claim 1 drives loop control circuit, it is characterized in that: described FPGA module comprises instruction module, frequency controller, sinusoidal signal generator, amplitude controller, multiplier, totalizer; Instruction module sends given frequency values to frequency controller, sends to tentering value to amplitude controller simultaneously; Described frequency control module receives given frequency values and carries out, after frequency modulation, being sent to sinusoidal signal generator, and forcing function generator produces the sine wave that amplitude unit is 1; Export target amplitude after amplitude controller receives given amplitude and carries out amplitude modulation; Described unit is that 1 sine wave and described target amplitude are sent to totalizer after multiplier multiplies each other, and totalizer obtains digital sine control signal after producing biasing, is sent to D/A chip; Instruction module receives digital feedback signal, and given frequency values, given amplitude and digital feedback signal are sent to totalizer, and totalizer is subtracted each other the practical frequency in digital feedback signal and given frequency by totalizer, obtain frequency modulation input value e
1and be sent to frequency controller and carry out frequency modulation (k); The frequency modulation result of sinusoidal signal generator receive frequency controller to produce new unit be 1 sine wave; Totalizer is subtracted each other the actual measurement amplitude in digital feedback signal and given amplitude by totalizer, obtain phase modulation input amplitude e
2(k) and be sent to amplitude controller and carry out phase modulation, obtain new target amplitude; New unit is that 1 sine wave and new target amplitude are sent to totalizer after multiplier multiplies each other, and totalizer produces and obtains new digital sine control signal after biasing and send, and is sent to D/A chip.
3. a kind of digital quartz tuning-fork gyro according to claim 1 drives loop control circuit, it is characterized in that: described FPGA module and host computer communicate by RS422 interface, and described FPGA module is also connected with EPCS chip, for storing data.
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| CN111964655A (en) * | 2020-07-15 | 2020-11-20 | 北京自动化控制设备研究所 | A quartz tuning fork gyroscope digital drive circuit |
| CN114593723A (en) * | 2020-12-04 | 2022-06-07 | 北京晨晶电子有限公司 | Quartz tuning fork gyroscope circuit and gyroscope |
| CN114839503A (en) * | 2021-01-15 | 2022-08-02 | 北京晨晶电子有限公司 | Test circuit, circuit test method and device |
| CN115127534A (en) * | 2022-09-01 | 2022-09-30 | 中国船舶重工集团公司第七0七研究所 | Quartz gyroscope sine wave phase detection compensation method based on carrier modulation |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111964655A (en) * | 2020-07-15 | 2020-11-20 | 北京自动化控制设备研究所 | A quartz tuning fork gyroscope digital drive circuit |
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| CN114839503A (en) * | 2021-01-15 | 2022-08-02 | 北京晨晶电子有限公司 | Test circuit, circuit test method and device |
| CN115127534A (en) * | 2022-09-01 | 2022-09-30 | 中国船舶重工集团公司第七0七研究所 | Quartz gyroscope sine wave phase detection compensation method based on carrier modulation |
| CN115127534B (en) * | 2022-09-01 | 2022-11-18 | 中国船舶重工集团公司第七0七研究所 | Quartz gyro sine wave phase detection compensation method based on carrier modulation |
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