CN103687289A - Printed wiring board and method for manufacturing printed wiring board - Google Patents
Printed wiring board and method for manufacturing printed wiring board Download PDFInfo
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- CN103687289A CN103687289A CN201310351720.8A CN201310351720A CN103687289A CN 103687289 A CN103687289 A CN 103687289A CN 201310351720 A CN201310351720 A CN 201310351720A CN 103687289 A CN103687289 A CN 103687289A
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- conductive pattern
- printed wiring
- opening
- wiring board
- interlayer insulating
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 23
- 229910000679 solder Inorganic materials 0.000 claims description 52
- 238000003466 welding Methods 0.000 claims description 44
- 238000007747 plating Methods 0.000 claims description 19
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- 239000003054 catalyst Substances 0.000 claims description 12
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- 239000004020 conductor Substances 0.000 description 10
- 239000011162 core material Substances 0.000 description 10
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 9
- 229910052737 gold Inorganic materials 0.000 description 9
- 239000010931 gold Substances 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- 229910052763 palladium Inorganic materials 0.000 description 8
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- 238000009434 installation Methods 0.000 description 2
- 238000011900 installation process Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000010992 reflux Methods 0.000 description 2
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- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 1
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- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
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Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/04—Soldering or other types of metallurgic bonding
- H05K2203/041—Solder preforms in the shape of solder balls
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
The invention provides a printed wiring board and a method for manufacturing the printed wiring board, thereby ensuring connection reliability of bumps while enhancing density of conductive patterns on an outermost layer. The printed wiring board has an interlayer insulation layer, a conductive pattern formed on the interlayer insulation layer, a solder-resist layer formed on the interlayer insulation layer and the conductive pattern and having an opening portion exposing a portion of the conductive pattern and a portion of the interlayer insulation layer around the portion of the conductive pattern, a metal layer formed on the conductive pattern and the interlayer insulation layer which are exposed from the opening, and a bump structure formed in the opening portion of the solder-resist layer.
Description
Technical field
The present invention relates to a kind of printed wiring board, it has by the accumulation horizon that alternately stacked interlayer insulating film and conductive pattern form, and the invention still further relates to a kind of manufacture method of such printed wiring board.
Background technology
In recent years, along with electronic installation becomes more little thinner, exist for the strong demand that is arranged on the thinner printed wiring board on such electronic installation.In order to meet the demand for thinner printed wiring board, need to reduce in the number of accumulation horizon and the layer still less in the printed wiring board of piling up and arrange conductive pattern.Patent documentation 1 discloses and has not formed the structure of ring bank (pad), and this allows to expand for arranging the space of conductive pattern, thereby has increased the number of conductive pattern.
Prior art
Patent is open
Patent documentation 1: TOHKEMY 2010-103435 communique
Summary of the invention
The technical problem to be solved in the present invention
Yet if formed projection on without bank conductive pattern in patent documentation 1, the connection reliability of projection is due to inevitably reducing compared with little contact area between projection and conductive pattern (pad).In addition, because the volume of projection also reduces, therefore, its ability that slows down stress is considered to reduce when the nude film of installing such as IC chip etc.
The present invention is used for addressing the above problem.The object of the present invention is to provide a kind of Printed circuit board and manufacturing methods, make to have guaranteed the connection reliability of projection in the density that increases outermost layer conductive pattern.
Technical scheme of the present invention
An aspect of of the present present invention provides following printed circuit board (PCB), it has interlayer insulating film, is formed on conductive pattern and solder mask on interlayer insulating film, and it has makes at least a portion of conductive pattern and the opening that conductive pattern interlayer insulating film around exposes.In such printed circuit board (PCB), at the conductive pattern exposing from opening and interlayer insulating film, be formed with metal level, and be formed with projection on the metal level in opening.
Effect of the present invention
According in the printed wiring board of first aspect, at least a portion of conductive pattern and conductive pattern interlayer insulating film around exposes from the opening of solder mask.That is, the width of conductive pattern (pad) is set to less than the diameter of the opening of solder mask.Therefore, the situation that is less than pad diameter with the diameter of the opening of solder mask is compared, and the occupied region of pad reduces, thereby allows the high-density arrangement of conductive pattern.In addition, at the conductive pattern exposing from opening and interlayer insulating film, be formed with metal level, and be formed with projection on the metal level in opening.Therefore, projection is formed on the conductive pattern and its interlayer insulating film around in the opening of solder mask.As a result, when forming the projection that can slow down the stress applying during installation process, strengthened the connection reliability of semiconductor element.
Accompanying drawing explanation
Fig. 1 is the view of manufacturing step that the printed wiring board of first embodiment of the invention is shown;
Fig. 2 is the view of manufacturing step that the printed wiring board of first embodiment of the invention is shown;
Fig. 3 is the view of manufacturing step that the printed wiring board of first embodiment of the invention is shown;
Fig. 4 is the view of manufacturing step that the printed wiring board of first embodiment of the invention is shown;
Fig. 5 is the view of manufacturing step that the printed wiring board of first embodiment of the invention is shown;
Fig. 6 is according to the sectional view of the printed wiring board of the first execution mode;
Fig. 7 is the plane graph of outermost conductive pattern;
(A) of Fig. 8 is the sectional view that the position relationship of welding disk and opening is shown; Fig. 8 (B) is plane graph; (C) of Fig. 8 is the view that the admissible error between welding disk and opening is shown;
(A) of Fig. 9 is the zoomed-in view of the circle (Ca) in (A) of Fig. 5; (B) of Fig. 9 is the zoomed-in view of the circle (Cb) in (B) of Fig. 5; (C) of Fig. 9 is the enlarged drawing of the circle (Cc) in Fig. 6;
Figure 10 is the microphoto of projection;
Figure 11 is according to the plane graph of the conductive pattern of the printed wiring board of the modified example of the first execution mode; And
Figure 12 is the view illustrating according to the manufacturing step of the projection of the printed wiring board of the second execution mode.
Embodiment
The first execution mode
Fig. 6 shows the structure of the printed wiring board 10 of first embodiment of the invention.The side that semiconductor element will be installed) and second surface (S) (lower surface: core substrate 30 side that motherboard will be installed) printed wiring board 10 comprises (the F) (upper surface: that has first surface.The first conductive pattern (34F) is formed on the first surface (F) of core substrate 30, and the second conductive pattern (34S) is formed on second surface (S).Via hole conductor 36 is formed in core substrate 30, and the first conductive pattern (34F) is connected by via hole conductor 36 with the second conductive pattern (34S).In the end of via hole conductor 36, the first conductor loops bank (36f) is formed on first surface (F) side, and the second conductor loops bank (36s) is formed on second surface (S) side.The first interlayer insulating film (50F) forms first surface (F) and the first conductive pattern (34F) that covers core substrate 30.It is upper that conductive pattern (58F) is formed on the first interlayer insulating film (50F), and conductive pattern (58F) is connected by via (60F) with the first conductive pattern (34F).Solder mask (70F) forms and covers the first interlayer insulating film (50F) and the first conductive pattern (34F).Solder mask (70F) has opening (71F).Then, solder projection (76F) is formed in opening (71F).And the second interlayer insulating film (50S) forms second surface (S) and the second conductive pattern (34S) that covers core substrate 30.It is upper that conductive pattern (58S) is formed on the second interlayer insulating film (50S), and conductive pattern (58S) is connected by via (60S) with the first conductive pattern (34S).Solder mask (70S) forms and covers the second interlayer insulating film (50S) and the second conductive pattern (34S).Solder mask (70S) has opening (71S).Then, solder projection (76S) is formed in opening (71S).
(A) of Fig. 7 shows the plane graph of the conductive pattern (58F) being formed on the first interlayer insulating film (50F).Chain-dotted line in Fig. 7 (A) shows the opening (71F) of solder mask (70F).In conductive pattern (58F), the part of exposing from the opening (71F) of solder mask (70F) is as welding disk (58FP).For the solder projection (76F) being connected with semiconductor element, be formed on welding disk (58FP).In addition, conductive pattern (58F) has from welding disk (58FP) extended wiring portion (58FL).In the first embodiment, the diameter of opening (71F) is approximately 50 μ m, and the width (W1) of welding disk (58FP) is approximately 15 μ m, and that the width (W1) of welding disk (58FP) is set to the width (W2) of wiring portion (58FL) is roughly the same.Here, in the middle of welding disk (58FP), welding disk (58FP1) has the width (W3) of about 30 μ m.Welding disk (58FP) is roughly rectangle in plan view.The end (58FPP) of conductive pattern (58F) is covered by solder mask (70F).Therefore, guaranteed the adhesiveness between conductive pattern (58F) and the first interlayer insulating film (50F).In some conductive patterns (58F), the boundary member (K) between welding disk (58FP1) and wiring portion (58FL1) is covered by solder mask (70F).Therefore, prevent boundary member (K) contact solder projection (76F), and suppressed to come from cracking and the interior propagation of projection (76F) that boundary member (K) is located.
In addition, expose from the opening (71F) of solder mask (70F) on the surface (H) of welding disk (58FP) the first interlayer insulating film (50F) around.Here, (C) of Fig. 9 is the enlarged drawing of the part the circle (Cc) of Fig. 6 of exposing of the opening (71F) from the solder mask (70F) of first surface (F) side, and Figure 10 is the microphoto of this part.As mentioned above, interlayer insulating film (50F) and end (58FP) expose from the opening (71F) of solder mask (70F).The surface of the interlayer insulating film (50F) exposing from opening (71F) is roughened.The bight of end (58FP) forms and in cross sectional view, is roughly arc.Therefore,, when printed wiring board has been increased thermal history, the stress being applied on the bight of welding disk (58FP) is alleviated.Therefore, think the cracking at the place, bight that suppressed to come from welding disk (58FP) and the propagation in solder projection (76F).The metal level 80 consisting of nickel coating 72 and Gold plated Layer 74 is formed on the interlayer insulating film (50F) and welding disk (58FP) exposing from opening (71F).The surface curvature of the metal level 80 on welding disk (58FP) for being roughly semicircle in cross sectional view.And, metal level 80 form its thickness in end the bight place of (58FP) thinner, and its relative thickness increases on the upper surface of welding disk (58FP).The solder projection (76F) forming on metal level 80 is filled in opening (71F) and does not leave any gap, and contacts with the whole side surface of opening (71F).
(A) of Fig. 8 is the sectional view that the position relationship of welding disk (58FP) and opening (71F) is shown, and Fig. 8 (B) is plane graph.Their position is provided so that the center (C) of opening (71F) and the center in a lateral direction through welding disk (58FP) and the dummy line (C2) of extending in a longitudinal direction intersect.By such setting, with respect to the left part of projection (76F) and the right part of projection (76F) at the center (C2) of the welding disk on direction of principal axis, become symmetry.Therefore, stress is not concentrated partly, and more easily guarantees the connection reliability of projection (76F).
(C) of Fig. 8 shows the admissible error between welding disk (58FP) and opening (71F).Opening (71F) shows the opening that there is no error.Between opening (71F) and the sidewall of welding disk (58FP), be formed with distance (T) ((50-15) ÷ 2=17.5 μ m).(71F ') shows have the margin of error opening of (t).In the first embodiment, the margin of error (t) is set to less than distance (T).
In the printed wiring board of the first execution mode, do not use the circular pad (158P) of the prior art shown in (B) of Fig. 7, but as pad (welding disk (58FP): width (w1)) and other wiring (58FL) (width (W1)) form and there is roughly the same width.Here, in the prior art, the interval between conductive pattern (D2) inevitably increases (D2 > D1) to keep the insulation distance (d2) between circular pad (158P) and conductive pattern 158
.On the contrary, in the first embodiment, welding disk (58FPP) is rectangular shape, and its width is roughly identical with the width of wiring portion, as shown in Fig. 7 (A).Therefore, the distance (d1) between welding disk (58FPP) is identical with above-mentioned (d2), and the interval between conductive pattern (D1) becomes and is less than above-mentioned (D2).That is, in the first embodiment, compared with prior art, the number of the conductive pattern of per unit area can increase, thereby allows the high-density arrangement of conductive pattern.Conventionally, in the printed wiring board of semiconductor element will be installed, scattered and increase gradually towards the outermost layer (orlop interlayer insulating film) of motherboard side by the outermost layer (the superiors' interlayer insulating film) being close to below semiconductor element in the interval of conductive pattern, thereby the thin electrode of semiconductor element is connected to the electrode of motherboard side.Therefore, the density of the superiors' conductive pattern is the highest, thereby further increase, requires the density of the conductive pattern of the highdensity the superiors.In addition, the diameter of the opening (71F) by solder mask (70F) is set to be greater than the width of conductive pattern (58F), if there is the accuracy error relevant to conductive pattern in the forming process of opening (71F), more easily expose conductive pattern (58F) (welding disk).As a result, more easily guarantee being connected of solder projection (76F) and conductive pattern (58F) (welding disk), and realized betwixt enough connection reliability.In addition, metal level 80 is formed on the conductive pattern and interlayer insulating film exposing from the opening of solder mask (70F) (71F), and solder projection (76F) is formed on metal level 80.Therefore,, in the opening (71F) of solder mask (70F), solder projection is formed on conductive pattern and conductive pattern interlayer insulating film around.As a result, guarantee the connection reliability of semiconductor element, made more easily to form the projection that can alleviate stress in installation process.
The manufacture method of the printed wiring board 10 in Fig. 6 has been shown in Fig. 1～6.
(1) insulated substrate 30 is original materials, its thickness be 0.2mm and by by the core material such as glass cloth and glass epoxy resin or BT(Bismaleimide Triazine) resin is immersed in and comes together to manufacture (Fig. 1 (A)).From upper surface (first surface (F)) side and lower surface (second surface (S)) side, use laser to be formed for through hole 31(Fig. 1 of via hole conductor (B)).
(2) on the upper surface of insulated substrate 30, apply palladium catalyst (being manufactured by Atotech), and carry out electroless plating copper to form electroless plating copper film (protective layer) 32(Fig. 1 that 0.6 μ m is thick (C) on the upper surface at substrate and the sidewall for the through hole 31 of via hole conductor).
(3) then, stacked commercially available desciccator diaphragm on two surfaces of insulated substrate 30, and form anti-plating agent 35(Fig. 2 (A) by exposing and developing).
(4) carry out electrolysis plating with in through hole 31 and (B) that in the part that does not form anti-plating agent 35 of substrate 30, form electrolytic copper plating film 33(Fig. 2).
(5) then, using after amine aqueous solution removes anti-plating agent 35, utilizing the etching solution that mainly comprises copper chloride (II) to dissolve and remove the electroless plating film 32 that is formed with anti-plating agent with formation, to comprise the first conductive pattern (34F) and second conductive pattern (34S) (Fig. 2 (C)) of the first conductor loops bank (36f) and the second conductor loops bank (36s).
(6) do not comprise core material and be slightly less than resin molding (the trade name ABF-45SH for interlayer insulating film of substrate, by Ajinomoto, manufactured) be disposed on the upper surface (first surface) and lower surface (second surface) of substrate 30, tentatively press and by after size cutting, use vacuum layer depressor to carry out lamination.Therefore, the first interlayer insulating film (50F) and the second interlayer insulating film (50S) (Fig. 2 (D)) have been formed.
(7) next, use CO2 gas laser, in interlayer insulating film (50F, 50S), form via opening (51F, 51S) (Fig. 3 (A)).
(8) substrate that has a via opening (51F, 51S) is immersed in 80 ℃ of solution of the permanganic acid that comprises 60g/L 10 minutes to remove the particle existing on the upper surface of interlayer insulating film (50F, 50S).Therefore the upper surface of interlayer insulating film (50F, 50S) that, comprises the inwall of via opening 51 is roughened (not shown in FIG.).
(9) next,, after above-mentioned processing, substrate is immersed in neutralization solution (being manufactured by Shipley) and water cleans.In addition,, by apply palladium catalyst on the coarse surface of substrate, catalyst core is attached in the upper surface of interlayer insulating film and the inner wall surface of via opening.
(10) next, the substrate that is attached with catalyst is immersed in the Co. by C.Uyemura &, Ltd. in the electroless plating copper solution (Thru-cup PEA) of manufacturing, thereby on whole coarse surface, form the electroless plating copper film of the thickness with 0.3～3.0 μ m.Therefore, obtained following substrate, it has (B) that is formed on the electroless plating copper film 52(Fig. 3 on first interlayer insulating film (50F) of the inner wall surface that comprises via opening (51F, 51S) and the upper surface of the second interlayer insulating film (50S)).
(11) the commercially available photosensitive desciccator diaphragm of lamination on the substrate that is formed with electroless plating copper film 52, and arrange that mask and expose/development treatment are to form anti-plating agent 54(Fig. 3 (C)).
(12) utilize the water cleaning base plate of 50 ℃ to clean and degreasing.Utilizing after water cleans, further utilize sulfuric acid to carry out cleaning base plate.Then, carry out electrolysis plating to form electrolytic copper plating film 56(Fig. 4 that 15 μ m are thick (A) in the part not forming anti-plating agent 54).
(13) in addition, utilizing after 5%KOH solution removes anti-plating agent 54, using the mixed solution of sulfuric acid and hydrogen peroxide to etch away electroless plating film below anti-plating agent to form conductive pattern (58F, 58S) and via (60F, 60S) (Fig. 4 (B)).Then, the upper surface of conductive pattern (58F, 58S) and via (60F, 60S) is carried out to alligatoring.
(14) next,, on two surfaces of multiwiring board, commercially available welding resistance compound is applied for to 20 μ m thick and be dried.Then, the thick photomask of 5mm with the pattern of welding resistance peristome is adhered to solder mask, be exposed to UV ray and utilize DMTG solution to develop.Therefore, in upper surface side, formed the opening (71F) with small diameter, and formed and there is larger-diameter opening (71S) (Fig. 4 (C)) in lower face side.The conductive pattern (58F) exposing from opening (71F) has formed welding disk (58FP).In addition, utilize heat treatment for solidification solder mask, and formed and there is opening and thickness is the solder mask (70F, 70S) of 15～25 μ m.
(15) in the opening (71F) of solder mask (70F), carry out oxygen plasma treatment, and the surface of the interlayer insulating film exposing (50F) is roughened (Fig. 5 (A)) in opening.(A) of Fig. 9 is the enlarged drawing of the part in the circle (Ca) in (A) of Fig. 5.
(16) substrate that next, has a solder mask (70F, 70S) is immersed in electroless plating nickel solution to form the thick nickel coating 72 of 5 μ m in peristome (71F, 71S).Then, substrate is further immersed in electroless plating gold solution to form Gold plated Layer 74(Fig. 5 that 0.03 μ m is thick (B) on nickel coating 72).During this period, due to residual palladium catalyst the whole part exposing from peristome (71F), therefore, in the whole part of exposing from peristome (71F), form the metal level of being made by nickel coating 72 and Gold plated Layer 74.(B) of Fig. 9 is the enlarged drawing of a part for the circle (Cb) in (B) of Fig. 5.Replacement nickel-Jin layer, the individual layer of also can form three layers of being made by nickel-palladium-Jin layer, for example, being made by tin or noble metal (, gold, silver, palladium or platinum).As mentioned above, the surface curvature of metal level 80 for to have semicircular sectional shape on welding disk (58FP).In addition, the surface curvature of Gold plated Layer 74 is for to have less thickness in the end of welding disk (58FP).
(17) scaling powder (not shown in FIG.) is being applied to opening (71F, after 71S), it is upper that solder ball (77Fb) is loaded in the opening (71F) of solder mask (70F), and solder ball (77Sb) is loaded in the opening (71S) of lower solder mask (70S) (Fig. 5 (C)).Next, reflux on upper surface, to form solder projection (76F) and form up and down solder projection (76S) (Fig. 6) at lower surface.In the reflow treatment of solder ball (77Fb), due to the high solderability of above-mentioned Gold plated Layer 74, be formed on solder projection (76F) in Gold plated Layer 74 and be filled in opening (71F) and there is no leaving space, and all side surfaces of contact openings (71F).
Semiconductor element mounting, on printed wiring board 10, and refluxes and makes the welding disk of printed wiring board and the electrode of semiconductor element be connected (not shown in the accompanying drawings) by solder projection (76F).
According in the manufacture method of the printed wiring board of the first execution mode, forming solder mask (70F) afterwards, alligatoring is carried out in the surface of the interlayer insulating film (50F) exposing from opening (71F).Then, metal level is formed on the coarse surface of interlayer insulating film, and projection is formed on metal level.Therefore, projection is enhanced with the connection reliability of the part (interlayer insulating film) of exposing from opening (71F).
The first modified example of the first execution mode
(A) of Figure 11 is according to the plane graph of the conductive pattern (58F) of the printed wiring board of the first modified example of the first execution mode.In the first modified example of the first execution mode, welding disk (58FP) is formed in rectangular pads portion (58FPP).In the first modified example of the first execution mode, due to the wider width of welding disk (58FP), therefore between welding disk (58FP) and projection, strengthened connection reliability.
The second modified example of the first execution mode
(B) of Figure 11 is according to the plane graph of the conductive pattern (58F) of the printed wiring board of the second modified example of the first execution mode.In the second modified example of the first execution mode, do not form rectangular pads portion.In the second modified example of the first execution mode, further strengthened the density of conductive pattern.
The second execution mode
Figure 12 shows according to the manufacture method of the printed wiring board of the second execution mode.In the first execution mode that (B) with reference to figure 4 describes, remove electroless plating film below anti-plating agent when forming conductive pattern (58F), use the palladium catalyst of the catalyst core that acts on electroless plating sparsely to remain in the upper and residual amount of interlayer insulating film (50F) and do not cause short circuit (Figure 12 (A)).Then, due to palladium catalyst, upper (B) that forms nickel coating 72 and Gold plated Layer 74(Figure 12 of interlayer insulating film (50F) exposing in the opening (71F) of solder mask (70F)).Afterwards, with the same in the first execution mode, in opening 71, form projection (76F) (Figure 12 (C)).
According in the manufacture method of the printed wiring board of the second execution mode, owing to when forming conductive pattern (58F), palladium catalyst being remained on interlayer insulating film (50F), therefore, on the surface by the interlayer insulating film that exposes in the opening at solder mask (71F), plate processing and utilizing palladium catalyst and form metal level (plated nickel film 72 and gold-plated film 74).That is, projection (76F) is formed on the whole part that the opening (71F) from solder mask exposes, and has realized the effect identical with the first execution mode.
Description of reference numerals
30 core substrates
34F, 34S conductive pattern
50F, 50S interlayer insulating film
58F, 58S conductive pattern
58FP welding disk
60F, 60S via conductor
70F, 70S solder mask
80 metal levels
76F projection
Claims (11)
1. a printed wiring board, described printed wiring board comprises:
Interlayer insulating film;
Conductive pattern, described conductive pattern is formed on described interlayer insulating film; And
Solder mask, described solder mask has opening, and described opening makes at least a portion of described conductive pattern and is positioned at this conductive pattern described interlayer insulating film around to expose,
Wherein, at the described conductive pattern exposing from described opening and described interlayer insulating film, be formed with metal level; And
On described metal level in described opening, be formed with projection.
2. printed wiring board according to claim 1, wherein, described metal level is formed on the whole part of exposing from described opening.
3. printed wiring board according to claim 1, wherein, the whole sidewall contact of described projection and described opening.
4. printed wiring board according to claim 1, wherein, the described metal level being formed on described conductive pattern has curved surface.
5. printed wiring board according to claim 1, wherein, described conductive pattern has welding disk and wiring portion, and described projection is formed on described welding disk, and described wiring portion extends from described welding disk, and described welding disk is roughly rectangle in plan view.
6. printed wiring board according to claim 5, wherein, the bight of described welding disk is roughly arc in cross sectional view.
7. printed wiring board according to claim 5, wherein, the width of described wiring portion and the width of described welding disk are roughly the same.
8. printed wiring board according to claim 5, wherein, described welding disk axially on the center that is centered close to described opening.
9. a manufacture method for printed wiring board, described manufacture method comprises:
Form interlayer insulating film;
On described interlayer insulating film, provide catalyst;
On described interlayer insulating film, form electroless plating film;
On described electroless plating film, form the anti-plating agent with predetermined pattern;
On its of described electroless plating film, do not form in the part of described anti-plating agent and form electrolytic film plating;
By removing described anti-plating agent and removing the described electroless plating film exposing from described electrolytic film plating, form conductive pattern; And
Form solder mask, described solder mask has opening, and described opening exposes for the described interlayer insulating film that makes at least a portion of described conductive pattern and be positioned at the surrounding of this conductive pattern,
Wherein, at the described conductive pattern exposing from described opening and described interlayer insulating film, form metal level, and form projection on the described metal level in described opening.
10. the manufacture method of printed wiring board according to claim 9, wherein, after formation has the described solder mask of opening, carries out roughening to the surface of exposing from described opening of described interlayer insulating film.
The manufacture method of 11. printed wiring boards according to claim 9, wherein, when removing the described electroless plating film exposing from described electrolytic film plating, makes described catalyst residue on described interlayer insulating film.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201261694983P | 2012-08-30 | 2012-08-30 | |
| US61/694,983 | 2012-08-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103687289A true CN103687289A (en) | 2014-03-26 |
| CN103687289B CN103687289B (en) | 2016-11-30 |
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| CN111755223A (en) * | 2019-03-27 | 2020-10-09 | 株式会社村田制作所 | Multilayer metal film and inductor component |
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| CN1276090A (en) * | 1997-10-30 | 2000-12-06 | 株式会社日产制作所 | Semiconductor device and method for manufacturing the same |
| US6228466B1 (en) * | 1997-04-11 | 2001-05-08 | Ibiden Co. Ltd. | Printed wiring board and method for manufacturing the same |
| JP2004022713A (en) * | 2002-06-14 | 2004-01-22 | Dainippon Printing Co Ltd | Multilayer wiring board |
| CN1630459A (en) * | 1996-12-19 | 2005-06-22 | 揖斐电株式会社 | Printed wiring board and method for manufacturing the same |
| TW200913804A (en) * | 2007-05-31 | 2009-03-16 | Kyocera Slc Technologies Corp | Wiring substrate and the method of manufacturing the same |
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| CN1630459A (en) * | 1996-12-19 | 2005-06-22 | 揖斐电株式会社 | Printed wiring board and method for manufacturing the same |
| US6228466B1 (en) * | 1997-04-11 | 2001-05-08 | Ibiden Co. Ltd. | Printed wiring board and method for manufacturing the same |
| CN1276090A (en) * | 1997-10-30 | 2000-12-06 | 株式会社日产制作所 | Semiconductor device and method for manufacturing the same |
| JP2004022713A (en) * | 2002-06-14 | 2004-01-22 | Dainippon Printing Co Ltd | Multilayer wiring board |
| TW200913804A (en) * | 2007-05-31 | 2009-03-16 | Kyocera Slc Technologies Corp | Wiring substrate and the method of manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111755223A (en) * | 2019-03-27 | 2020-10-09 | 株式会社村田制作所 | Multilayer metal film and inductor component |
| CN111755223B (en) * | 2019-03-27 | 2024-03-29 | 株式会社村田制作所 | Multilayer metal film and inductor component |
Also Published As
| Publication number | Publication date |
|---|---|
| US20140060904A1 (en) | 2014-03-06 |
| KR20140029241A (en) | 2014-03-10 |
| KR101523840B1 (en) | 2015-05-28 |
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