CN103682094A - Phase change memory structure and manufacturing method thereof - Google Patents

Abstract

The invention relates to a phase-change memory structure and a preparation method thereof. The prepared phase-change memory structure includes a substrate and several adjacent phase-change memory units located on the substrate; the phase-change memory unit comprises a phase-change material layer, located The first dielectric layer on both sides of the phase change material layer, the upper electrode layer on the upper surface of the phase change material layer and the first dielectric layer on both sides, and the second dielectric layer, the second dielectric layer covers the first dielectric layer A dielectric layer and the upper electrode layer are filled between adjacent phase-change memory cells; an air gap is formed between the first dielectric layers of two adjacent phase-change memory cells, and the air gap is located in the second dielectric layer Within the layer; the air gap can increase the thermal resistance between the phase change units, reduce the heat loss in device operation, thereby reducing the operating power consumption, and also reduce the thermal crosstalk between the storage cells; on the other hand, the air gap has an air gap Memory devices can reduce parasitic capacitance between wires to increase operating speed.

Description

A kind of phase change memory structure and preparation method thereof

technical field

The invention relates to a phase-change memory structure and a preparation method thereof, belonging to the field of phase-change memory or high-density phase-change memory devices. the

Background technique

Phase change memory is a new type of non-volatile data storage device, which uses the difference in electrical conductivity or optical properties of phase change alloy materials when they transform between crystalline and amorphous states to achieve data storage. Phase-change memory has the advantages of high-speed reading, high erasable times, non-volatility, small device size, low power consumption, and simple manufacturing process. It can replace a variety of traditional memories and is widely used in mobile communications, mobile data Terminals, mobile multimedia and other consumer electronics and other fields. the

In the process of commercialization of phase change memory, there are still many challenges in terms of reliability, power consumption, and speed. During the operation of the phase-change memory unit, Joule heat is used to convert the phase-change unit from a crystalline state to an amorphous state, which is accompanied by a complicated thermal process. Part of the Joule heat generated in the above process is used for the operation of the phase change unit, and other heat is dissipated through the surrounding dielectric and metal. In a T-shaped phase-change cell, about a quarter of the heat is lost to the surrounding dielectric. Improving thermal efficiency by reducing heat loss in the memory is one of the effective ways to reduce the power consumption of the phase change memory. The thermal conductivity of commonly used materials in common integrated circuits is shown in Table 1. The thermal conductivity of air is much smaller than that of conventional dielectrics such as silicon dioxide. Adopting the air gap structure can effectively increase the thermal resistance between the phase change units, thereby reducing the power consumption of the phase change memory. At the same time, increasing the thermal resistance between the phase change units through the air space structure also provides a solution to the thermal crosstalk between the storage units. the

Table 1: Thermal conductivity of commonly used materials in commonly used integrated circuits

At the same time, with the continuous improvement of the memory density, the time delay (τ) between the metal wirings is also increasing to the operating speed of the memory. The time delay of the metal connection can be expressed by the product of the resistance (R) of the metal wire and the parasitic capacitance (C) between the metal wires. At present, in order to reduce the resistance of metal wires, a large number of copper wires with low resistivity have been used. At the same time, using a dielectric with a lower dielectric constant (k) to reduce the parasitic capacitance between metal wires is another option to reduce time delay. . The low dielectric constant materials mainly used at present mainly include FSG, HSQ, SiLK ^TM , BD, CDO, NDC and so on. The above-mentioned low dielectric constant materials basically have properties such as low dielectric constant and low surface conductivity at the same time, but still face problems such as reliability, low mechanical strength or poor integration with metals. Since the ideal dielectric constant of air is close to 1, using air as an insulating substance between metals is also one of the solutions to effectively reduce the parasitic capacitance between metal wires.

In view of this, an efficient and feasible phase-change memory structure with air gaps and a fabrication method are of great significance. The invention can provide a complete solution and can reach mass production scale. the

Contents of the invention

The purpose of the present invention is to overcome the shortcomings of the prior art, and provide a phase change memory structure and manufacturing method, by forming a large number of air gaps between the phase change memory units, and then effectively increasing the thermal resistance between the phase change units , thereby reducing the power consumption of the phase change memory. At the same time, having a large amount of air space can also achieve the effect of reducing the time delay in the integrated circuit. the

The present invention is achieved through the following technical solutions:

A phase-change memory structure comprising a substrate and several adjacent phase-change memory cells located on the substrate;

The phase change memory unit includes a phase change material layer, a first dielectric layer located on both sides of the phase change material layer, an upper electrode layer located on the upper surface of the phase change material layer and the first dielectric layer on both sides, And a second dielectric layer, the second dielectric layer is covered outside the first dielectric layer and the upper electrode layer and filled between adjacent phase-change memory cells;

An air space is formed between the first dielectric layers of two adjacent phase change memory cells, and the air space is located within the second dielectric layer;

The longitudinal section of the phase change material layer is an inverted trapezoid;

The longitudinal section of the upper electrode layer is trapezoidal. the

The base is a semiconductor substrate, such as a semiconductor substrate of single crystal silicon or a semiconductor substrate of other materials. the

The substrate is also provided with fabricated semiconductor devices, such as MOS transistors, diodes, BJTs, electrodes, resistors, capacitors and the like. the

The material of the phase change material layer is selected from antimony-tellurium compounds and germanium-tellurium compounds. the

Preferably, the material of the phase change material layer is selected from germanium-antimony-tellurium, silicon-antimony-tellurium, titanium-antimony-tellurium and aluminum-antimony-tellurium compounds. the

The material of the first dielectric layer is selected from silicon oxide, silicon nitride or silicon oxynitride. the

The material of the second dielectric layer is silicon oxide, silicon nitride or silicon oxynitride. the

The material of the upper electrode layer is titanium, titanium nitride, titanium aluminum nitrogen or titanium silicon nitrogen. the

The present invention further provides a preparation method of the phase change memory structure, comprising the following steps:

(1) providing a substrate on which a first dielectric layer is formed;

(2) Etching the first dielectric layer anisotropically, and forming a number of inverted trapezoidal first grooves on the substrate for forming confinement phase-change memory cells;

(3) Depositing a phase change material layer in the first trench and covering the upper surface of the first dielectric layer;

(4) Planarize the phase change material layer by chemical mechanical polishing until the phase change material layer is flush with the upper surface of the first dielectric layer;

(5) Depositing an upper electrode layer on the upper surface of the phase change material layer and the first dielectric layer;

(6) Patterning the upper electrode layer on the first dielectric layer, then anisotropically etching the upper electrode layer, and using the upper electrode layer as a hard mask to over-etch the first dielectric layer to form the second two grooves;

(7) wet etching and isotropically etching the second trench within a short period of time to form a hollow structure in the first dielectric layer;

(8) Depositing a second dielectric layer on the overall structure formed above is used to cover each hollow structure to form an air gap;

(9) Planarize the surface of the second dielectric layer by chemical mechanical polishing. the

in,

The deposition process of the phase-change material layer can adopt techniques such as physical vapor deposition, chemical vapor deposition, and atomic layer deposition. the

The deposition process of the second dielectric layer may adopt methods such as chemical vapor deposition (CVD) or plasma enhanced chemical gas deposition. the

The polishing liquid used in the chemical mechanical polishing described in step (4) is an acidic phase change material polishing liquid. the

The polishing liquid used in the chemical mechanical polishing described in step (9) is an alkaline silica polishing liquid. the

The technical effects and advantages of the present invention are: an air gap is formed between the phase change units, on the one hand, the thermal resistance between the phase change units can be increased, the heat loss in device operation can be reduced to reduce the operating power consumption, and at the same time, the Thermal crosstalk between memory cells; on the other hand, memory devices with an air spacer structure can reduce parasitic capacitance between wires to increase operating speed. the

Description of drawings

Figure 1 Schematic diagram of substrate and first dielectric layer (before etching);

Fig. 2 schematic diagram of the first groove;

Figure 3 Schematic diagram of phase change material layer (before polishing);

Figure 4 Schematic diagram of phase change material layer (after polishing);

Figure 5 schematic diagram of the upper electrode layer (before etching);

The schematic diagram of the second groove of Fig. 6;

Figure 7 hollow structure schematic diagram;

Figure 8 Schematic diagram of the second dielectric layer and air space (before polishing);

Figure 9 Schematic diagram of the second dielectric layer and air gap (after polishing)

Reference signs:

210 - base;

220-the first dielectric layer;

221 - the first groove;

230-phase change material layer;

231-The phase change material layer filled in the first trench after chemical mechanical polishing;

240-upper electrode layer;

241-etching the patterned upper electrode layer;

242 - the second groove;

243-hollow structure;

250 - the second dielectric layer;

251 - air spacer;

252-the second dielectric layer after chemical mechanical polishing;

Detailed ways

The technical solutions of the present invention are illustrated below through specific examples. It should be understood that one or more method steps mentioned in the present invention do not exclude that there are other method steps before and after the combined steps or other method steps can be inserted between these explicitly mentioned steps; it should also be understood that these The examples are only for illustrating the present invention and are not intended to limit the scope of the present invention. Moreover, unless otherwise stated, the numbering of each method step is only a convenient tool for identifying each method step, and is not intended to limit the sequence of each method step or limit the scope of the present invention. The change or adjustment of its relative relationship is in In the case of no substantive change in the technical content, it shall also be regarded as the applicable scope of the present invention. the

A phase-change memory structure, as shown in Figure 9, includes a substrate 210 and several adjacent phase-change memory cells located on the substrate 210;

The phase-change memory unit includes a phase-change material layer, a first dielectric layer 220 located on both sides of the phase-change material layer 230 , and a layer on the surface of the phase-change material layer 230 and the first dielectric layer 220 on both sides thereof. The upper electrode layer 241, and the second dielectric layer 252, the second dielectric layer 252 is covered outside the first dielectric layer 220 and the upper electrode layer 241 and filled between adjacent phase change memory cells;

An air space 251 is formed between the first dielectric layers 220 of two adjacent phase change memory cells, and the air space 251 is located within the second dielectric layer 252;

The longitudinal section of the phase change material layer 230 is an inverted trapezoid;

The longitudinal section of the upper electrode layer 241 is trapezoidal. the

The phase change memory structure is prepared through the following method steps:

Step (1): As shown in FIG. 1 , a base 210 is provided, and a first dielectric layer 220 is formed on the base, and the first dielectric layer 220 is arranged on the surface of the base (semiconductor substrate) 210 . The surface of the substrate 210 may include fabricated semiconductor components, such as MOS transistors, diodes, BJTs, electrodes, resistors, capacitors and the like. Since these components are not the focus of the invention, they are not shown in the icon. The semiconductor substrate 210 may be a semiconductor substrate of single crystal silicon or a semiconductor substrate of other materials. The first dielectric layer 220 may be silicon oxide, silicon nitride or silicon oxynitride or a combination thereof. the

Step (2): As shown in FIG. 2 , anisotropically etch the first dielectric layer 220 to form an inverted trapezoidal first groove 221 for forming a restricted phase-change memory cell;

Step (3): As shown in FIG. 3 , deposit a phase-change material layer 230 in the first trench 221 and cover the upper surface of the first dielectric layer 220 , the material of the phase-change material layer 230 is germanium- Antimony-tellurium, silicon-antimony-tellurium, titanium-antimony-tellurium, aluminum-antimony-tellurium, or other antimony-tellurium compounds and germanium-tellurium compounds, etc. The phase change material can be formed on the substrate by techniques such as physical vapor deposition, chemical vapor deposition or atomic layer deposition. the

Step (4): As shown in FIG. 4 , planarize the phase change material layer 230 by using an acidic phase change material polishing process until the remaining phase change material layer 231 is flush with the upper surface of the first dielectric layer 220 , The size of the phase change material surface after treatment is d;

Step (5): As shown in FIG. 5 , the surface of the phase change material layer 2 after the planarization treatment is covered with an upper electrode layer 240 ; in this embodiment, the material of the etching stop layer 240 is titanium nitride. The advantage of titanium nitride as an etching barrier layer is that it has good adhesion with phase change materials, and its electrical and thermal conductivity meet the performance requirements. The material of the etching stop layer 240 can also be titanium, titanium aluminum nitrogen, titanium silicon nitrogen and other common materials in the field. the

Step (6), as shown in FIG. 6 , pattern the upper electrode layer 240 located on the first dielectric layer 220 , and then anisotropically etch the upper electrode layer 240 to expose a predetermined part, and then Using the remaining upper electrode layer as an etching barrier layer, and using the barrier layer as a hard mask, the first dielectric layer 220 is over-etched to form a second trench 242; the upper surface size of the etching barrier layer is h , the size of the lower surface is H, H>h and H>d; that is, the remaining upper electrode layer 240 is trapezoidal and completely covers the phase change material layer;

Step (7), as shown in FIG. 7 , wet etching isotropically etches the second trench 242 in a short period of time to form a hollow structure 243 in the first dielectric layer 220;

In step (8), as shown in FIG. 8 , a second dielectric layer 250 is deposited on the overall structure formed in step (7) to cover each hollow structure to form an air gap 251; the material of the second dielectric layer 250 can be It is silicon oxide, silicon nitride or silicon oxynitride; the deposition process of the second dielectric layer can adopt methods such as chemical vapor deposition (CVD) or plasma enhanced chemical gas deposition. the

In step (9), as shown in FIG. 9 , the surface of the second dielectric layer 250 is planarized with an alkaline silicon dioxide polishing solution, and the second dielectric layer 252 is obtained after treatment. the

The advantage of the present invention is that an air gap is formed between the phase change units, on the one hand, it can increase the thermal resistance between the phase change units, reduce the heat loss in device operation and thereby reduce the operating power consumption, and also reduce the thermal resistance between the storage units. Thermal crosstalk; on the other hand, memory devices with an air spacer structure can reduce parasitic capacitance between wires to increase operating speed. the

To sum up, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value. the

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention. the

Claims (13)

1. A phase change memory structure comprises a substrate and a plurality of adjacent phase change memory units positioned on the substrate;

the phase change memory unit comprises a phase change material layer, first dielectric layers positioned on two sides of the phase change material layer, upper electrode layers positioned on the phase change material layer and the upper surfaces of the first dielectric layers on the two sides of the phase change material layer, and second dielectric layers, wherein the second dielectric layers are coated outside the first dielectric layers and the upper electrode layers and are filled between the adjacent phase change memory units;

an air space is formed between the first dielectric layers of two adjacent phase change memory units and is positioned in the second dielectric layer;

the longitudinal section of the phase change material layer is in an inverted trapezoid shape;

the longitudinal section of the upper electrode layer is trapezoidal.

2. The phase change memory structure of claim 1, wherein the base is a semiconductor substrate.

3. The phase change memory structure of claim 1, wherein a completed semiconductor device is further disposed on the substrate.

4. The phase change memory structure of claim 3, wherein the semiconductor device is a MOS transistor, a diode, a BJT, an electrode, a resistor, or a capacitor.

5. The phase change memory structure of claim 1, wherein the phase change material layer material is selected from antimony-tellurium compounds and germanium-tellurium compounds.

6. The phase change memory structure of claim 5, wherein the phase change material layer material is selected from germanium-antimony-tellurium, silicon-antimony-tellurium, titanium-antimony-tellurium, and aluminum-antimony-tellurium compounds.

7. The phase change memory structure of claim 1, wherein the first dielectric layer material is selected from silicon oxide, silicon nitride, or silicon oxynitride.

8. The phase change memory structure of claim 1, wherein the second dielectric layer material is silicon oxide, silicon nitride, or silicon oxynitride.

9. The phase change memory structure of claim 1, wherein the top electrode layer material is titanium, titanium nitride, titanium aluminum nitrogen, or titanium silicon nitrogen.

10. A method of fabricating a phase change memory structure as claimed in any one of claims 1 to 9, comprising the steps of:

(1) providing a substrate, and forming a first dielectric layer on the substrate;

(2) anisotropically etching the first dielectric layer, and forming a plurality of inverted trapezoidal first grooves on the substrate for forming a limited phase change memory unit;

(3) depositing a phase change material layer in the first groove and covering the upper surface of the first dielectric layer;

(4) carrying out planarization treatment on the phase change material layer by adopting a chemical mechanical polishing method until the phase change material layer is flush with the upper surface of the first dielectric layer;

(5) depositing an upper electrode layer on the upper surfaces of the phase change material layer and the first dielectric layer;

(6) patterning the upper electrode layer on the first dielectric layer, then anisotropically etching the upper electrode layer, and over-etching the first dielectric layer by taking the upper electrode layer as a hard mask to form a second groove;

(7) wet etching is adopted, the second groove is isotropically etched in a short time, and a hollow structure is formed in the first dielectric layer;

(8) depositing a second dielectric layer on the formed integral structure for covering each hollow structure to form an air space;

(9) and planarizing the surface of the second dielectric layer by adopting a chemical mechanical polishing method.

11. The method according to claim 10, wherein the deposition process of the phase-change material layer is physical vapor deposition, chemical vapor deposition or atomic layer deposition.

12. The method of claim 10, wherein the second dielectric layer is deposited by a chemical vapor deposition process or a plasma enhanced chemical vapor deposition process.

13. The method according to claim 10, wherein the polishing solution used in the chemical mechanical polishing in the step (4) is an acidic phase-change material polishing solution; the polishing solution used for the chemical mechanical polishing in the step (9) is alkaline silicon dioxide polishing solution.

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