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CN103681612A - Seed layer structure and method - Google Patents

Seed layer structure and method Download PDF

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Publication number
CN103681612A
CN103681612A CN201310030491.XA CN201310030491A CN103681612A CN 103681612 A CN103681612 A CN 103681612A CN 201310030491 A CN201310030491 A CN 201310030491A CN 103681612 A CN103681612 A CN 103681612A
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Prior art keywords
seed layer
crystal seed
via openings
sidewall
thickness
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CN103681612B (en
Inventor
江祯斌
王泓智
李魁斌
周其雨
梁耀祥
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A seed layer structure and a method. A seed layer comprises a bottom seed layer portion formed on the bottom of a via opening, a sidewall seed layer portion formed on an upper portion of the sidewall of the via opening and a corner seed layer portion formed between the bottom seed layer portion and the sidewall seed layer portion. The sidewall seed layer portion is of a first thickness. The corner seed layer portion is of a second thickness and the second thickness is greater than the first thickness.

Description

Crystal seed layer structure and method
Technical field
The present invention relates to semiconductor device, in particular to crystal seed layer structure and method.
Background technology
Due to updating of the integration density of various electronic components (such as transistor, diode, resistor, capacitor etc.), semiconductor industry has experienced rapid growth.For most applications, this improvement of integration density aspect is that this allows more element to be integrated on given area due to constantly the reducing of minimal parts size.Recently along with the increase of the demand of the electronic device to even less, to the demand of encapsulation technology more small-sized and that have more creationary semiconductor element also in continuous increase.
A kind of in these creative encapsulation technologies manufactures interconnection structure, for example through hole and metal wire.Complementary metal oxide semiconductors (CMOS) (CMOS) device can comprise various semiconductor structures, such as transistor, capacitor and/or resistor etc.The one or more conductive layers that comprise metal wire are formed on the top of semiconductor structure and separate by adjacent dielectric layer.Thereby through hole is formed in dielectric layer and provides electrical connection between adjacent metal wire.In a word, metal wire and through-hole interconnection semiconductor structure provide conducting channel between the external contact part of semiconductor structure and cmos device.
Can be by using dual-damascene technics to form metal wire and adjacent through hole thereof.According to the manufacturing process of dual-damascene structure, comprise that the dual damascene opening of throughhole portions and trench portions is formed in dielectric layer.Can form dual damascene opening by photoetching technique known in the art.Conventionally, photoetching relates to deposition photoresist material, then according to the pattern of appointment irradiate (exposure) thereby and development remove a part of photoresist material.Material below remaining photoresist material protection avoids carrying out treatment step subsequently, such as etching.Etch process can be wet type or dry type, anisotropy or isotropic etch process, but anisotropy dry type etch process preferably.After etch process, can remove remaining photoresist material.Be to be further noted that can pass through one or more optional processing steps (for example first through hole or first groove mosaic technology) forms mosaic interlinkage opening.
After dual damascene opening forms, can be along sidewall and formation barrier layer, bottom and the crystal seed layer of dual damascene opening.Can form barrier layer by suitable manufacturing technology, such as various physical vapor deposition (PVD) technology etc.Can be by using suitable manufacturing technology to form crystal seed layer, such as PVD, electroless plating etc.
And, can use electroplating technology to dual damascene opening.As a result, dual damascene opening is filled by electric conducting material.Electric conducting material can comprise copper, but can utilize alternatively other suitable materials, such as the polysilicon of aluminium, alloy, tungsten, silver, doping, these combination and/or similar material.
Summary of the invention
In order to solve problems of the prior art, according to an aspect of the present invention, provide a kind of device, comprising: the dielectric layer forming above substrate; The via openings forming in described dielectric layer; And along the sidewall of described via openings and the crystal seed layer of bottom formation, wherein said crystal seed layer comprises: the bottom seed crystal layer segment forming on the bottom of described via openings; The sidewall crystal seed layer part forming along the top of the sidewall of described via openings, wherein said sidewall crystal seed layer partly has the first thickness; And the turning crystal seed layer part forming between described bottom seed crystal layer segment and described sidewall crystal seed layer part, wherein said turning crystal seed layer partly has the second thickness, and described the second thickness is greater than described the first thickness.
In described device, described via openings is the throughhole portions of dual-damascene structure.
In described device, the aspect ratio of described the second thickness and described via openings is proportional.In one embodiment, when the aspect ratio of described via openings is 1.6, described the second thickness equals approximately 80 dusts; And when the aspect ratio of described via openings is 2.0, described the second thickness equals approximately 180 dusts.
Described device is also included in the barrier layer that described crystal seed layer forms below.
Described device is also included in the electric conducting material of filling in described via openings.In one embodiment, described device also comprises: the metal covering forming above described electric conducting material; And the etching stopping layer forming above described metal covering.
According to a further aspect in the invention, provide a kind of method, having comprised: dielectric layer above substrate; In described dielectric layer, form dual damascene opening, wherein said dual damascene opening comprises: via openings and groove opening; In the surface of described dual damascene opening deposit seed; Sputtering technology is again used in the bottom of described crystal seed layer; And depositing operation is implemented in the bottom of described crystal seed layer.
Described method also comprises: before the step of the surface of described dual damascene opening deposit seed, along sidewall and the formation barrier layer, bottom of described dual damascene opening.
Described method also comprises: use physical vapor deposition process deposit seed.
In described method, described in the bottom of described crystal seed layer is used, the step of sputtering technology also comprises again: the bottom of using argon plasma bundle to clash into described crystal seed layer.
Described method also comprises: with copper, fill described dual damascene opening.In one embodiment, described method, also comprises: use flatening process and remove unnecessary copper.
In described method, described crystal seed layer comprises: along the sidewall of described via openings the sidewall crystal seed layer part that forms near the top of the sidewall of described via openings, wherein said sidewall crystal seed layer partly has the first thickness; And the turning crystal seed layer part forming between the bottom of described via openings and described sidewall crystal seed layer part, wherein said turning crystal seed layer partly has the second thickness, and described the second thickness is greater than described the first thickness.
According to another aspect of the invention, provide a kind of method, having comprised: above substrate, deposited the first dielectric layer; In described the first dielectric layer, form via openings; Sidewall and bottom deposit seed along described via openings; Sputtering technology is again implemented in the bottom of described crystal seed layer; Depositing operation is used in bottom to described crystal seed layer; And fill described via openings with electric conducting material.
Described method also comprises: use flatening process to remove the electric conducting material of the top face that is positioned at described the first dielectric layer.In one embodiment, described method also comprises: above electric conducting material, form metal covering; And above described metal covering deposition etch stop-layer.
In described method, described electric conducting material is copper.
Described method also comprises: before the sidewall along described via openings and bottom deposit the step of described crystal seed layer, along sidewall and the bottom deposited barrier layer of described via openings.
In described method, by use bottom that argon plasma bundle clashes into described crystal seed layer implement described in sputtering technology again.
Accompanying drawing explanation
In order to understand more fully the present invention and advantage thereof, the following description of carrying out in connection with accompanying drawing now as a reference, wherein:
Fig. 1 illustrates the sectional view according to each embodiment with the via openings of the crystal seed layer forming above the sidewall of via openings and bottom;
Fig. 2 illustrates and according to each embodiment, in substrate, has formed multiple circuit semiconductor device afterwards;
Fig. 3 illustrates the sectional view of the semiconductor device shown in the Fig. 2 forming above substrate according to each embodiment after the first dielectric layer;
Fig. 4 illustrates the sectional view that forms the semiconductor device shown in opening Fig. 3 afterwards according to each embodiment in the first dielectric layer;
Fig. 5 illustrates the sectional view of the semiconductor device shown in the Fig. 4 after forming barrier layer according to each embodiment above the sidewall of opening and bottom;
Fig. 6 illustrates the sectional view of the semiconductor device shown in the Fig. 5 forming above barrier layer according to each embodiment after crystal seed layer;
Fig. 7 illustrates and according to each embodiment, crystal seed layer is implemented the sectional view of the semiconductor device shown in sputtering technology Fig. 6 afterwards again;
Fig. 8 illustrates and according to each embodiment, the bottom of crystal seed layer is implemented the sectional view of the semiconductor device shown in physical vapor deposition (PVD) technique Fig. 7 afterwards;
Fig. 9 illustrates according to the sectional view of each embodiment semiconductor device shown in the Fig. 8 after filled conductive material in opening;
Figure 10 illustrates according to each embodiment and implements the sectional view that flatening process is removed the semiconductor device shown in unnecessary electric conducting material Fig. 9 afterwards;
Figure 11 illustrates the sectional view of semiconductor device shown in the Figure 10 forming above through hole according to each embodiment after metal covering and etching stopping layer; And
Figure 12 illustrates the sectional view according to each embodiment with second half conductor device of the crystal seed layer structure shown in Fig. 1.
Except as otherwise noted, the corresponding numbering in different accompanying drawings and symbol typically refer to corresponding parts.Drawing accompanying drawing needn't be drawn in proportion for being clearly shown that the related fields of each embodiment.
Embodiment
Below, discuss manufacture and the use of the embodiment of the present invention in detail.Yet, should be appreciated that, the invention provides many applicable inventive concepts that can realize in various specific environments.The specific embodiment of discussing only illustrates the concrete mode of manufacturing and using the embodiment of the present invention, and be not used in, limits the scope of the invention.
With reference to the embodiment in specific environment, the present invention is described, i.e. the formation method of crystal seed layer structure and semiconductor device.Yet embodiments of the invention also go for various semiconductor device.Hereinafter, describe with reference to the accompanying drawings each embodiment in detail.
Fig. 1 illustrates the sectional view according to each embodiment with the via openings of the crystal seed layer forming along sidewall and the bottom of via openings.The crystal seed layer can as shown in Figure 1, with sidewall, the bottom of via openings and the conformal formation of end face of dielectric layer 150 along via openings.Crystal seed layer can be by forming such as electric conducting materials such as copper.Can form crystal seed layer by using such as suitable manufacturing technologies such as physical vapor deposition (PVD).
According to different positions, crystal seed layer can be divided into four parts.First 151 is formed directly into the top of dielectric layer 150.Second portion 152 forms the top of also close sidewall along the sidewall of via openings.Third part 153 is formed on the sidewall of via openings and near the bottom of sidewall.The 4th part 154 is formed on the bottom of via openings.
As shown in Figure 1, the degree of depth of via openings is defined as to L.The open-topped width of through hole is defined as to d.The aspect ratio of through hole is defined as to AR, and it equals L/d.According to each embodiment, when forming crystal seed layer in high aspect ratio through hole, the thickness of the third part 153 of the thickness of crystal seed layer, especially crystal seed layer may have a direct impact the reliability of the through hole shown in Fig. 1.
In high aspect ratio through hole, the through hole that is greater than 1.6 such as AR value, traditional crystal seed layer (not shown) may not for example, provide good adhesiveness for the copper that forms subsequently (filling through hole material, such as copper).Specifically, in the traditional crystal seed layer being formed by PVD technique, third part 153 (bottom corners that is called again crystal seed layer) is thinner than second portion 152.This thinner bottom corners of crystal seed layer may cause barrier layer (not shown) in through hole and the copper product (not shown) that forms subsequently between adhesiveness a little less than.This weak adhesiveness through hole (open via) that may cause opening a way in reliability testing.
By contrast, as shown in Figure 1, the bottom corners of crystal seed layer part (for example third part 153) is for example, than the top of crystal seed layer (second portion 152) thicker.Specifically, by crystal seed layer, the thickness at height h place is defined as T2.According to each embodiment, h is approximately 10% of via depth.The thickness of second portion 152 is defined as to T1.
In order to have good adhesiveness between the electric conducting material that makes the barrier layer in through hole and form subsequently, T2 is greater than T1.According to each embodiment, when AR is 1.6 left and right, T2 is greater than approximately 80 dusts.In addition, when AR is 2.0 left and right, T2 is greater than approximately 180 dusts.The detailed formation technique of the third part 153 of crystal seed layer shown in Fig. 1 is below described with reference to Fig. 2 to Figure 11.
In a word, in traditional crystal seed layer, in hot test process, thin crystal seed layer especially thin bottom part turning may not provide strongly adherent between barrier layer and the copper forming subsequently.Due to thermal stress, may there are some integrity problems, such as copper pull back (copper pullback).As a result, due to the copper forming subsequently and the disconnection between barrier layer, may there is open fault.
A favorable characteristics with the thicker bottom corners shown in Fig. 1 is that this thicker bottom corners (for example third part 153) contributes to improve the copper of formation subsequently and the adhesiveness between barrier layer.Adhering improvement prevents that the copper forming is subsequently pulled and contributes to realization between the copper forming subsequently and barrier layer to connect reliably.According to each embodiment, after humidity heat stress test, the open circuit through hole failure rate being caused by the copper problem of pulling back can be improved to approximately 0% (crystal seed layer shown in Fig. 1) from approximately 70% (traditional crystal seed layer).
Fig. 2 to Figure 11 illustrates according to the intermediate steps of the semiconductor device shown in each embodiment shop drawings 1.Fig. 2 illustrates and according to each embodiment, in substrate, has formed multiple circuit semiconductor device afterwards.Substrate 102 can be formed by silicon, but this substrate also can be formed by other III families, IV family and/or V group element, such as silicon, germanium, gallium, arsenic, and these combination.
Substrate 102 can be also the form of silicon-on-insulator (SOI).SOI substrate can be included in the semi-conducting material that the top of the insulator layer that forms in silicon substrate (such as oxygen buried layer etc.) forms (for example silicon, germanium and/or similarly material) layer.In addition, operable other substrates comprise MULTILAYER SUBSTRATE, gradient substrate, hybrid orientation substrate and/or similar substrate.
Substrate 102 can also comprise multiple circuit (not shown).The circuit being formed on substrate 102 can be the circuit that is applicable to any type of application-specific.According to some embodiment, circuit can comprise various N-shaped metal-oxide semiconductor (MOS)s (NMOS) and/or p-type metal-oxide semiconductor (MOS) (PMOS) device, such as transistor, capacitor, resistor, diode, photodiode, fuse and/or similar device.These circuit can interconnect to carry out one or more functions.This function can comprise memory construction, processing structure, transducer, amplifier, power division, input/output circuitry and/or similar function.
As shown in Figure 2, metal-oxide semiconductor (MOS) (MOS) transistor 105 and relevant contact plug 118 thereof are for representing the circuit of semiconductor device.MOS transistor 105 is formed in substrate 102.MOS transistor 105 comprises two drain/source region 106.As shown in Figure 2, drain/source region 106 is formed on the opposition side of grid pile overlapping piece.Grid pile overlapping piece is included in the gate dielectric 112 of substrate 102 tops formation, gate electrode and the gate spacer part 116 forming above gate dielectric 112.As shown in Figure 2, on the opposition side of MOS transistor 105, can form two isolated areas 104.
Isolated area 104 can be shallow trench isolation from (STI) district, and can to form groove, then with dielectric material filling groove known in the art, form by etch substrate 102.For example, can use such as oxide material, high-density plasma (HDP) oxide and/or similar dielectric material and fill isolated area 104.Can use the flatening process such as CMP technique to end face, result can be removed unnecessary dielectric material.
Gate dielectric 112 can be dielectric material, such as silica, silicon oxynitride, silicon nitride, oxide, nitrogen-containing oxide, these combination and/or similar dielectric material.The relative dielectric constant of gate dielectric 112 can be greater than approximately 4.Other examples of this material comprise aluminium oxide, lanthana, hafnium oxide, zirconia, nitrogen hafnium oxide, these combination and/or similar material.At gate dielectric 112, comprise in some embodiment of oxide skin(coating), can use tetraethoxysilane (TEOS) and oxygen to form gate dielectric 112 as precursor by pecvd process.According to each embodiment, the thickness of gate dielectric 112 can be approximately 8
Figure BDA00002778621300071
to approximately 200 scope in.
Gate electrode 114 can comprise electric conducting material, for example, for example, for example, such as metal (tantalum, titanium, molybdenum, tungsten, platinum, aluminium, hafnium, ruthenium), metal silicide (titanium silicide, cobalt silicide, nickle silicide, tantalum silicide), metal nitride (titanium nitride, tantalum nitride), the polysilicon adulterating, other electric conducting materials, these combination and/or similar electric conducting material.At gate electrode 114, be in some embodiment of polysilicon, can pass through low-pressure chemical vapor deposition (LPCVD) dopant deposition or unadulterated polysilicon to thickness between approximately 400 to approximately 2400
Figure BDA00002778621300074
scope in form gate electrode 114.
Can form distance piece 116 by deposit one or more wall (not shown) above gate electrode 114 and substrate 102.Wall 116 can comprise suitable dielectric material, such as SiN, nitrogen oxide, SiC, SiON, oxide and/or similar dielectric material.Can form wall 116 by conventional technology such as CVD, PECVD and/or sputter.
Can in the substrate 102 on the opposition side of gate dielectric 112, form drain/source region 106.At substrate 102, be in some embodiment of N-shaped substrate, can form drain/source region 106 by injecting suitable p-type alloy (such as boron, gallium, indium and/or similar alloy).Alternatively, at substrate 102, be in some embodiment of p-type substrate, can form drain/source region 106 by injecting suitable N-shaped alloy (such as phosphorus, arsenic and/or similar alloy).
Interlayer dielectric layer 115 is formed on the top of substrate 102.Interlayer dielectric layer 115 can be formed by for example low k dielectric (such as silica).Can form interlayer dielectric layer 115 by any suitable method known in the art, such as spin coating, chemical vapor deposition (CVD) and plasma enhanced chemical vapor deposition (PECVD).Although be to be further noted that and those skilled in the art will recognize that Fig. 2 illustrates single interlayer dielectric layer, interlayer dielectric layer 115 can comprise a plurality of dielectric layers.
As shown in Figure 2, interlayer dielectric layer 115 is formed on the top of substrate 102.In interlayer dielectric layer 115, can be formed with contact plug 118.Formation is through the contact plug 118 of interlayer dielectric layer 115, thereby provides electrical connection in MOS transistor 105 with between the interconnection structure (not shown) forming above interlayer dielectric layer 115.
Can be by depositing on interlayer dielectric layer 115 by photoetching technique and patterning photoresist material forms contact plug 118.According to the position of contact plug 118 and shape, expose a part of photoresist.Can use the etch process such as anisotropy dry type etch process to form opening in interlayer dielectric layer 115.
Can depositing electrically conductive lining before filling contact consent.This conductive liner is preferably conformal, and can comprise the individual layer of Ta, TaN, WN, WSi, TiN, Ru and these combination in any.This conductive liner can be used as barrier layer conventionally, for preventing, such as the electric conducting material of copper, diffuses into substrate 102 below.Can use suitable depositing operation depositing electrically conductive lining, such as CVD, PVD, ald (ALD) and/or similar technology.
Then filled conductive material in opening.Can use CVD, PVD or ALD deposits conductive material.Above conductive liner, deposits conductive material is filled contact plug opening.By using such as the flatening process of chemico-mechanical polishing (CMP) technology, from the end face of interlayer dielectric layer 115, remove the redundance of electric conducting material.Electric conducting material can be copper, tungsten, aluminium, silver, titanium, titanium nitride, tantalum and these combination and/or similar material.
Above interlayer dielectric layer 115, form metal intermetallic dielectric layer 138.In metal intermetallic dielectric layer 138, can be embedded with two wires 134 and 136.Metal intermetallic dielectric layer 138 can be by forming such as fluorosilicate glass (FSG) and/or similar low k dielectric.Can be by forming metal intermetallic dielectric layer 138 such as the suitable deposition technique such as PECVD technology and/or high-density plasma chemical gas deposition (HDPCVD).
Fig. 3 illustrates the sectional view of the semiconductor device shown in the Fig. 2 forming above substrate according to each embodiment after the first dielectric layer.The first dielectric layer 145 can be by forming such as fluorosilicate glass (FSG) and/or similar low k dielectric.The first dielectric layer 145 can play the effect of metal intermetallic dielectric layer.Can form by suitable deposition technique the first dielectric layer 145, such as PECVD technology, high-density plasma chemical gas deposition (HDPCVD) and/or similar technology.
Fig. 4 illustrates the sectional view that forms the semiconductor device shown in opening Fig. 3 afterwards according to each embodiment in the first dielectric layer.According to the position of the through hole forming, in the first dielectric layer 145, form opening 402 on metal wire 134.Can form opening 402 by any suitable semiconductor patterning technology, such as etch process, laser ablation process and/or similar technique.
Fig. 5 illustrates the sectional view of the semiconductor device shown in the Fig. 4 after forming barrier layer according to each embodiment above the sidewall of opening and bottom.Barrier layer 502 is along the conformal formation of sidewall and bottom of opening 402.Barrier layer can be formed by suitable metal material, such as titanium, titanium nitride, tantalum, tantalum nitride and these combination and/or similar metal material.Can use suitable manufacturing technology to form barrier layer 502, such as ALD, PECVD, plasma, strengthen physical vapor deposition (PEPVD) and/or similar technology.According to each embodiment, the thickness on barrier layer 502 can be at approximately 20 dusts to the scope of approximately 200 dusts.
Fig. 6 illustrates the sectional view of the semiconductor device shown in the Fig. 5 forming above barrier layer according to each embodiment after crystal seed layer.Crystal seed layer 602 can by copper, nickel, gold, these combination in any and/or similarly material form.Crystal seed layer can be formed by suitable deposition technique, such as PVD, CVD and/or similar technology.The thickness of crystal seed layer can be at approximately 50 dusts to the scope of approximately 1000 dusts.
In addition, crystal seed layer 602 can form alloy with the material that improves the adhesion property of crystal seed layer 602, makes crystal seed layer 602 can play the effect of adhesion layer.For example, crystal seed layer 602 can form alloy with material such as magnesium or aluminium, and this material will migrate to interface between crystal seed layer and barrier layer and will strengthen this adhesiveness between two-layer.Can in the process that forms crystal seed layer 602, introduce alloying material (alloying material).This alloying material can comprise no more than approximately 10% crystal seed layer 602.Should be noted that, due to the thicker bottom corners shown in Fig. 1, alloy technique can be optional step, because this thicker bottom corners can help improve the adhesiveness between barrier layer and crystal seed layer.
Fig. 7 illustrates and according to each embodiment, crystal seed layer is implemented the sectional view of the semiconductor device shown in sputtering technology Fig. 6 afterwards again.Can be by using argon plasma bundle to implement sputtering technology again.Specifically, make argon plasma bundle target in the bottom of crystal seed layer 602.By controlling the bias voltage of the plasma of sputtering technology, argon ion clashes into the bottom of crystal seed layer 602 again.Owing to colliding with argon ion, the copper ion of the bottom of crystal seed layer 602 can obtain significant momentum.As a result, the copper ion of capacitation can overcome the adhesion of the plane of crystal of crystal seed layer 602.And copper ion spatters to the sidewall of crystal seed layer 602, the bottom corners 702 of sidewall especially.As a result, compare with the top 704 of sidewall, the thickness of bottom corners 702 increases.
Fig. 8 illustrates and according to each embodiment, the bottom of crystal seed layer is implemented the sectional view of the semiconductor device shown in PVD technique Fig. 7 afterwards.After the sputtering technology again shown in Fig. 7, compare the thickness attenuation of the bottom of crystal seed layer with the bottom of the crystal seed layer forming by PVD technique.Thereby can implement the identical level of thickness that PVD techniques can be increased to the thickness of the bottom 802 of crystal seed layer to produce with conventional PVD technique to the bottom 802 of crystal seed layer.
Fig. 9 illustrates according to the sectional view of each embodiment semiconductor device shown in the Fig. 8 after filled conductive material in opening.As shown in Figure 9, can be at opening (example opening 402) as shown in Figure 8 thus in the through hole that is connected with metal wire 134 of filled conductive material 902 formation.Electric conducting material 902 can be copper, but can be also any suitable electric conducting material, such as copper alloy, aluminium, tungsten, silver, these any combination and/or similar electric conducting material.Can form electric conducting material 902 by suitable technology, such as electroless plating, CVD, plating and/or similar technology.
Figure 10 illustrates according to each embodiment and implements the sectional view that flatening process is removed the semiconductor device shown in unnecessary electric conducting material Fig. 9 afterwards.Can be by using the appropriate technology enforcement flatening process such as the combination of grinding, polishing and/or chemical etching, etching and grinding technique.According to each embodiment, can be by using CMP process implementing flatening process.In CMP technique, etching material and the combination of grinding-material and the end face of semiconductor device are contacted, then use grinding pad (not shown) to grind and remove unnecessary copper and part barrier layer and crystal seed layer until expose the first dielectric layer 145.
Figure 11 illustrates the sectional view of semiconductor device shown in the Figure 10 forming above through hole according to each embodiment after metal covering (metal cap) and etching stopping layer.The electric conducting material of through hole (such as copper) demonstrates with the adhesiveness of the dielectric protection layer of above covering poor.For improve through hole copper and on poor adhesiveness between the dielectric layer that covers, the copper of through hole and on form metal cladding 1102 between the dielectric layer that covers.Metal cladding 1102 can be cobalt/tungsten/phosphorus (CoWP) metal covering.Can form CoWP metal cladding 1102 by using such as suitable semiconductor deposition technology such as electroless deposition technique.
Etching stopping layer 1104 is formed by the dielectric material with the etching selectivity different from adjacent layer.In certain embodiments, etching stopping layer 1104 can be formed by SiN, SiCN, SiCO, CN, these combination and/or similar material.Can pass through such as suitable techniques of deposition etching stopping layers 1104 such as CVD.
Figure 12 illustrates the sectional view according to each embodiment with second half conductor device of the crystal seed layer structure shown in Fig. 1.Except through hole be by dual-damascene technics, form, the structure of semiconductor device 1200 and the structural similarity of the semiconductor device shown in Figure 11 1100.In the dual-damascene structure 1202 shown in Figure 12, throughhole portions can have identical crystal seed layer with the through hole that single mosaic technology forms that passes through shown in Figure 11.
Although described embodiments of the invention and advantage thereof in detail, should be appreciated that, can in the situation that do not deviate from the spirit and scope of the present invention that claims limit, carry out various changes, replacement and change.
And the application's scope is not limited in the specific embodiment of technique, machine, manufacture, material component, device, method and the step described in this specification.As those of ordinary skills, according to the present invention, should be readily appreciated that, according to the present invention, can utilize existing or Future Development for carrying out the function substantially the same with corresponding embodiment described herein or obtaining technique, machine, manufacture, material component, device, method or the step of substantially the same result.Therefore, claims expection comprises such technique, machine, manufacture, material component, device, method or step within the scope of it.

Claims (10)

1. a device, comprising:
The dielectric layer forming above substrate;
The via openings forming in described dielectric layer; And
Along the sidewall of described via openings and the crystal seed layer of bottom formation, wherein said crystal seed layer comprises:
The bottom seed crystal layer segment forming on the bottom of described via openings;
The sidewall crystal seed layer part forming along the top of the sidewall of described via openings, wherein said sidewall crystal seed layer partly has the first thickness; With
The turning crystal seed layer part forming between described bottom seed crystal layer segment and described sidewall crystal seed layer part, wherein said turning crystal seed layer partly has the second thickness, and described the second thickness is greater than described the first thickness.
2. device according to claim 1, wherein, described via openings is the throughhole portions of dual-damascene structure.
3. device according to claim 1, the aspect ratio of wherein said the second thickness and described via openings is proportional.
4. device according to claim 3, wherein:
When the aspect ratio of described via openings is 1.6, described the second thickness equals approximately 80 dusts; And
When the aspect ratio of described via openings is 2.0, described the second thickness equals approximately 180 dusts.
5. device according to claim 1, also comprises:
The barrier layer forming below described crystal seed layer.
6. device according to claim 1, also comprises:
The electric conducting material of filling in described via openings.
7. device according to claim 6, also comprises:
The metal covering forming above described electric conducting material; And
The etching stopping layer forming above described metal covering.
8. a method, comprising:
Dielectric layer above substrate;
In described dielectric layer, form dual damascene opening, wherein said dual damascene opening comprises:
Via openings; With
Groove opening;
In the surface of described dual damascene opening deposit seed;
Sputtering technology is again used in the bottom of described crystal seed layer; And
Depositing operation is implemented in the bottom of described crystal seed layer.
9. method according to claim 8, wherein said crystal seed layer comprises:
Along the sidewall of described via openings the sidewall crystal seed layer part that forms near the top of the sidewall of described via openings, wherein said sidewall crystal seed layer partly has the first thickness; And
The turning crystal seed layer part forming between the bottom of described via openings and described sidewall crystal seed layer part, wherein said turning crystal seed layer partly has the second thickness, and described the second thickness is greater than described the first thickness.
10. a method, comprising:
Above substrate, deposit the first dielectric layer;
In described the first dielectric layer, form via openings;
Sidewall and bottom deposit seed along described via openings;
Sputtering technology is again implemented in the bottom of described crystal seed layer;
Depositing operation is used in bottom to described crystal seed layer; And
With electric conducting material, fill described via openings.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108140578A (en) * 2015-10-23 2018-06-08 应用材料公司 The gap filling from bottom to top handled by envenomation
CN115863259A (en) * 2023-02-07 2023-03-28 合肥晶合集成电路股份有限公司 Metal interconnection structure and manufacturing method thereof

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8736056B2 (en) 2012-07-31 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Device for reducing contact resistance of a metal
US10825724B2 (en) 2014-04-25 2020-11-03 Taiwan Semiconductor Manufacturing Company Metal contact structure and method of forming the same in a semiconductor device
US10157785B2 (en) * 2017-05-01 2018-12-18 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
CN113594131A (en) * 2021-07-27 2021-11-02 日月光半导体制造股份有限公司 Semiconductor package device and method of manufacturing the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7648899B1 (en) * 2008-02-28 2010-01-19 Novellus Systems, Inc. Interfacial layers for electromigration resistance improvement in damascene interconnects
US20100068881A1 (en) * 2008-09-18 2010-03-18 Kang Joo-Ho Method of forming metallization in a semiconductor device using selective plasma treatment
CN102148192A (en) * 2010-12-30 2011-08-10 上海交通大学 Method for growing blocking layer and seed layer on surface of silicon through hole

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6117781A (en) * 1999-04-22 2000-09-12 Advanced Micro Devices, Inc. Optimized trench/via profile for damascene processing
US6410418B1 (en) * 1999-08-18 2002-06-25 Advanced Micro Devices, Inc. Recess metallization via selective insulator formation on nucleation/seed layer
DE10227615A1 (en) * 2002-06-20 2004-01-15 Infineon Technologies Ag Layer arrangement and method for producing a layer arrangement
US8324738B2 (en) 2009-09-01 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned protection layer for copper post structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7648899B1 (en) * 2008-02-28 2010-01-19 Novellus Systems, Inc. Interfacial layers for electromigration resistance improvement in damascene interconnects
US20100068881A1 (en) * 2008-09-18 2010-03-18 Kang Joo-Ho Method of forming metallization in a semiconductor device using selective plasma treatment
CN102148192A (en) * 2010-12-30 2011-08-10 上海交通大学 Method for growing blocking layer and seed layer on surface of silicon through hole

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108140578A (en) * 2015-10-23 2018-06-08 应用材料公司 The gap filling from bottom to top handled by envenomation
CN108140578B (en) * 2015-10-23 2022-07-08 应用材料公司 Bottom-up gapfill by surface poisoning
CN115863259A (en) * 2023-02-07 2023-03-28 合肥晶合集成电路股份有限公司 Metal interconnection structure and manufacturing method thereof

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