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CN103680317B - 一种阵列基板及其制造方法和显示装置 - Google Patents

一种阵列基板及其制造方法和显示装置 Download PDF

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Publication number
CN103680317B
CN103680317B CN201310712539.5A CN201310712539A CN103680317B CN 103680317 B CN103680317 B CN 103680317B CN 201310712539 A CN201310712539 A CN 201310712539A CN 103680317 B CN103680317 B CN 103680317B
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China
Prior art keywords
layer
array base
base palte
tack coat
metal layer
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CN201310712539.5A
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CN103680317A (zh
Inventor
罗强强
權基瑛
周保全
曲坤
李震芳
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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Priority to CN201310712539.5A priority Critical patent/CN103680317B/zh
Publication of CN103680317A publication Critical patent/CN103680317A/zh
Priority to US14/408,289 priority patent/US20160282659A1/en
Priority to PCT/CN2014/000562 priority patent/WO2015089892A1/zh
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Publication of CN103680317B publication Critical patent/CN103680317B/zh
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/1341—Filling or closing of cells
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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Abstract

本发明公开了一种阵列基板及其制造方法和显示装置，其中阵列基板的结构是在基板周边区域设置有多根信号线，每一根信号线用于与集成电路芯片连接的部位设置有至少两个不同厚度的粘结层，各粘结层之间通过导电金属层电连接。本发明通过将改变现有技术中一整片的粘结层设计成至少两个粘结层结构，即在一个绑定位置处包括两个不同厚度的粘结层，并通过导电金属层将二者连接，可以避免膜厚差异和金属层的偏移造成的绑定异常，减少由于绑定异常造成的布线不良的发生，提高产品质量。同时本发明还提供了一种基于上述阵列基板的显示装置，其中阵列基板上的粘结层通过各向异性胶与显示装置中的驱动集成电路连接。

Description

一种阵列基板及其制造方法和显示装置
技术领域
本发明涉及显示技术领域，特别涉及一种阵列基板及其制造方法和显示装置。
背景技术
在基板设计以及加工流程中，集成电路（Integrated Circuit，简称IC）在对电极引线和印刷电路板（Printed Circuit Board，简称PCB）时起到重要作用，尤其是对基板上的绑定垫片（Bonding Pad）和PCB板路连接时。
对于大尺寸的显示产品一般还包括栅电极层垫片（即Gate Pad）和源漏层垫片（即SD Pad），而小尺寸（一般是指7寸以下）的显示产品，通常只有一个垫片（即Pad），栅电极层采用GOA（Gate Driveron Array，阵列基板行驱动）技术不进行IC绑定，或者是采用COG（Chip On Glass的简称）技术，即直接将IC或者是具有IC的芯片制作在玻璃基板上，并且IC和玻璃基板之间通过ACF胶（AnisotropicConductive Film，即各向异性导电胶）导通。目前小尺寸产品的垫片设计一般是采用两层布线，可以节省空间。
但是采用双层布线的设计存在不足之处，即不同层的膜厚差异会影响绑定效果，另外由于工艺波动造成不同层的布线发生偏移也会影响绑定效果，导致绑定设备对位报警严重时发生绑定异常。
发明内容
（一）要解决的技术问题
本发明要解决的技术问题是如何避免由于垫片造成绑定异常现象的发生。
（二）技术方案
为解决上述技术问题，本发明提供了一种阵列基板，所述基板周边区域设置有多根信号线，每一根信号线用于与集成电路芯片连接的部位设置有至少两个不同厚度的粘结层，各所述粘结层之间通过导电金属层电连接。
进一步地，各所述粘结层为金属材料制成。
进一步地，所述粘结层的数量为两个，其中一个粘结层与阵列基板上的源漏金属层同层设置且材料相同，另一粘结层与阵列基板上的栅极电极层同层设置且材料相同。
进一步地，所述导电金属层与阵列基板中的透明导电层同层形成。
进一步地，通过在所述导电金属层上开孔将信号线输出端引出到阵列基板的表面，并与集成电路芯片连接。
进一步地，所述多根信号线分为至少两层，每层信号线之间用于与集成电路芯片连接的部位设置的粘结层互不重叠。
为解决上述技术问题，本发明还提供了一种显示装置的制造方法，包括：通过第一次构图工艺在所述阵列基板周边区域形成包括多根信号线的图形；通过第二次构图工艺在每一根信号线用于与集成电路芯片连接的部位形成至少两个不同厚度的粘结层的图形；通过第三次构图工艺形成导电金属层电的图形，且各所述粘结层之间通过所述导电金属层电连接。
进一步地，各所述粘结层采用金属材料形成。
进一步地，所述第二次构图工艺形成两个不同厚度的粘结层的图形的步骤中，一个粘结层与阵列基板上的源漏金属层同层设置且材料相同，另一粘结层与阵列基板上的栅极电极层同层设置且材料相同。
进一步地，所述第三次构图工艺中导电金属层与阵列基板中的透明导电层同层形成。
进一步地，所述第三次构图工艺后还包括：在所述导电金属层上开孔，以将信号线输出端引出到阵列基板的表面与集成电路芯片连接。
进一步地，所述第一次构图工艺中形成的多根信号线图形分为至少两层，每层信号线之间用于与集成电路芯片连接的部位设置的粘结层互不重叠。
为解决上述技术问题，本发明还提供了一种显示装置，包括驱动集成电路芯片，还包括以上所述的阵列基板，所述阵列基板上的粘结层通过各向异性胶与所述驱动集成电路连接。
（三）有益效果
本发明实施例提供的一种阵列基板和显示装置，其中阵列基板的结构是在基板周边区域设置有多根信号线，每一根信号线用于与集成电路芯片连接的部位设置有至少两个不同厚度的粘结层，各粘结层之间通过导电金属层电连接。本发明通过将改变现有技术中一整片的粘结层设计成至少两个粘结层结构，即在一个绑定位置处包括两个不同厚度的粘结层，并通过导电金属层将二者连接，可以避免膜厚差异和金属层的偏移造成的绑定异常，减少由于绑定异常造成的布线不良的发生，提高产品质量。同时本发明还提供了一种基于上述阵列基板的显示装置，其中阵列基板上的粘结层通过各向异性胶与显示装置中的驱动集成电路连接。
附图说明
图1是现有技术提供的显示装置的截面示意图；
图2是现有技术IC绑定后垫片位置处的剖面图；
图3是对图2中结构沿A-A’方向的剖视图；
图4是对图2中结构沿B-B’方向的剖视图；
图5是本发明实施例一中提供的一种邦定垫片进行IC绑定后的剖面图；
图6是本发明实施例一中对图5中结构沿C-C’方向的剖视图；
图7是本发明实施例一中对图5中结构沿D-D’方向的剖视图；
图8是本实施例二中提供的一种阵列基板的制造方法的步骤流程图。
具体实施方式
下面结合附图和实施例，对本发明的具体实施方式作进一步详细描述。以下实施例用于说明本发明，但不用来限制本发明的范围。
对于现有的绑定垫片、集成电路IC与阵列基板的位置关系示意图如图1所示，具体的图1为集成电路中绑定垫片（即IC Bonding Pad）的截面示意图，在阵列衬底基板4的周边区域设置有绑定垫片3，IC通过ACF胶与绑定垫片3电连接。小尺寸的显示产品在进行外围布线时，为了节省空间一般使用双层布线，参照图2所示，信号线20分为两层，一层为A-A’，另一层为B-B’，该两层信号线在与驱动IC1连接的位置均设置有粘结层6和8，并通过ACF胶分别实现驱动IC1与粘结层6和8的电连接。
图1的右侧还示出了液晶显示面板中阵列基板显示区域的截面结构图，即编号5指向的框，由于该部分结构就是现有技术中阵列基板和彩膜基板以及他们之间填充液晶的结构，此处不再赘述。
参照图2所示，设置在基板周边的信号线通过绑定垫片和各项异性导电胶（ACF胶）与驱动IC连接，ACF胶是通过在胶里面掺杂可导电的金球实现的各向导电的功能，且只有当金球被压变形到一定程度后才能导电（金球外面是一层绝缘层，被压变形后绝缘层会被破坏）。对图2中结构沿A-A’剖开得到的示意图如图3所示，沿B-B’剖开得到的示意图如图4所示，其中图3和图4中的1为驱动IC，基板4、与源漏金属层同层形成的粘结层8、绝缘层9、导电球，1导电金属层11，栅极电极层同层形成的粘结层6。在图3所示的结构中衬底基板4的上方形成一层绝缘层9之后与显示区域的源漏金属层同层形成的粘结层8，之后继续在与源漏金属层同层形成的粘结层8上方形成绝缘层，并刻蚀掉粘结层8上方的部分绝缘层，并在该区域的绝缘层9上方形成一层导电金属层11；而在图4中衬底基板4上方经过一次构图工艺形成与栅极电极层同层形成的粘结层6，继续在与栅极电极层同层形成的粘结层6上方形成绝缘层9，同样刻蚀掉栅极电极层上方的绝缘层9，只保留部分绝缘层9，在保留的绝缘层9上方沉积一层金属作为导电金属层11，最后经过刻蚀只保留栅极电极层上方和绝缘层9上方部分区域以及绝缘层9边缘的导电金属层11，最后导电球10位于驱动IC1和导电金属层11之间，导电金属层11连接信号线（图3和图4中未示出信号线）。由于导电球10是一种外层具有绝缘层、内部含有导电材质的金球，只有在它被压变形的情况下外层的绝缘层会被破坏，进而实现导电功能，图3和图4不同之处在于图3中形成与源漏金属层同层形成粘结层8之前还有一层绝缘层，所以驱动IC与粘结层8之间的距离更加接近，导电球被压缩，导电良好。
因此通过对比图3和图4可知，图3中所示的粘结层8和显示区域中源漏金属层（SD层）同层形成，此处的导电球被压变形，能够实现驱动IC与导电球下方的导电金属层之间良好的导通，即绑定良好，但是对于图4中所述的粘结层6和阵列基板上栅极电极层（Gate层）同层形成，此处的导电球没有被压缩变形，无法实现驱动IC与导电球下方的导电金属层之间良好的导通，即出现绑定不良。图3和图4中所示的两种粘结层分别形成两个垫片，两个垫片连接不通的信号线，粘结层和驱动IC之间的电连接，更进一步地，为了满足电阻率和降低成本等目的，一般Gate层和SD层的金属材质和厚度不一样，这样会导致与栅极电极层同层形成的绑定垫片和与源漏金属层同层形成的绑定垫片之间存在厚度差异进而影响绑定的成功率；另外，由于工艺波动，例如在曝光过程中会造成Gate层和SD层发生偏移，因此，造成该绑定区域的绑定垫片错位，会造成绑定异常。
实施例一
基于上述，本发明实施例一中提供了一种阵列基板，基板周边区域设置有多根信号线20，每一根信号线20用于与集成电路芯片连接的部位设置有至少两个不同厚度的粘结层6和8，各粘结层之间通过导电金属层11电连接。
例如，导电金属层11可以与阵列基板中的透明导电层同层形成，该透明导电层所采用的材料可以为铟锡金属氧化物ITO（Indium TinOxides，简称ITO）或者是，铟锌氧化物(Indium Zinc Oxide,简称IZO），或其他透明导电材料，并且，该透明导电层可以是阵列基板中的像素电极层或者公共电极层。
其中各粘结层为金属材料制成，具体的粘结层6和8均为金属层。
优选地，本实施例中的粘结层的数量为两个，其中一个粘结层8与阵列基板上的源漏金属层同层设置且材料相同，另一粘结层6与阵列基板上的栅极电极层同层设置且材料相同。
优选地，本实施例中的通过在导电金属层11上开孔将信号线20输出端引出到阵列基板的表面，并与集成电路芯片连接。
优选地，本实施例中的多根信号线20分为至少两层，在图5中利用不同填充表示两层信号线，每层信号线之间用于与集成电路芯片连接的部位设置的粘结层互不重叠。
上述绑定垫片进行IC绑定后的剖面图如图5所示，包括导电金属层11以及与栅极电极层同层形成的粘结层6和与源漏金属层同层形成的粘结层8，其中的导电金属层可以为透明金属氧化物形成，例如ITO层。
本发明的改进点就是在于一个垫片包括两个不同厚度的粘结层，即一个是与栅极电极层同层形成的粘结层6，另一个是与源漏金属层同层形成的粘结层8。因此也可以说本实施例中的一个垫片包括两部分，第一垫片和第二垫片，这两个金属垫片均在一层信号线上，并通过导电金属层11实现两者之间的连接，够避免由于垫片的存在导致的厚度差异。
进一步地，对图5中结构沿着C-C’剖开得到的示意图如图6所示，对图5中结构沿着D-D’剖开得到的示意图如图7所示，其中图6中和图7中都包括驱动IC1、衬底基板4、与源漏金属层同层形成的粘结层8、与栅极电极层同层形成的粘结层6、绝缘层9、导电球10和导电金属层11。图6中经过一次构图工艺形成在衬底基板4的上方与阵列基板上栅极电极层同层形成的粘结层6，继续在与栅极电极层同层形成的粘结层6上方形成绝缘层9，并刻蚀掉与栅极电极层同层形成的粘结层6上方的绝缘层9，只保留部分绝缘层9，在与栅极电极层同层形成的粘结层6的上方再沉积一层金属层，最后经过刻蚀只保留与栅极电极层同层形成的粘结层6上方和绝缘层9上方部分区域以及绝缘层9边缘的导电金属层11，最后导电球10位于驱动IC1和导电金属层11之间。
图6和图7的不同之处：图6中与栅极电极层同层形成的粘结层6处的导电球未被压缩，与源漏金属层同层形成的粘结层处的导电球被压缩，而图7中与栅极电极层同层形成的粘结层处的导电球被压缩，与源漏金属层同层形成的粘结层处的导电球未被压缩。由于每一层信号线或者说每一根信号线上的垫片都包括两种不同厚度的粘结层，总能保证有一个粘结层处的金属球通过导电金属层和导电球实现与驱动IC之间的电连接，避免由于一根信号线上只有一种厚度的金属层时，由于金属层偏移导致的绑定不良现象的发生。
综上所述，本实施例中的绑定垫片通过改变现有垫片只有一个垫片的设计结构，在一个绑定位置设置两个金属垫片，分别与栅极电极层和源漏金属层同层形成，并通过导电金属层将二者连接，可以避免膜厚差异和金属层的偏移造成的绑定异常，减少由于绑定异常造成的布线不良的发生。
实施例二
本发明还提供了一种显示装置的制造方法，步骤流程图如图8所示，具体包括以下步骤：
步骤S101、通过第一次构图工艺在阵列基板周边区域形成包括多根信号线的图形；
步骤S102、通过第二次构图工艺在每一根信号线用于与集成电路芯片连接的部位形成至少两个不同厚度的粘结层的图形；
步骤S103、通过第三次构图工艺形成导电金属层电的图形，且各粘结层之间通过导电金属层电连接。
优选地，本实施例中的各粘结层可金属材料形成。
优选地，本实施例中第二次构图工艺形成两个不同厚度的粘结层的图形的步骤中，一个粘结层与阵列基板上的源漏金属层同层设置且材料相同，另一粘结层与阵列基板上的栅极电极层同层设置且材料相同。
优选地，本实施例中第三次构图工艺中导电金属层与阵列基板中的透明导电层同层形成。
优选地，本实施例中第三次构图工艺后还包括：在导电金属层上开孔，以将信号线输出端引出到阵列基板的表面与集成电路芯片连接。
优选地，本实施例中第一次构图工艺中形成的多根信号线图形分为至少两层，每层信号线之间用于与集成电路芯片连接的部位设置的粘结层互不重叠。
通过使用本实施例中提供的阵列基板的制造方法，通过改变现有垫片只有一个垫片的设计结构，在一个绑定位置设置两个金属垫片，分别与栅极电极层和源漏金属层同层形成，并通过导电金属层将二者连接，可以避免膜厚差异和金属层的偏移造成的绑定异常，减少由于绑定异常造成的布线不良的发生。
实施例三
本发明实施例三还提供了一种显示装置，包括驱动集成电路芯片，还包括本发明实施例提供的阵列基板，所述阵列基板上的粘结层通过各向异性胶与所述驱动集成电路连接。
以上实施方式仅用于说明本发明，而并非对本发明的限制，有关技术领域的普通技术人员，在不脱离本发明的精神和范围的情况下，还可以做出各种变化和变型，因此所有等同的技术方案也属于本发明的范畴，本发明的专利保护范围应由权利要求限定。

Claims (13)

1.一种阵列基板，所述基板周边区域设置有多根信号线，其特征在于，每一根信号线用于与集成电路芯片连接的部位设置有至少两个不同厚度的粘结层，各所述粘结层之间通过导电金属层电连接。
2.如权利要求1所述的阵列基板，其特征在于，各所述粘结层为金属材料制成。
3.如权利要求1所述的阵列基板，其特征在于，所述粘结层的数量为两个，其中一个粘结层与阵列基板上的源漏金属层同层设置且材料相同，另一粘结层与阵列基板上的栅极电极层同层设置且材料相同。
4.如权利要求3所述的阵列基板，其特征在于，所述导电金属层与阵列基板中的透明导电层同层形成。
5.如权利要求1所述的阵列基板，其特征在于，通过在所述导电金属层上开孔将信号线输出端引出到阵列基板的表面，并与集成电路芯片连接。
6.如权利要求1所述的阵列基板，其特征在于，所述多根信号线分为至少两层，每层信号线之间用于与集成电路芯片连接的部位设置的粘结层互不重叠。
7.一种权利要求1-6中任一项所述阵列基板的制造方法，其特征在于，所述方法包括：通过第一次构图工艺在所述阵列基板周边区域形成包括多根信号线的图形；通过第二次构图工艺在每一根信号线用于与集成电路芯片连接的部位形成至少两个不同厚度的粘结层的图形；通过第三次构图工艺形成导电金属层的图形，且各所述粘结层之间通过所述导电金属层电连接。
8.根据权利要求7所述的制造方法，其特征在于，各所述粘结层采用金属材料形成。
9.根据权利要求7所述的制造方法，其特征在于，所述第二次构图工艺形成两个不同厚度的粘结层的图形的步骤中，一个粘结层与阵列基板上的源漏金属层同层设置且材料相同，另一粘结层与阵列基板上的栅极电极层同层设置且材料相同。
10.根据权利要求7所述的制造方法，其特征在于，所述第三次构图工艺中导电金属层与阵列基板中的透明导电层同层形成。
11.根据权利要求7所述的制造方法，其特征在于，所述第三次构图工艺后还包括：在所述导电金属层上开孔，以将信号线输出端引出到阵列基板的表面与集成电路芯片连接。
12.根据权利要求7所述的制造方法，其特征在于，所述第一次构图工艺中形成的多根信号线图形分为至少两层，每层信号线之间用于与集成电路芯片连接的部位设置的粘结层互不重叠。
13.一种显示装置，包括驱动集成电路芯片，其特征在于，还包括权利要求1-6中任一项所述的阵列基板，所述阵列基板上的粘结层通过各向异性胶与所述驱动集成电路连接。
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CN103680317B (zh) * 2013-12-20 2015-09-23 合肥京东方光电科技有限公司 一种阵列基板及其制造方法和显示装置
CN104460154A (zh) * 2014-12-15 2015-03-25 京东方科技集团股份有限公司 阵列基板及其制备方法、显示装置
CN109949703B (zh) * 2019-03-26 2021-08-06 京东方科技集团股份有限公司 柔性显示基板、显示面板、显示装置及制作方法
CN112086424B (zh) * 2019-06-14 2023-06-23 群创光电股份有限公司 接合垫结构
CN111552129B (zh) * 2020-05-25 2023-10-13 Tcl华星光电技术有限公司 液晶显示面板
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JP2789293B2 (ja) * 1993-07-14 1998-08-20 株式会社半導体エネルギー研究所 半導体装置作製方法
US6162667A (en) * 1994-03-28 2000-12-19 Sharp Kabushiki Kaisha Method for fabricating thin film transistors
TW200415393A (en) * 2003-01-15 2004-08-16 Toshiba Matsushita Display Tec LCD device
KR101209489B1 (ko) * 2003-08-22 2012-12-07 엘지디스플레이 주식회사 액정표시장치
JP2006073994A (ja) * 2004-08-05 2006-03-16 Seiko Epson Corp 接続用基板、接続構造、接続方法並びに電子機器
KR20060085450A (ko) * 2005-01-24 2006-07-27 삼성전자주식회사 표시 패널용 기판 및 이를 구비한 표시 패널
KR101074383B1 (ko) * 2005-06-30 2011-10-17 엘지디스플레이 주식회사 액정표시장치 및 그의 제조방법
KR101329078B1 (ko) * 2008-05-28 2013-11-12 엘지디스플레이 주식회사 액정표시장치 및 그 제조방법
KR101034750B1 (ko) * 2008-12-08 2011-05-17 엘지디스플레이 주식회사 표시 장치 및 그 제조 방법
EP2657974B1 (en) * 2010-12-20 2017-02-08 Sharp Kabushiki Kaisha Semiconductor device and display device
CN102629046B (zh) * 2011-06-29 2015-05-20 北京京东方光电科技有限公司 阵列基板及其制造方法、液晶显示器件
CN202307895U (zh) * 2011-10-21 2012-07-04 北京京东方光电科技有限公司 一种tft阵列基板及液晶显示器
CN202433650U (zh) * 2011-12-08 2012-09-12 上海天马微电子有限公司 阵列基板、液晶面板和液晶显示器
CN103064223B (zh) * 2013-01-07 2015-02-11 京东方科技集团股份有限公司 一种阵列基板和一种显示面板
CN103219392B (zh) * 2013-04-10 2017-04-12 合肥京东方光电科技有限公司 薄膜晶体管、阵列基板、制备方法以及显示装置
CN103278972B (zh) * 2013-04-28 2015-09-09 合肥京东方光电科技有限公司 一种阵列基板及显示装置
CN203275842U (zh) * 2013-06-09 2013-11-06 合肥京东方光电科技有限公司 一种阵列基板及显示装置
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