CN103647542B - Pre-weight reduction circuit for high-speed serialization deserializer - Google Patents
Pre-weight reduction circuit for high-speed serialization deserializer Download PDFInfo
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- CN103647542B CN103647542B CN201310597942.8A CN201310597942A CN103647542B CN 103647542 B CN103647542 B CN 103647542B CN 201310597942 A CN201310597942 A CN 201310597942A CN 103647542 B CN103647542 B CN 103647542B
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- loss
- weight
- amplitude controller
- transmission gates
- output stage
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- 239000013585 weight reducing agent Substances 0.000 title abstract description 6
- 230000005540 biological transmission Effects 0.000 claims abstract description 30
- 208000020442 loss of weight Diseases 0.000 claims description 57
- 230000000694 effects Effects 0.000 abstract description 4
- 238000013461 design Methods 0.000 description 9
- 238000000034 method Methods 0.000 description 9
- 238000004891 communication Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005562 fading Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003472 neutralizing effect Effects 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 208000016261 weight loss Diseases 0.000 description 1
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Abstract
The invention discloses a pre-weight reduction circuit for a high-speed serialization deserializer, which comprises a resistance voltage divider, a weight reduction amplitude controller and an output stage, wherein the resistance voltage divider and the output stage are connected with the weight reduction amplitude controller. The resistor voltage divider comprises thirty-one equivalent resistors and a first resistor with a resistance value larger than the equivalent resistors, which are sequentially connected in series. The weight-reducing amplitude controller is also connected with an inverter and an external input signal end. The weight reduction amplitude controller is of a tree structure, five columns are provided, and each column is controlled by thirty transmission gates, sixteen transmission gates, eight transmission gates, four transmission gates and two transmission gates. The output stage consists of a multiplexer, a voltage buffer and an operational amplifier which are connected in sequence. The invention can be used for the sending end of a high-speed serialization deserializer, and can reduce the weight of each bit after the first bit in the same polarity bit string, thereby achieving the effect of reducing the amplitude of low-frequency data in advance, compensating the high-frequency attenuation of a channel, and improving the transmission bandwidth on the premise of ensuring the error rate.
Description
Technical field
The present invention relates to a kind of pre- loss of weight circuit, more particularly to a kind of pre- loss of weight electricity for high speed SerDes
Road, belongs to analog communication techniques field.
Background technology
In Modern Communication System, serial data communication can save interconnection resources, and the requirement to signal amplitude is little, and signal it
Between crosstalk it is little, transfer rate is high, is widely used in various high-speed communication standards, such as Ethernet, fiber optic communication, core bus
Deng.
When transmission high-speed serial data on larger link is lost, channel can be abstracted into a low pass filter.This
There is distortion in the data that can make transmission, increase the bit error rate of the data in receiving terminal.Additionally, maximum in the design of high speed SerDes
Problem be data processing time control, this be also restrict drive bandwidth key factor.With carrying for drive bandwidth
Height, when the bit wide of each data is less than the position process time of driver, the value of previously sent signal will affect present bit
Waveform, that is, there is intersymbol interference.Intersymbol interference easily occurs when identical numbered of one group of serial data stream comprising multiple bits
According to, and followed by short bit opposite value data when.Prolonged steady state value is fully charged to channel electric capacity, immediately
In the contrary data bit cannot reverse compensation, the magnitude of voltage for making contrary data is possible without being detected, so as to code occur
Between disturb.Intersymbol interference reduces the peak frequency that system can be run.
The content of the invention
The technical problem to be solved is to provide a kind of pre- loss of weight circuit for high speed SerDes, and its is right
First afterwards each implements loss of weight in identical polar bit string, and first in identical polar bit string not loss of weight can be applied
In the transmitting terminal of high speed SerDes, the effect for reducing low-frequency data amplitude in advance is can reach, compensates the high frequency attenuation of channel,
Transmission bandwidth is improved on the premise of the bit error rate is ensured.
The present invention is to solve above-mentioned technical problem by following technical proposals：It is a kind of for high speed SerDes
Pre- loss of weight circuit, it is characterised in that it includes resitstance voltage divider, loss of weight amplitude controller, output stage, resitstance voltage divider, output
Level is all connected with loss of weight amplitude controller.
Preferably, the resitstance voltage divider include 31 substitutional resistances being sequentially connected in series and a resistance value more than etc.
The first resistor of value resistance.
Preferably, the resistance of the first resistor is the 40 octuple of substitutional resistance.
Preferably, the loss of weight amplitude controller is also connected with a phase inverter, an external input signal end.
Preferably, the external input signal end is input into five external input signals, and five external input signals are used to control
Loss of weight amplitude processed；Five external input signals distinguish inverted device and generate five bit Inverting signals.
Preferably, the loss of weight amplitude controller is tree structure, has five row, each column respectively by 30 transmission gates, ten
Six transmission gates, eight transmission gates, four transmission gates, two transmission gate controls.
Preferably, the output stage is made up of the multiplexer, voltage buffer, operational amplifier that are sequentially connected.
Preferably, the resitstance voltage divider exports 32 reference voltages as the input of loss of weight amplitude controller.
The present invention positive effect be：The present invention can effectively simplify pre- loss of weight circuit structure, so as to reduce realization
Number of transistors needed for pre- loss of weight function, can reduce the area and cost of chip, and reduce power consumption when using.The present invention can
Loss of weight amplitude is flexibly controlled by five external input signals, the 32 kinds of loss of weight amplitudes not waited from 0～-4.3dB are realized.
Description of the drawings
Fig. 1 is structural representation of the present invention for the pre- loss of weight circuit of high speed SerDes.
Fig. 2 is the structural representation of resitstance voltage divider in the present invention.
Fig. 3 is the structural representation of loss of weight amplitude controller in the present invention.
Fig. 4 is the structural representation of output stage in the present invention.
Specific embodiment
Present pre-ferred embodiments are given below in conjunction with the accompanying drawings, to describe technical scheme in detail.
As shown in Figures 1 to 4, the present invention includes resitstance voltage divider, subtracts for the pre- loss of weight circuit of high speed SerDes
Weight amplitude controller, output stage, resitstance voltage divider, output stage are all connected with loss of weight amplitude controller.Resitstance voltage divider include according to
The first resistor of 31 substitutional resistances of secondary series connection and resistance value more than substitutional resistance.Loss of weight amplitude controller also with
One phase inverter, an external input signal end connection.Loss of weight amplitude controller is tree structure, has five row, each column respectively by
30 transmission gates, 16 transmission gates, eight transmission gates, four transmission gates, two transmission gate controls.Output stage is by connecting successively
Multiplexer, voltage buffer, the operational amplifier composition for connecing.
32 resistance of resitstance voltage divider（R0 to R31）Resistance string on 32 taps be designated as Vref
[0] to Vref [31], 32 different transmission amplitude reference voltages can be produced.Wherein, the resistance of first resistor can be
The 40 of substitutional resistance are octuple.External input signal end is input into five external input signals（De_empha [0] can be expressed as extremely
de_empha[4]）, five external input signals are used to control loss of weight amplitude；Five external input signals distinguish inverted device life
Into five bit Inverting signals（Den_empha [0] to den_empha [4] can be expressed as）.Five external input signals and five are anti-
Phase signals co- controlling transmission gate switch.Its conducting when the control signal of transmission gate is " 1 ".Transmission gate is designated as S (p, q), than
" S [0,1] " such as in figure etc..Resitstance voltage divider output 32 reference voltages as loss of weight amplitude controller input,
Correspond respectively to the 32 kinds of loss of weight amplitudes not waited from 0～-4.3dB.The input of 32 tunnels is by tree structure and output phase
Even, every input all the way is connected through five transmission gate switches with output Vref_tx.If p is even number, S (p, q)=Den_empha
[q-1]；If p is odd number, S (p, q)=De_empha [q-1].If de_empha [4:0] binary number for representing is i, then export
Vref_tx=vref [i].If input signal bitmap=1 of output stage, multiplexer output v1=vp（Supply voltage）；If
Bitmap=0, multiplexer output v1=vref_tx.Driving force is increased by voltage buffer.Vp_tx=v1.Computing is put
Big device is input into by differential data of Txip/m.Vp_tx is used as the power supply of output stage operational amplifier.During bitmap=1, without loss of weight
Function, the amplitude of amplifier differential output signal txop/txom is 1.2V；During bitmap=0, the amplitude of txop/txom is matched somebody with somebody before
Loss of weight amplitude vp_tx put.
The present invention can be used for the transmitting terminal of high speed SerDes, to first afterwards each in identical polar bit string
Implement loss of weight, can reach the effect for reducing low-frequency data amplitude in advance, the high frequency attenuation of channel is compensated, before the bit error rate is ensured
Put raising transmission bandwidth.Pre- loss of weight is realized according to which, the Analog Circuit Design flow process with available standards is realized, can be subtracted
Minor clock restoring circuit complexity, area, power consumption, and can flexibly be controlled with input signal, realize various（32 kinds）Loss of weight
The characteristics of amplitude.
The present invention chooses whether loss of weight for the pre- loss of weight circuit of high speed SerDes using a control signal.Control
Signal is provided by digital circuit.When the position is 1, instruction does not need the peak-to-peak value of loss of weight, transmitting terminal output difference signal to be
1.2V.When the position is 0, instruction needs loss of weight, output difference signal to export by the loss of weight amplitude of setting.For high speed string neutralizing
The structure of the pre- loss of weight circuit of string device is as far as possible simple.The structure of pre- loss of weight circuit is simpler, needed for realizing pre- loss of weight function
Number of transistors is fewer, and the area of such chip is less, and chip cost is reduced, and in addition power consumption also will reduce；The present invention can
Loss of weight amplitude is flexibly controlled by five external input signals, the 32 kinds of loss of weight amplitudes not waited from 0～-4.3dB are realized.Pre- loss of weight
Circuit is realized completely using analog circuit, and supports the Analog Circuit Design flow process of standard.The Analog Circuit Design stream of standard
Cheng Caiyong EDA (Electronic Design Automatic：Electric design automation) instrument Aided Design, improves design effect
Rate.Pre- loss of weight circuit is realized using analog circuit, and supports board design flow process, can be simplified and for the circuit is integrated into stringization
Difficulty in deserializer transmitting terminal, improves circuit reliability.
The present invention improves signal waveform for the decay of thermal compensation signal HFS using balancing technique.Balancing technique
It is a kind of technological means for improving signal transmission quality, it can to a great extent compensate high frequency loss.Balancing technique
Generally comprise transmitting terminal balanced balanced with receiving terminal.Transmitting terminal is balanced to be also referred to as preequalization, can pass through pre- loss of weight circuit realiration.Fortune
Pre- Technology of Weight Reduction is used, first amplitude fading is carried out to low-frequency data in transmitting terminal, here it is it can compensate for the pass of high frequency attenuation
Key is located.Its operation principle is：When signal occurs saltus step, circuit is constant to signal drive amplitude；And it is any in signal
Consecutive identical numerical value in, reduce drive volume, make signal swing decrease.This is because the high fdrequency components of signal focus mostly on
The hopping edge of data；And when consecutive identical numerical value occur in data, more based on low frequency component, at this time data are declined
Subtract, that is, the low frequency component of the data that decayed, thus, just having reached the purpose of pre- loss of weight circuit decay low frequency.In addition, the present invention is logical
Cross when signal occurs saltus step, circuit is constant to the amplitude that signal drives, and in the arbitrary consecutive identical numerical value of signal,
The means of drive volume are reduced, the speed of saltus step generation is greatly speeded up, so as to reduce intersymbol interference, when accelerating the process of data
Between.So as on the premise of the receiving terminal bit error rate is ensured, improve the bandwidth of driver.
Particular embodiments described above, the technical problem, technical scheme and beneficial effect to the solution of the present invention is carried out
Further describe, should be understood that the specific embodiment that the foregoing is only of the invention, be not limited to
The present invention, all any modification, equivalent substitution and improvements within the spirit and principles in the present invention, done etc., should be included in this
Within the protection domain of invention.
Claims (5)
1. a kind of pre- loss of weight circuit for high speed SerDes, it is characterised in that it includes resitstance voltage divider, loss of weight amplitude
Controller, output stage, resitstance voltage divider, output stage are all connected with loss of weight amplitude controller, the outfan of resitstance voltage divider with subtract
The input of weight amplitude controller is connected, and the outfan of loss of weight amplitude controller is connected with the input of output stage；
The loss of weight amplitude controller is also connected with a phase inverter, an external input signal end；
The external input signal end is input into five external input signals, and five external input signals are used to control loss of weight amplitude；
Five external input signals distinguish inverted device and generate five bit Inverting signals；
The loss of weight amplitude controller is tree structure, has five row, each column respectively by 30 transmission gates, 16 transmission gates,
Eight transmission gates, four transmission gates, two transmission gate controls.
2. the pre- loss of weight circuit of high speed SerDes is used for as claimed in claim 1, it is characterised in that the electric resistance partial pressure
Device includes the first resistor of 31 substitutional resistances being sequentially connected in series and a resistance value more than substitutional resistance.
3. the pre- loss of weight circuit of high speed SerDes is used for as claimed in claim 2, it is characterised in that the first resistor
Resistance be the 40 octuple of substitutional resistance.
4. the as claimed in claim 1 pre- loss of weight circuit for being used for high speed SerDes, it is characterised in that the output stage by
Multiplexer, voltage buffer, the operational amplifier composition being sequentially connected.
5. the pre- loss of weight circuit of high speed SerDes is used for as claimed in claim 1, it is characterised in that the electric resistance partial pressure
Device exports 32 reference voltages as the input of loss of weight amplitude controller.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310597942.8A CN103647542B (en) | 2013-11-22 | 2013-11-22 | Pre-weight reduction circuit for high-speed serialization deserializer |
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|---|---|---|---|
| CN201310597942.8A CN103647542B (en) | 2013-11-22 | 2013-11-22 | Pre-weight reduction circuit for high-speed serialization deserializer |
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| Publication Number | Publication Date |
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| CN103647542A CN103647542A (en) | 2014-03-19 |
| CN103647542B true CN103647542B (en) | 2017-05-03 |
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| CN201310597942.8A Active CN103647542B (en) | 2013-11-22 | 2013-11-22 | Pre-weight reduction circuit for high-speed serialization deserializer |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102055314A (en) * | 2010-11-16 | 2011-05-11 | 香港应用科技研究院有限公司 | Programmable EMI suppression with enhanced noise immunity and process tolerance |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8736306B2 (en) * | 2011-08-04 | 2014-05-27 | Micron Technology, Inc. | Apparatuses and methods of communicating differential serial signals including charge injection |
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102055314A (en) * | 2010-11-16 | 2011-05-11 | 香港应用科技研究院有限公司 | Programmable EMI suppression with enhanced noise immunity and process tolerance |
Non-Patent Citations (1)
| Title |
|---|
| 一种2.5Gb/s带预加重结构的低压差分串行发送器;韦雪明等;《微电子学》;20110321;第40卷(第6期);第770-773页 * |
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| CN103647542A (en) | 2014-03-19 |
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