CN103645879B - Execution controller for floating-point number division operation - Google Patents

Abstract

A floating-point number division execution controller includes a floating-point operand configuration control module, a floating-point number division operator, a pulse generation distribution controller, and a result output control module; Under the control of timing pulses generated by the distribution controller, the selection and configuration of the two operands involved in the calculation and the latching of the calculation results are completed independently, without the need for the system to apply timing control pulses to the operation process of the execution controller. The execution controller can realize four processing methods of division operation, execute two operands from the system data bus, and can also execute one operand is the result of the last operation, avoiding the need to transfer the instruction to the end of each instruction operation. The process of writing back the operation result, and in the process of floating-point number division operation, the system can read the result of the last operation from the execution controller in parallel, which improves the speed of the system to execute the sequence of floating-point number division operation instructions.

Description

Floating-point division execution controller

technical field

The invention relates to a floating-point number division operation execution controller, in particular to a floating-point number division operation control circuit and a timing control method based on the hard connection of an FPGA parallel operation circuit.

Background technique

With the continuous improvement of modern science and technology on the accuracy of data operations and the continuous expansion of the range of numerical operations, the application of floating-point operations has become more and more important. In the instruction system of the microprocessor, the floating-point number division instruction is used to realize the division operation of two 32-bit floating-point numbers conforming to the IEEE754 standard. Module, under the control of timing pulses issued by the microprocessor control unit, multiple floating-point number division instructions are executed in the order of the modules, and the operation result needs to be written back after the operation of each instruction in the pipeline. However, for the executed floating-point number division instruction that needs to use the operation result of the previous operation instruction as an instruction, the pipeline operation of the floating-point number division operation loses its effect, which affects the execution speed of the floating-point number division operation instruction, and usually many operations Both need to apply the last operation result as the operand of this operation; division needs to realize the last operation result/operand, or operand/last operation result. For example, if there are multiple continuous division operations, such as 7 operands, each operation needs to use the operation result of the last division operation as the operand, and 6 floating-point number division operation instructions are required to implement it. To execute these 6 instructions, the operation needs to be The result is written back 6 times, and the operand is transmitted to the floating-point number division operator 12 times. It is necessary to change the address of the transmission operand and the address of the write-back operation result according to the timing requirements of data transmission, and the operation result is sent to the floating-point number division operation as an operand. The process of writing back an input terminal and the operation result is processed in a time-sharing manner, which is not conducive to further improving the execution speed of arithmetic operation instructions.

Contents of the invention

The object of the present invention is to provide a kind of floating-point number division execution controller that can independently complete the floating-point number division operation function; the floating-point number division operation execution controller uses FPGA to design hard-wired control circuits, and the operand is 32 bits that meet the IEEE754 standard. For floating-point numbers, the two operands of the division operation either come from the system data bus, or one of the operands is the operation of the last operation result, and can execute the last operation result/operand, operand/last operation result, The division operation of the first operand/second operand, the second operand/the first operand, the selection and configuration of the operands are completed independently under the control of the internal sequence of the execution controller, and the operation process does not need The system applies timing control pulses, and in the process of floating-point number division, the system can read the result of the last operation from the floating-point division execution controller, so as to overcome the shortcomings of the prior art.

The technical solution for solving the above-mentioned technical problems is: a floating-point number division operation execution controller, which is used to realize two 32-bit floating-point number division operations conforming to the IEEE754 standard, including a floating-point operand configuration control module, a floating-point number division operator, Pulse generation distribution controller and result output control module;

The floating-point operand configuration control module is connected with the floating-point number division operator, the pulse generation distribution controller, and the result output control module;

The floating-point number division operator is also connected with the result output control module;

The pulse generation distribution controller is also connected with the result output control module;

The floating-point operand configuration control module configures the floating-point number division operator according to the operand type and the operation mode. The operand 1 is from the last operation result, and also from the floating-point operand of the system data bus DB. Under the control of the timing pulse output by the distribution controller, the selection of operand 1 input by the floating-point number division operator, and the configuration and latching of operand 1 and operand 2 are completed;

The floating-point number division operator performs operations on the operand 1 and the operand 2 output by the floating-point operand configuration control module, and outputs the result of the division operation;

The pulse generation distribution controller, under the condition of satisfying the start-up work, sends out the timing pulse configured by operand 1 and operand 2 according to the type of operand, the latch signal of the operation result of the floating-point number division operator, and the end of the division operation signal; the pulse generation distribution controller automatically starts the work of the pulse generation distribution controller under the condition of satisfying the cycle start;

The result output control module latches the result of the division operation under the action of the result latch signal output by the pulse generation distribution controller, and judges whether the result of the division operation is abnormal, and the system can read the result of the division operation.

Its further technical solution is: the floating-point operand configuration control module includes a strobe, an operation result register, an operand register, an operand switch, a NOT gate I, an OR gate I, an OR gate II, and an AND gate I;

One input end of the strobe is connected to the system data bus DB, the other input end is connected to the result output control module, the output end is connected to the input end of the operation result register, and the strobe control input end is connected to the operand type input of the system line connection;

The latch pulse input end of the operation result register is connected to the pulse generation distribution controller, and the output end is connected to the exchange number 1 input end of the operand switcher;

The input end of the operand register is connected to the system data bus DB, the latch pulse input end is connected to the output end of the AND gate 1, and the output end is connected to the exchange number 2 input end of the operand switcher;

The exchange control input end of the operand switcher is connected with the operation mode input line of the system; the operand 1 output end is connected with the operand 1 input end of the floating-point number division operator, and the operand 2 output end is connected with the floating-point number division operator The operand 2 input terminal connection;

The input end of the NOT gate I is connected to the operand type input line of the system, and the output end is connected to an input end of the OR gate I;

The other input end of the OR gate I is connected to the pulse generation distribution controller, and the output end is connected to an input end of the AND gate I;

One input end of the OR gate II is connected to the pulse generation distribution controller, the other input end is connected to the operand type input line of the system, and the output end is connected to an input end of the AND gate I.

Its further technical solution is: the pulse generation distribution controller includes a pulse generator, a type register, an OR gate III, an OR gate IV, a NOT gate II, an OR gate V and an AND gate II;

The reset input terminal of the pulse generator is connected with the reset Rst line of the system, the start input terminal is connected with the output terminal of OR gate III, the cycle start input terminal is connected with the output terminal of AND gate II, and the pulse synchronization input terminal is connected with the system clock Clock The type input terminal is connected to the output terminal of the type register, the pulse ① output terminal is connected to the latch pulse input terminal of the operation result register, or an input terminal of the OR gate II; the pulse ② output terminal is connected to the other input terminal of the OR gate I connected to the latch input terminal of the type register; the pulse ③ output terminal is connected to an input terminal of the OR gate IV; the pulse ④ output terminal is connected to an input terminal of the OR gate V; the result latch output terminal is connected to the result output control module , the operation end output terminal outputs an operation end signal to the system;

The input end of the type register is connected to the system operand type input line, and the operand type output end is also connected to another input end of the OR gate IV and an input end of the NOT gate II;

The two input terminals of the OR gate III are respectively connected to the enable signal CS line and the write signal WR line of the system;

The output end of the OR gate IV is connected to an input end of the AND gate II;

The output end of the NOT gate II is connected to the other input end of the OR gate V;

The output end of the OR gate V is connected to the other input end of the AND gate II;

The output end of the AND gate II is also connected to the result output control module;

The pulse 1., pulse 2., pulse 3. and pulse 4. of the pulse generator output are synchronized with the system clock Clock, that is, the system clock Clock is the synchronous pulse of the pulse generation and distribution controller;

When the operand type is "0", the pulse generation distribution controller is under the action of the falling edge of pulse ②, the output state of the type register is "0", and the output state of OR gate V is "1". Under the action of the OR gate IV, the output of the OR gate IV changes from "1" to "0", and the output of the AND gate II also changes from "1" to "0", which is used as the cycle start signal of the pulse generator and the result latch of the result output control module Signal;

When the operand type is "1", the pulse generation distribution controller is under the action of the falling edge of pulse ②, the output state of the type register is "1", and the output state of OR gate IV is "1". Under the effect of , the output of OR gate V changes from "1" to "0", then the output of AND gate II also changes from "1" to "0", which is used as the cycle start signal of the pulse generator and the result latch of the result output control module Signal;

When the operation of the pulse generator ends and the output terminal is "0" and CS is "0", under the action of the falling edge of the WR signal, the signal at the start input terminal changes from "1" to "0", and the start pulse generator works , after the pulse generator is started to work, set the operation end signal output terminal to "1"; if the start input terminal is "0", the cycle start input terminal is changed from "1" to "0", and the pulse generator is started to work; if it is started The signal at the input terminal is "1", the signal at the input terminal of the cycle start changes from "1" to "0", and the operation end signal is sent to the system, the pulse generator stops working, and the output terminals of pulse ①, pulse ②, pulse ③ and pulse ④ are all When it is in the state of "1", the output terminal of the operation end is in the state of "0"; when the reset input terminal is "0", the pulse generator is reset, and the output terminals of pulse ①, pulse ②, pulse ③ and pulse ④ are all in the state of " 1” state, the output end of the operation is in the “0” state.

Its further technical solution is: the result output control module includes a result output register, operation exception flag control, 32-bit tri-state gate group and OR gate VI;

The operation result input end of the described result output register is connected with the operation result output end of the floating-point number division operator, and the operation result output end is connected with the input end of the 32-bit tri-state gate group, the operation result input end controlled by the abnormal operation flag, and the gate One input terminal of the device is connected, and the result latch input terminal is connected with the output terminal of AND gate II;

The operation result input terminal controlled by the operation exception flag is connected to the operation result output terminal of the result output register, and the result latch input terminal is connected to the output terminal of AND gate II; the output terminal outputs an interrupt request signal IRQ, and when the operation result is abnormal , the output terminal sends an interrupt request signal IRQ to the system;

The control input terminal of the 32-bit tri-state gate group is connected to the output terminal of the OR gate VI, and the output terminal is connected to the system data bus DB;

The two input terminals of the OR gate VI are respectively connected to the system enable signal CS and the read signal RD line;

The 32-bit tri-state gate output result output register outputs the operation result. When the enable signal CS is "0" and the read signal RD is "0", the output of the OR gate VI is "0", controlling the 32-bit tri-state The gate group outputs the result of the last operation.

Its further technical solution is: the floating-point operand configuration control module and the pulse generation distribution controller are controlled by the system operand type and operation mode:

When the operand type is "0": the selector outputs the operation result output by the output register, and under the action of the falling edge of pulse ① output by the pulse generator, the operation result register latches the operation result output by the result output register, or The output terminal of gate II changes from "1" to "0", the output terminal of AND gate I changes from "1" to "0", and the operand register latches the operand from the system bus DB, then the processing of the division operation is as follows: ways:

The operation mode is "0": the operation result of the exchange number 1 input terminal of the operand switcher is transmitted to the operand 1 input terminal of the floating-point number division operator, and the operand of the exchange number 2 input terminal of the operand switcher is transmitted to the floating point number The input terminal of the operand 2 of the division operator, the floating-point number division operator implements the calculation of the operation result/operand;

The operation mode is "1": the operation result of the input terminal of the exchange number 1 of the operand switcher is transmitted to the input terminal of the operand 2 of the floating-point number division operator, and the operand of the input terminal of the exchange number 2 of the operand switcher is transmitted to the floating-point number The input terminal of the operand 1 of the division operator realizes the exchange of two numbers, and the floating-point number division operator implements the operation of the operand/operation result;

When the operand type is "1": the selector outputs the first operand from the system bus DB, and under the action of the falling edge of pulse ① output by the pulse generator, the operation result register latches the first operand of the system bus DB operand, the output terminal of OR gate II is "1", and the output terminal of NOT gate I is "0". The operand register latches the second operand from the system bus DB, and the division operation is processed in the following two ways:

The operation mode is "0": the first operand of the system bus DB at the input end of the operand switch 1 is transmitted to the input end of the operand 1 of the floating-point number division operator, and the exchange number 2 of the operand switch is input The second operand of the system bus DB at the end is transmitted to the input end of the operand 2 of the floating-point number division operator, and the floating-point number division operator implements the operation of the first operand/the second operand;

The operation mode is "1": the first operand at the input terminal of the exchange number 1 of the operand switcher is transmitted to the input end of the operand 2 of the floating-point number division operator, and the system bus DB at the input end of the exchange number 2 of the operand switcher The second operand of the floating-point number division operator is transmitted to the input terminal of operand 1 of the floating-point number division operator to realize the exchange of two numbers, and the floating-point number division operator implements the operation of the second operand/the first operand.

Due to the adoption of the above structure, the floating-point number division execution controller of the present invention has the following beneficial effects:

1. The execution of the division operation is completed by the autonomous control of the executive controller

The floating-point number division execution controller of the present invention fully utilizes the FPGA parallel processing function, the execution controller is selected by the system, and the pulse generation and distribution controller is started, and the floating-point number division operation execution controller is under the action of the timing pulse of the internal pulse generation distribution controller. The selection and configuration of the operands and the latching of the operation results are completed independently, and the system does not need to apply timing control pulses to the operation processing process of the execution controller of the floating-point number division operation.

2. Control and implement four division operation processing methods

The operand of the floating-point number division execution controller of the present invention is a 32-bit floating-point number conforming to the IEEE754 standard, and can perform operation results/operands, operands/operation results, and the first operand/the first operand according to the operation mode of the operands. Operation with 2 operands, 2nd operand/1st operand.

3. The operation process reads out the last operation result in parallel

In the floating-point number division execution controller of the present invention, during the floating-point number division operation process, the system can read out the last operation result in parallel from the floating-point number division execution controller.

Fourth, the executive controller is cost-effective

The floating-point number division operation executive controller of the present invention takes the hard-wired control circuit of FPGA as the core, and according to the type of operands, under the action of the timing pulse of the internal pulse generation and distribution controller, the selection and configuration of the operands and the lock of the operation results are completed autonomously. It does not require the system to apply timing control pulses to the operation processing process of the floating-point division execution controller. The system can read the last operation result in parallel from the floating-point division execution controller, which improves the speed of the system's execution of command sequences. When an exception occurs in the floating-point number division operation, an interrupt request can be sent to the system, which has a high cost performance.

The technical features of the floating-point number division execution controller of the present invention will be further described below in conjunction with the drawings and embodiments.

Description of drawings

Fig. 1: the system structural block diagram of floating-point number division execution controller of the present invention;

Fig. 2: the circuit connection diagram of the floating-point operand configuration control module of the floating-point number division execution controller of the present invention;

Fig. 3: the circuit connection diagram of the pulse generation and distribution controller of the floating-point number division execution controller of the present invention;

Fig. 4: the result output control block diagram of the floating-point number division execution controller of the present invention;

Fig. 5: the timing diagram of the operand type 0 of the floating-point number division execution controller of the present invention;

Fig. 6: the timing diagram of the operand type 1 of the floating-point number division execution controller of the present invention;

Fig. 7: two operand type timing diagrams of the floating-point number division execution controller of the present invention;

In the picture:

I—floating point operand configuration control module, II—floating point number division operator, III—pulse generation distribution controller, IV—result output control module;

1—selector, 2—operation result register, 3—operand register, 4—operand switch, 5—not gate I, 6—or gate I, 7—or gate II, 8—and gate I, 9 —pulse generator, 10—type register, 11—OR gate III, 12—OR gate IV, 13—invert gate II, 14—OR gate V, 15—AND gate II, 16—result output register, 17—operation exception Flag control, 18-32-bit tri-state gate group, 19-or gate Ⅵ.

Explanation of abbreviations in the text:

FPGA－Field Programmable Gate Array, Field Programmable Gate Array;

DB－Data Bus, data bus;

CS-Chip Select, chip select or enable, CS in the figure represents "enable signal";

Clock - clock;

RD-Read, read, the figure represents "read signal";

WR-Write, write, the figure represents "write signal";

IRQ－Interrupt Request, interrupt application, the figure represents "interrupt request signal";

Rst-Reset, reset.

detailed description

Example:

A floating-point number division execution controller, as shown in Figure 1, is used to realize two 32-bit floating-point number division operations that conform to the IEEE754 standard, and is characterized in that: the execution controller includes a floating-point operand configuration control module I, Floating-point division operator II, pulse generation distribution controller III and result output control module IV;

The floating-point operand configuration control module I is connected with the floating-point number division operator II, the pulse generation distribution controller III, and the result output control module IV;

The floating-point number division operator II is also connected to the result output control module IV;

The pulse generation distribution controller III is also connected to the result output control module IV;

The floating-point operand configuration control module I configures the floating-point number division operator II according to the operand type and operation mode. The operand 1 is from the last operation result, and also from the floating-point operand of the system data bus DB. Under the control of the timing pulse output by the pulse generation distribution controller III, the selection of operand 1 input by the floating-point number division operator II, and the configuration and latching of operand 1 and operand 2 are completed;

The floating-point number division operator II performs operations on the operand 1 and operand 2 output by the floating-point operand configuration control module I, and outputs the result of the division operation;

The pulse generation distribution controller III, under the condition of satisfying the start-up work, sends out the timing pulse configured by operand 1 and operand 2 according to the type of the operand, the latch signal of the operation result of the floating-point number division operator II, and the division Operation end signal; the pulse generation and distribution controller III automatically starts the work of the pulse generation and distribution controller III under the condition of satisfying the cycle start;

The result output control module IV latches the result of the division operation under the action of the result latch signal output by the pulse generation distribution controller III, and judges whether the result of the division operation is abnormal, and the system can read the result of the division operation.

As shown in Figure 2, the floating-point operand configuration control module I includes a gate 1, an operation result register 2, an operand register 3, an operand switch 4, a NOT gate I5, an OR gate I6, an OR gate II7 and AND gate Ⅰ 8;

One input end of the gate 1 is connected to the system data bus DB, the other input end is connected to the result output control module IV, the output end is connected to the input end of the operation result register 2, and the gate control input end is connected to the operation of the system Number type input line connection;

The latch pulse input end of the operation result register 2 is connected to the pulse generation distribution controller III, and the output end is connected to the exchange number 1 input end of the operand switcher 4;

The input end of the operand register 3 is connected to the system data bus DB, the latch pulse input end is connected to the output end of the AND gate 18, and the output end is connected to the exchange number 2 input end of the operand switcher 4;

The exchange control input end of the operand switcher 4 is connected with the operation mode input line of the system; the operand 1 output end is connected with the operand 1 input end of the floating-point number division operator II, and the operand 2 output end is connected with the floating-point number division The operand 2 input terminal of the arithmetic unit II is connected;

The input end of the NOT gate I5 is connected to the operand type input line of the system, and the output end is connected to an input end of the OR gate I6;

The other input end of the OR gate I6 is connected to the pulse generation distribution controller III, and the output end is connected to an input end of the AND gate I8;

One input end of the OR gate II7 is connected to the pulse generation distribution controller III, the other input end is connected to the operand type input line of the system, and the output end is connected to an input end of the AND gate I8.

As shown in Figure 3, the pulse generation distribution controller III includes a pulse generator 9, a type register 10, an OR gate III11, an OR gate IV12, a NOT gate II13, an OR gate V14 and an AND gate II15;

The reset input terminal of the pulse generator 9 is connected to the reset Rst line of the system, the start input terminal is connected to the output terminal of the OR gate III11, the cycle start input terminal is connected to the output terminal of the AND gate II15, and the pulse synchronization input terminal is connected to the system clock Clock line connection, the type input terminal is connected with the output terminal of the type register 10, the pulse ① output terminal is connected with the latch pulse input terminal of the operation result register 2, or an input terminal of the OR gate II7; the pulse ② output terminal is connected with the OR gate I6 The other input terminal is connected to the latch input terminal of the type register 10; the output terminal of the pulse ③ is connected to an input terminal of the OR gate IV12; the output terminal of the pulse ④ is connected to an input terminal of the OR gate V14, and the output terminal of the operation is output to the system operation end signal;

The input end of the type register 10 is connected with the system operand type input line, and the operand type output end is also connected with another input end of the OR gate IV 12 and an input end of the NOT gate II 13;

The two input terminals of the OR gate III11 are respectively connected to the enable signal CS line and the write signal WR line of the system;

The output end of the OR gate IV12 is connected to an input end of the AND gate II15;

The output end of the NOT gate II13 is connected to the other input end of the OR gate V14;

The output end of the OR gate V14 is connected to the other input end of the AND gate II15;

The output terminal of the AND gate II15 is also connected with the result output control module IV;

The pulse 1., pulse 2., pulse 3. and pulse 4. of the pulse generator 9 output are synchronous with the system clock Clock, that is, the system clock Clock is the synchronous pulse of the pulse generation and distribution controller III;

When the operand type is "0", the pulse generation distribution controller III is under the action of the falling edge of pulse ②, the output state of the type register 10 is "0", and the output state of the OR gate V14 is "1". Under the action of the falling edge, the output of OR gate IV12 changes from "1" to "0", then the output of AND gate II15 also changes from "1" to "0", which is used as the cycle start signal of pulse generator 9 and the result output control module IV The result latch signal;

When the operand type is "1", the pulse generation distribution controller III is under the action of the falling edge of the pulse ②, the output state of the type register 10 is "1", and the output state of the OR gate IV 12 is "1". Under the action of the falling edge, the output of the OR gate V14 changes from "1" to "0", and the output of the AND gate II15 also changes from "1" to "0", which is used as the cycle start signal of the pulse generator 9 and the result output control module IV The result latch signal;

When the operation end output of the pulse generator 9 is "0" and CS is "0", under the action of the falling edge of the WR signal, the start input signal changes from "1" to "0" to start the pulse generator 9 works, after the pulse generator 9 is started to work, set the operation end signal output terminal to "1"; if the start input terminal is "0", the cycle start input terminal changes from "1" to "0", and the pulse generator 9 is started work; if the signal at the start input terminal is "1", the signal at the cycle start input terminal changes from "1" to "0", and sends an operation end signal to the system, the pulse generator 9 stops working, pulse ①, pulse ②, pulse ③ and pulse The output terminals of ④ are all in the state of "1", and the output terminal of the operation is in the state of "0"; when the reset input terminal is "0", the reset pulse generator 9, pulse ①, pulse ②, pulse ③ and pulse ④ The output ends are all in the "1" state, and the output end is in the "0" state after the operation is completed.

As shown in Figure 4, the result output control module IV includes a result output register 16, an abnormal operation flag control 17, a 32-bit tri-state gate group 18 and an OR gate VI 19;

The calculation result input terminal of the result output register 16 is connected with the calculation result output terminal of the floating-point number division operator II, and the calculation result output terminal is connected with the input terminal of the 32-bit tri-state gate group 18 and the calculation result input terminal of the operation exception flag control 17 terminal, an input terminal of the selector 1 is connected, and the result latch input terminal is connected with the output terminal of the AND gate II 15;

The operation result input end of the operation exception flag control 17 is connected with the operation result output end of the result output register 16, and the result latch input end is connected with the output end of the AND gate II 15; the output end outputs an interrupt request signal IRQ, when the operation result occurs When abnormal, the output terminal sends an interrupt request signal IRQ to the system;

The control input end of the 32-bit tri-state gate group 18 is connected to the output end of the OR gate VI 19, and the output end is connected to the system data bus DB;

The two input terminals of the OR gate VI19 are respectively connected to the system enable signal CS and the read signal RD line;

The 32-bit tri-state gate group 18 outputs the operation result output by the output register 16. When the enable signal CS is "0" and the read signal RD is "0", the output of the OR gate VI19 is "0", and the control 32 Bit tri-state gate group 19 outputs the last operation result.

As shown in Figure 2 and Figure 3, the floating-point operand configuration control module I and the pulse generation distribution controller III are controlled by the system operand type and operation mode:

When the operand type is "0": the gate 1 outputs the operation result output by the result output register 16, and under the action of the falling edge of the pulse ① output by the pulse generator 9, the operation result register 2 latches the result output register 16 to output The result of the operation, the output terminal of the OR gate II7 changes from "1" to "0", the output terminal of the AND gate I8 changes from "1" to "0", and the operand register 3 latches the operand from the system bus DB, then the division Operations are processed in the following two ways:

The operation mode is "0": the operation result of the input terminal of the exchange number 1 of the operand switcher 4 is transmitted to the input terminal of the operand 1 of the floating-point number division operator II, and the operand of the input terminal of the exchange number 2 of the operand switcher 4 is transmitted To the input terminal of the operand 2 of the floating-point number division operator II, the floating-point number division operator II implements the calculation of the operation result/operand;

When the operand type is "1": the operation result of the input terminal of the exchange number 1 of the operand switcher 4 is transmitted to the input terminal of the operand 2 of the floating-point number division operator II, and the operation result of the input terminal of the exchange number 2 of the operand switcher 4 The operand is transmitted to the input terminal of operand 1 of the floating-point number division operator II to realize the exchange of two numbers, and the floating-point number division operator II implements the operation of the operand/operation result;

When the operand type is "1": the strobe 1 outputs the first operand from the system bus DB, and under the action of the falling edge of the pulse ① output by the pulse generator 9, the operation result register 2 latches the system bus DB The first operand of the OR gate II7 is "1", and the output of the NOT gate I5 is "0". Under the action of the falling edge of the output pulse ②, the output end of the AND gate I8 changes from "1" to "" 0", the operand register 3 latches the second operand from the system bus DB, then the division operation is processed in the following two ways:

The operation mode is "0": the first operand of the system bus DB at the input end of the exchange number 1 of the operand switcher 4 is transmitted to the input end of the operand 1 of the floating-point number division operator II, and the exchange of the operand switcher 4 The second operand of the system bus DB at the number 2 input terminal is transmitted to the input terminal of the operand 2 of the floating-point number division operator II, and the floating-point number division operator II implements the operation of the first operand/the second operand;

The operation mode is "1": the first operand of the input terminal of the exchange number 1 of the operand switcher 4 is transmitted to the input end of the operand 2 of the floating-point number division operator II, and the operand of the input terminal of the exchange number 2 of the operand switcher 4 The second operand of the system bus DB is transmitted to the input terminal of operand 1 of the floating-point number division operator II to realize the exchange of two numbers, and the floating-point number division operator II implements the second operand/first operand operation.

Claims (5)

1. A floating-point number division execution controller is used to realize two 32-bit floating-point number division operations that meet the IEEE754 standard, and is characterized in that: the execution controller includes a floating-point operand configuration control module (I), a floating-point number Division calculator (Ⅱ), pulse generation distribution controller (Ⅲ) and result output control module (Ⅳ); The floating-point operand configuration control module (I) is connected with the floating-point number division operator (II), the pulse generation distribution controller (III), and the result output control module (IV); The floating-point number division operator (II) is also connected to the result output control module (IV); The pulse generation distribution controller (Ⅲ) is also connected to the result output control module (Ⅳ); The floating-point operand configuration control module (I) configures the floating-point number division operator (II) according to the type of operand and the operation mode, whether the operand 1 of the floating-point number division operator (II) comes from the last operation result, or comes from the floating point of the system data bus DB. Point operands, under the control of the timing pulse output by the pulse generation distribution controller (Ⅲ), complete the selection of operand 1 input by the floating-point number division operator (Ⅱ), as well as the configuration and latching of operand 1 and operand 2 ; The floating-point number division operator (II) operates on the operand 1 and operand 2 output by the floating-point operand configuration control module (I), and outputs the result of the division operation; The pulse generation distribution controller (Ⅲ) sends out the timing pulses configured by operand 1 and operand 2 according to the type of operands according to the condition of starting work, and the operation result of the floating-point division operator (Ⅱ) is latched signal, and the end signal of the division operation; the pulse generation and distribution controller (Ⅲ) automatically starts the work of the pulse generation and distribution controller (Ⅲ) under the condition of satisfying the cycle start; The result output control module (Ⅳ) latches the result of the division operation under the action of the result latch signal output by the pulse generation distribution controller (Ⅲ), judges whether the result of the division operation is abnormal, and the system can read the result of the division operation . 2. The floating-point number division execution controller according to claim 1, characterized in that: the floating-point operand configuration control module (I) includes a gate (1), an operation result register (2), an operand Register (3), operand switcher (4), NOT gate I (5), OR gate I (6), OR gate II (7) and AND gate I (8); One input end of the strobe (1) is connected to the system data bus DB, the other input end is connected to the result output control module (Ⅳ), the output end is connected to the input end of the operation result register (2), and the strobe control The input end is connected with the operand type input line of the system; The latch pulse input terminal of the operation result register (2) is connected to the pulse generation distribution controller (Ⅲ), and the output terminal is connected to the exchange number 1 input terminal of the operand switcher (4); The input end of the operand register (3) is connected to the system data bus DB, the latch pulse input end is connected to the output end of the AND gate I (8), and the output end of the operand register (3) is connected to the operand switch ( 4) The exchange number 2 input terminals are connected; The exchange control input of the operand switch (4) is connected to the input line of the system's operation mode; the output of operand 1 is connected to the input of operand 1 of the floating-point number division operator (II), and the output of operand 2 Connect with the operand 2 input terminal of the floating-point number division operator (II); The input end of the NOT gate I (5) is connected to the operand type input line of the system, and the output end is connected to an input end of the OR gate I (6); The other input end of the OR gate I (6) is connected to the pulse generation distribution controller (III), and the output end is connected to an input end of the AND gate I (8); One input end of the OR gate II (7) is connected to the pulse generation distribution controller (III), the other input end is connected to the operand type input line of the system, and the output end is connected to an input end of the AND gate I (8) connect. 3. The floating-point number division execution controller according to claim 1, characterized in that: the pulse generation distribution controller (III) includes a pulse generator (9), a type register (10), or gate III (11 ), OR gate IV (12), NOT gate II (13), OR gate V (14) and AND gate II (15); The reset input terminal of the pulse generator (9) is connected to the reset Rst line of the system, the start input terminal is connected to the output terminal of OR gate III (11), and the cycle start input terminal is connected to the output terminal of AND gate II (15). , the pulse synchronization input terminal is connected to the system clock Clock line, the type input terminal is connected to the output terminal of the type register (10), the pulse ① output terminal is connected to the latch pulse input terminal of the operation result register (2), or gate II (7) One input terminal of pulse ② is connected with the other input terminal of OR gate I (6) and the latch input terminal of type register (10); the output terminal of pulse ③ is connected with one input terminal of OR gate IV (12) connection; the pulse ④ output terminal is connected to an input terminal of the OR gate V (14), and the operation end output terminal outputs an operation end signal to the system; The input terminal of the type register (10) is connected to the system operand type input line, and the operand type output terminal is also connected to another input terminal of the OR gate IV (12) and an input terminal of the NOT gate II (13); The two input terminals of the OR gate III (11) are respectively connected to the enable signal CS line and the write signal WR line of the system; The output end of the OR gate IV (12) is connected to an input end of the AND gate II (15); The output terminal of the NOT gate II (13) is connected to the other input terminal of the OR gate V (14); The output end of the OR gate V (14) is connected to the other input end of the AND gate II (15); The output end of the AND gate II (15) is also connected to the result output control module (IV); The pulse ①, pulse ②, pulse ③ and pulse ④ output by the pulse generator (9) are synchronized with the system clock Clock, that is, the system clock Clock is the synchronous pulse of the pulse generation and distribution controller (Ⅲ); When the operand type is "0", the pulse generation distribution controller (Ⅲ) under the action of the falling edge of pulse ②, the output state of the type register (10) is "0", and the output state of the OR gate V (14) is " 1” state, under the action of the falling edge of pulse ③, the output of OR gate IV (12) changes from “1” to “0”, then the output of AND gate II (15) also changes from “1” to “0”, as The pulse generator (9) cycle start signal and the result latch signal of the result output control module (IV); When the operand type is "1", the pulse generation distribution controller (Ⅲ) under the action of the falling edge of pulse ②, the output state of the type register (10) is "1", and the output state of the OR gate IV (12) is " 1” state, under the action of the falling edge of pulse ④, the output of the OR gate V (14) changes from “1” to “0”, then the output of the AND gate II (15) also changes from “1” to “0”, as The pulse generator (9) cycle start signal and the result latch signal of the result output control module (IV); When the operation end output terminal of the pulse generator (9) is "0" and CS is "0", under the action of the falling edge of the WR signal, the signal at the start input terminal changes from "1" to "0", and the start pulse The generator (9) works, and after the pulse generator (9) is started to work, set the output end of the operation end signal to "1"; if the start input end is "0", the cycle start input end changes from "1" to "0" , start the pulse generator (9) to work; if the signal at the start input terminal is "1", the signal at the cycle start input terminal changes from "1" to "0", and sends an operation end signal to the system, and the pulse generator (9) stops working, The output terminals of pulse ①, pulse ②, pulse ③ and pulse ④ are all in the "1" state, and the output end of the operation is in the "0" state; when the reset input is "0", reset the pulse generator (9), The output terminals of pulse ①, pulse ②, pulse ③ and pulse ④ are all in the "1" state, and the output end of the operation is in the "0" state. 4. The floating-point number division execution controller according to claim 1, characterized in that: the result output control module (IV) includes a result output register (16), operation exception flag control (17), 32-bit tri-state Gate group (18) and OR gate VI (19); The operation result input terminal of the result output register (16) is connected to the output terminal of the floating-point number division operator (II), and the operation result output terminal is connected to the input terminal of the 32-bit tri-state gate group (18) and the abnormal operation flag control ( 17) The operation result input terminal is connected to an input terminal of the selector (1), and the result latch input terminal is connected to the output terminal of AND gate II (15); The operation abnormal flag control (17) result latch input terminal is connected to the output terminal of AND gate II (15); the output terminal outputs an interrupt request signal IRQ, and when the operation result is abnormal, the output terminal sends an interrupt request signal to the system IRQ; The control input terminal of the 32-bit tri-state gate group (18) is connected to the output terminal of the OR gate VI (19), and the output terminal is connected to the system data bus DB; The two input terminals of the OR gate VI (19) are respectively connected to the system enable signal CS and the read signal RD line; The 32-bit tri-state gate group (18) outputs the operation result output by the output register (16). When the enable signal CS is "0" and the read signal RD is "0", the output of the OR gate VI (19) is "0", controls the 32-bit tri-state gate group (18) to output the result of the last operation. 5. The floating-point number division execution controller according to claim 1, characterized in that: the floating-point operand configuration control module (I) and the pulse generation distribution controller (III) are subject to the system operand type and operation mode control: When the operand type is "0": the strobe (1) outputs the operation result output by the output register (16), and under the action of the falling edge of the pulse ① output by the pulse generator (9), the operation result register (2 ) the operation result output by the latch result output register (16), the output terminal of the OR gate II (7) changes from "1" to "0", the output terminal of the AND gate I (8) changes from "1" to "0", The operand register (3) latches the operand from the system bus DB, and the division operation is processed in the following two ways: The operation mode is "0": the operation result of the input terminal of the exchange number 1 of the operand switcher (4) is transmitted to the input terminal of the operand 1 of the floating-point number division operator (II), and the exchange number of the operand switcher (4) 2 The operand at the input terminal is transferred to the input terminal of operand 2 of the floating-point number division operator (II), and the floating-point number division operator (II) implements the calculation of the operation result/operand; The operation mode is "1": the operation result of the input terminal of the exchange number 1 of the operand switch (4) is transmitted to the input terminal of the operand 2 of the floating-point number division operator (II), and the exchange number of the operand switch (4) 2. The operand at the input end is transmitted to the input end of operand 1 of the floating-point number division operator (II) to realize the exchange of two numbers, and the floating-point number division operator (II) performs the operation of the operand/operation result; When the operand type is "1": the strobe (1) outputs the first operand from the system bus DB, and under the action of the falling edge of the pulse ① output by the pulse generator (9), the operation result register (2 ) to latch the first operand of the system bus DB, the output of the OR gate II (7) is "1", and the output of the NOT gate I (5) is "0", under the action of the falling edge of the output pulse ②, The output terminal of AND gate I (8) changes from "1" to "0", and the operand register (3) latches the second operand from the system bus DB, then the division operation is processed in the following two ways: The operation mode is "0": the first operand of the system bus DB at the input end of the exchange number 1 of the operand switcher (4) is transmitted to the input end of the operand 1 of the floating-point number division operator (II), and the operand is exchanged The second operand of the system bus DB at the exchange number 2 input terminal of the device (4) is transferred to the input terminal of the operand 2 of the floating-point number division operator (II), and the floating-point number division operator (II) performs the first operation Operation of number/second operand; The operation mode is "1": the first operand at the input end of the exchange number 1 of the operand switcher (4) is transmitted to the input end of the operand 2 of the floating-point number division operator (II), and the operand switcher (4) The second operand of the system bus DB at the input end of the exchange number 2 is transmitted to the input end of the operand 1 of the floating-point number division operator (II) to realize the exchange of two numbers, and the floating-point number division operator (II) implements the second operand operand/first operand operation.